VLSI Engineering

engineering & Technology
yo u r U C i n S i l i c o n Va l l e y
VLSI
Engineering
UCSC Silicon Valley Extension offers the VLSI
(Very Large Scale Integration) Engineering
Certificate Program for professionals working in
the integrated circuit, ASIC, semiconductor, EDA,
device and system industries. With more than 20
UC-quality courses, our VLSI program is the most
complete integrated circuit curriculum available in
Silicon Valley. Students gain practical experience
using the latest EDA tools on Linux in our stateof-the-art VLSI Lab. Our expert faculty teaches
hardware specification, logic design, verification,
synthesis, physical implementation, circuit design,
and testing of integrated circuit products.
ucsc-extension.edu/
engineering
*
VLSI Engineering Certificate
Certificate Requirements
To obtain the Certificate in VLSI Engineering,
you must successfully complete a total of 14 units,
including two of the five core courses.
GPA: 3.0 with a C or better in all courses.
Prerequisites
You will need a degree in a technical field or
equivalent knowledge acquired through training and
experience in hardware design and development.
Experience with UNIX and/or Linux is required for the
lab sessions. Knowledge of a programming language
(e.g., C, Perl or Bash Shell) may be helpful.
Recommended Course Sequence
It is recommended that you take at least one course
from the ‘Design Methodology’ category. Other
courses can be taken based on your interests and
professional level. For beginners, take ‘Introduction’
courses before ‘Advanced’.
Note: Some courses may be listed in more than one
program, however, only one course may be shared
between two Engineering and Technology certificate
programs unless otherwise noted.
Program Contact
Engineering and Technology Department,
(408) 861-3860 or email
[email protected]
This course focuses on the use of advanced verification
features in SystemVerilog, the new IEEE-1800
standard combining the hardware description
14 unit minimum
language and hardware verification language.
You’ll gain experience developing an industrial*Choose two of these five core courses
UnitsCourse
strength object-oriented programming (OOP)
testbench. The course starts with building flexible
Design Methodology
testbench components, and continues with functional
Developing the Nanometer ASIC
coverage to round up the development of a complete
from Spec to Silicon................................... 2.0.........3497
Verification Environment. The objective is to become
Designing Xilinx CPLDs and FPGAs,
familiar with the flexibility of an OOP-centric techIntroduction............................................... 3.0.........6346
nique, the power of constrained random verification
Logic and Functional Design
and the use of functional coverage tools. Concepts
*Digital Logic Design Using Verilog............. 3.0.........0764
introduced in class are reinforced in the lab.
Curriculum
Logic Synthesis, Introduction..................... 3.0.........4377
*Practical DFT Concepts for ASIC:
With Nanometer Test Enhancements......... 3.0.........5373
IO Concepts and Protocols: PCI Express,
Ethernet, and Fibre Channel...................... 3.0.......22177
Digital Design with FPGA.......................... 3.0.......30207
SystemVerilog and Verification
SystemVerilog Essentials:
Functional Verification and Simulation...... 1.5.........6932
SystemVerilog for ASIC and FPGA Design... 3.0.......20095
SystemVerilog Assertions
and Formal Verification.............................. 3.0.......20062
*Advanced Verification with
SystemVerilog OOP Testbench................... 3.0.......18966
System and Functional
Verification Using UVM (Universal Verification Methodology)........ 3.0.........0027
Physical Design and Timing Closure
*Physical Design Flow from
Netlist to GDS-II..........................................3.0.........4436
ASIC Physical Design, Advanced................ 3.0.........0634
Timing Closure in IC Design....................... 3.0.........4775
Circuit Design
Low-Power Design of Nano-Scale
Digital Circuits........................................... 3.0.......21941
*Analog IC Design, Introduction.................. 3.0.........3799
Enrollment Information
Visit ucsc-extension.edu/engineering for
the most up-to-date information about our
courses and programs, including textbooks,
instructors, schedules and locations.
Enroll online at ucsc-extension.edu.
Advanced Verification with
SystemVerilog OOP Testbench
Course 18966
*
Analog IC Design, Introduction
This course introduces analog IC design fundamentals
including single/multiple-transistor amplifiers, current
mirrors, current/voltage reference, output stages,
frequency response, feedback, stability, noise, nonlinearity, and mismatches. Transistor models and
CAD tools for analog design are also covered. You will
gain a basic understanding of analog IC design and
become familiar with circuit analysis and simulation
tool flow. These fundamentals will prepare you to
tackle advanced analog IC topics such as Op-amp,
PLL, ADC and DAC.
Course 3799
ASIC Physical Design, Advanced
This lab-based course covers advanced topics of
ASIC front-to-back design automation and provides
a 28nm library for you to practice techniques learned
in class. The instructor covers UPF-based synthesis
and placement, and gives an example of congestion
analysis and reduction. You will learn the CTS and how
to optimize timing sign-off. The course also introduces
hierarchical design flow, power mesh synthesis, and
IR drop analysis. You’ll further develop advanced
ASIC design skills with state-of-the-art EDA
back-end design tools and methodology.
Mixed-Signal IC Design............................. 3.0.........1999
Course 0634
IO Design Fundamentals............................ 3.0.......30170
Comprehensive Signal and Power
Integrity for High-Speed Digital Systems
PLL and Clock/Data Recovery Circuits........ 3.0.........2283
Wireless and Mobile Communications,
Introduction............................................... 3.0.........5455
Jitter Essentials.......................................... 1.5.......21321
Comprehensive Signal
and Power Integrity for
High-Speed Digital Systems....................... 3.0.......22874
Copyright © 2015 The Regents of the University of California. All rights reserved.
This course covers signal and power integrity analysis
of high-speed digital systems, and the modeling and
design techniques used in high-speed links (in board,
package, and connector). The instructor introduces IO
modeling including IBIS, behavioral, functional, and
ESD. You’ll also learn concepts of equalization design
This free event is an informal session for new or returning students who are interested in our Embedded Systems and VLSI Engineering certificate
program staff will be available to answer your questions, help you select courses and plan a course sequence that fits your goals. This is an excellent
opportunity to receive course counseling for upcoming quarters. Register early to reserve your space.
Course 22403
To learn more, visit ucsc-extension.edu/events.
and signaling techniques such as differential, NRZ,
and pulse. At the system level, you’ll learn about
clocking schemes such as PLL, DLL and CDR; timing
jitter analysis; and power analysis topics such as IR
drop, AC noise, simultaneous switching noise and
decoupling capacitor.
Course 22874
Designing Xilinx CPLDs and FPGAs,
Introduction
This course is a practical introduction to programmable
logic design with Xilinx FPGAs and CPLDs. You will
walk through a complete PLD design, using several
examples and design techniques. Upon completion of
the course, you should be able to complete a design
with Xilinx CPLDs and FPGAs, and understand the
design and timing reports. The course also covers
logic design process review, design software, Xilinx
CPLDs and FPGAs architecture, design techniques and
optimizing, JTAG, power optimization and large design
techniques. The course includes two student projects.
Course 6346
Developing the Nanometer ASIC: From
Spec to Silicon
This course covers each step in developing an ASIC,
explaining key concepts such as transistor action,
standard cells, RTL synthesis, meeting timing, functional coverage, formal equivalence, physical design,
signal integrity, DFT and BIST, tape-out, IC fabrication,
and emerging packaging trends. The course includes
hands-on “quick tour” labs to familiarize you with the
use of EDA tools. The focus is on mostly-digital ASICs
with multiple IP cores, low-power goals, and on-chip
RF-CMOS/analog blocks.
Course 3497
Digital Design with FPGA
This course provides the knowledge and hands-on
experience needed to design digital logic blocks in
FPGA. The course introduces how to build designs in
FPGA and covers specific designs of various digital
blocks. Starting from combinational logic, look-up
tables, carry chains, and multiplexers, you will learn to
design and test arithmetic and comparator functions
using FPGA. The instructor explains various sequential
flops, fast counters and shift register look-up. The
course also explores the embedded RAM, ROM and
finite state machine designs using Xilinx architecture.
Course 30207
Session
programs. You’ll learn the program objectives, requirements and the technical skills you’ll gain by studying with us. In addition to general Q&A,
Info
Info Session for Embedded Systems and VLSI Programs
Digital Logic Design Using Verilog
Jitter Essentials
This course will prepare you to implement Verilog
modeling of digital logic. You will learn Verilog
constructs and hardware modeling techniques, Verilog
language elements and data types. You will tackle
key challenges and learn structural, dataflow and
behavioral modeling in Verilog, including common
constructs and coding considerations. The instructor
includes coding and testing examples of combinational circuits (gates, mux/demux, encoders/decoders,
and Boolean expression), sequential circuits (latches,
flip-flops, shift registers, counters, RAMs and ROMs),
and complex logic (flavors of ALU and FSM).
Learn the definitions of various types of jitter
(including phase noise), understand which type of
jitter is important to your application and why, plus
learn how to propagate jitter through a system, create
jitter budgets, measure and minimize jitter. This course
emphasizes developing a working knowledge of jitter,
such as establishing a common language, understanding jitter beyond the definitions, gaining insight
by making simplifying assumptions, and visualizing
relationships between different types of jitter.
*
Course 0764
IO Concepts and Protocols: PCI Express,
Ethernet, and Fibre Channel
This course focuses on IO technologies and walks
you through the complexities of IO subsystems in
modern computers, and the networking and storage
subsystems to which they are attached. After an
introduction to the basic concepts of IO, we will delve
into the details of PCI Express, Ethernet and Fibre
Channel. Discussions will include operation, protocols,
and an exploration of how these technologies work.
We will follow an application’s IO request all the
way from the system call, to when the data actually
makes it out of the wire.
Course 22177
IO Design Fundamentals
This course is an introduction to IO interfacing at
chip and board levels. It covers the advantages and
disadvantages of TTL, CMOS, low-voltage CMOS,
LVDS and optical interfaces. The course emphasizes
fundamental concepts such as transmission line
analysis, slew rate and termination. It introduces
basic IO logic, timing analysis and package models.
You’ll also learn about bit error rate, bi-directional
IO and decision feedback filters. Because most
solutions are silicon-based, ESD concepts and
techniques will also be discussed.
Course 30170
Course 21321
Logic Synthesis, Introduction
This course outlines various concepts of logic synthesis.
Starting with the basics of synthesis, the course explains
the Synopsys tools and their use in synthesizing
high-level language into gates. It also covers various
options such as partitioning, design, gate-level optimization, time/area constraints and library management.
The course is intended for design engineers with
some knowledge of hardware description languages
such as Verilog HDL or VHDL. It is a lab-based
course with hands-on exercises.
Course 4377
Low-Power Design of Nano-Scale Digital
Circuits
This course introduces advanced topics in nano-scale
(below 90nm) VLSI device and circuit design. Highperformance and low-power design issues in modern
and future nano-scale CMOS technologies are
discussed in detail. You will learn low-power design
approaches and techniques at different levels of
abstraction. New design techniques are introduced
to deal with nano circuit designs under excessive
leakage and process variations. You’ll also explore
several non-classical CMOS devices for circuit design
in such technologies, and review prospects of future
non-silicon nanotechnologies.
Course 21941
Mixed-Signal IC Design
Practical DFT Concepts for ASICs:
With Nanometer Test Enhancements
SystemVerilog Essentials: Functional
Verification and Simulation
This hands-on course is ideal for IC designers seeking
a deeper understanding of test issues and test
engineers wanting to stay current with emerging
trends and tools. You will gain hands-on experience
building scan chains and generating test patterns
using Synopsys DFT Compiler (DFTC) and TetraMAX
ATPG. Advanced topics include building multiple scanchain insertion, employing sequential ATPG, optimizing
DFT logic, and understanding LBIST and MBIST.
By the end of the course, you will be able to hand
off a full-scan design and generate a high-coverage
test program for nanometer ASIC.
This lab course introduces the digital simulation
process with hands-on exercises using the simulation
tool. The instructor discusses simulation techniques
such as coding style, event ordering, delta cycle
debugging, zero width glitch, race conditions, time
slices, conditional compilation, simulation performance
and code coverage. SystemVerilog essentials include
new data types, interfaces, classes, randomization,
and overview of assertions. The course offers examples
to show how these tools help designers with code
compaction and system verifications.
*
This course will help you understand basic analog
circuits and systems, and problems encountered when
analog circuits share substrate with digital circuits.
You will also learn precautionary measures and
techniques used to circumvent these problems. Topics
include MOS transistors, basic analog building blocks,
phase-locked-loop circuits, sample and hold circuits,
comparator design, A/D and D/A converters, and
layout considerations in mixed-signal circuits.
The course is intended for practicing engineers and
design managers who want to understand analog
circuit and layout techniques in mixed-signal IC design.
Course 1999
Physical Design Flow from Netlist
to GDS-II
Course 5373
*
This course is an introduction to ASIC physical design
flow and tools from netlist to GDS-II. The course
starts with floor planning and block pin assignment.
The instructor then addresses placement and clocktree synthesis, followed by routing, and post-route
optimization. You will learn RC extraction, static timing
analysis, and physical verification. Upon completion
of the course, you will possess the essential knowledge
and hands-on experience with the back-end physical
design flows, from a synthesized netlist all the way
to layout completion for ASIC chip tapeout.
Course 4436
PLL and Clock/Data Recovery Circuits
Phase-locked-loop (PLL) circuits are used extensively in
system and chip designs for frequency multiplication,
data extraction, and re-timing purposes. This course
provides the knowledge required for analysis and
design of PLL circuits and their applications in clock
and data-recovery circuits. The instructor will discuss
various components involved in the design of a PLL
circuit. Topics include transceiver design, high-speed
I/O, ring and LC oscillators, charge-pump PLL, practical
issues at transistor-level design, noise and jitter in PLL,
delay-locked loop, frequency multiplier, and clock
and data recovery circuits.
Course 2283
System and Functional Verification Using
UVM (Universal Verification Methodology)
Universal Verification Methodology (UVM) is the
industry standard for functional verification methodology. This course introduces the UVM architecture,
its core set of base-classes and utility methods, and
associated factory automation techniques. The main
base classes covered are the UVM test classes,
sequence classes, component classes, messaging
and reporting mechanism, factory, configuration
database, transaction-level modeling (TLM), scoreboarding, coverage and phasing mechanism. Through
labs, take-home assignments, and a team project,
you’ll learn the power of UVM for successfully
designing complex constraint-random coverage
driven verification projects.
Course 0027
SystemVerilog Assertions and Formal
Verification
This course introduces SystemVerilog Assertion (SVA)
concepts and syntax, using small examples and a
realistic design. It covers the OVL checker library,
writing and debugging assertions. The second part
of the course introduces formal verification theory
and tools. You will learn FV application in several
design stages and in different functional areas, such
as SoC connectivity, coverage closure, and xpropagation checks. This course addresses key topics
in detail, from language constructs to assertion coding
guidelines with practical examples of how to use
assertions in verification.
Course 20062
Course Planning Session
Register online for a complimentary one-on-one session.
Course 30371
Not printed or mailed at state expense. 611796-1502-2086 (5/15/15)
Course 6932
SystemVerilog for ASIC and FPGA Design
This course prepares hardware engineers, ASIC and
FPGA designers, and design-support staff to use the
high-level syntax of SystemVerilog to design, debug,
and synthesize digital logic for ASICs, FPGAs, and IP
cores. You’ll learn SystemVerilog’s basic building blocks
and language constructs, including synthesizable data
types and operators, structures and unions, 2-D arrays
and loops, and the bus interface unit. In lab sessions,
you will write code and synthesize it into digital logic
and bus fabric, using both ASIC and FPGA tools.
Course 20095
Timing Closure in IC Design
This lab course begins with basic timing concepts
and STA methodology. You will learn what needs to
be timed and how to setup a run for STA. The course
exposes students to constraints, exceptions and “what
if” analysis. It also explains how to address timing
violations in ECO mode. You’ll also learn about nanotechnology topics, including noise analysis, prevention
and on-chip variations. The instructor shares practical
experiences meeting timing closure, budgeting and
debugging. The course uses primetime tools and test
cases for hands-on practical experience.
Course 4775
Wireless and Mobile Communications,
Introduction
This course builds an understanding of the various
wireless standards and techniques in use today,
beginning with a review of traditional amplitude
modulation (AM), frequency modulation (FM), and
single sideband (SSB). After covering the foundation
technologies, the course analyzes present-day digital
modulation schemes, including OFDM, TDMA and
CDMA. The course covers current wireless standards,
including, but not limited to, IS-136, IS-95, Bluetooth,
3G, 4G, 802.11, and LTE. Additional discussions
address antenna and transceiver design principles
and implementation in today’s mobile devices.
Course 5455