Nanostructures for Memory Devices and Bio-Sensors KAIST September 27, 2006

Nanostructures for Memory
Devices and Bio-Sensors
KAIST
(Department of Electrical Engineering)
September 27, 2006
Yang-Kyu Choi
NanO-Bio-Electronic Laboratory
KAIST
Outline
1. Sub-5nm FET Fabrication
2. Nanodots for Non-volatile Memory
3. Nanogap Devices for DNA Chips
4. Nano-Chestnut for Bio-Sensors
5. Summary
KAIST
Why Novel Structures?
Tbody
Gate
Gate
Gate
Source
Source
Drain
Source
Drain
Drain
BOX
Body/Halo Doping
Gate
Substrate
Bulk
Ultra-Thin Body
G
S
D
Fluid analog
KAIST
Double-Gate
FinFET
(Fin Field Effect Transistor)
in
e
in
a
r
D
ra
at
e
t
a
G
D
C
ur
r
en
t
ur
ce
e
c
r
u
So
So
n
i
F
G
Fin
KAIST
Pinchcock
Evolution of Transistor
G
S
G
D
S
D
Fin
Fin
Fin
Double gate
Ω-gate
All-around
Buried Oxide
Bulk-single gate
SOI single gate
No report for
Sub-50nm
LG=4nm
NEC
IEDM 2003
LG=8nm
IBM
IEDM 2003
LG=10nm
AMD/Berkeley
IEDM 2003
KAIST
LG=10nm
LETI
VLSI 2005
We did it!
Sub-5nm AAG FinFET
Gate
Before
LG=5nm
gate spacer
formation
Source
Drain
Source
WFin=3nm
Gate
Gate
Gate
Drain
KAIST
World Record Smallest Si FET (3nm)
Source
Gate
Gate
Drain
KAIST
Sub-5nm AAG FinFET: Gate
Poly-si
5nm
HfO2
IFO
5nm
Poly-si
Gate
Source
Gate
Gate
Si
Drain
Silicon fin
KAIST
5nm
Drain Current [A/µm]
1x10
1x10
10
10
-3
Simulated
Measured
160
VD=1.0V
140
-4
VD=0.2V
-5
DIBL=230mV/V
SS=208 mV/dec
HfO2 =1.4nm
LG=5nm
WFin=3nm
-6
-7
-1.0
-0.6
-0.2
0.2
0.6
120
100
80
60
40
20
0
1.0
Transconductance [µS/µm]
10
Drain Current [µA/µm]
I-V of Sub-5nm AAG FinFET
Gate Voltage [V]
350
HfO2 =1.4nm
LG=5nm
250 W =3nm
Fin
200
300
0.6V
0.4V
150
VG=0.2V
100
50
0
0.0
0.2
0.4
0.6
0.8
Drain Voltage [V]
Electrically 5nm FinFET (3D SILVACO)
Large DIBL and SS due to thick EOT
ITRS requirement: 0.5nm EOT for DG
KAIST
1.0
CMOS Scaling Scenario
70nm 45nm 25nm
2002 2005 2008
18nm 10nm (Lg)
2011 2014
S
G
D
Bulk
G
S
UTB
D
BOX
G
Multiple-Gate
(FinFET)
S
D
G
KAIST
Nanosphere Lithography
Nanobeads
Metal Evaporation
Metal Lift-off
Cross-sectional View
Top View
R.P. Van Duyne, J. Phys. Chem. B., 1999
KAIST
Metal Nanodots by Nanosphere Lithography
D d=0.23D
500nm PS Nanobeads
110nm PS Nanobeads
d=115nm metal dots
d=25nm metal dots
• Bead Diameter : D
• Metal Dot Size :
d = 0.23D
• Density =
4
3D2
• Density = 9.2x1011/cm2
• Density = 1.9x1011/cm2
• Well ordered 25nm metal dots are achieved.
KAIST
Nanodots for
Flash Memory
Before IPA
1.0
Dipping
Ti Metal Nanodot
50µmX50µm Pad
∆VT [V]
C/CMAX
1.5
1.0
0.5
0.0
-2
D
P-Type Substrate
TTunneling=5nm(SiO2)
TControl=30nm(HfO2)
2.0
P-Type Substrate
TTunneling=5nm(SiO2)
TControl=30nm(HfO2)
-4
NFGM
(Flash Memory)
2.5
∆VT
0.4
0.2
S
3.0
0.8
0.6
Gate
0
2
4
0.0
30X30
50X50
100X100
2
VTOP [V]
Top Electode Size [µm ]
Hysteresis ( ∆VT ) >1.5V.
No device size dependence → Well-ordered nanodots
KAIST
Chemical Synthesis and Thermal Decomposition
Ni
Target=3nm
2~5nm/2.4X1012cm-2
XRD Analysis
Ag
24
22
20
18
16
14
12
10
8
6
4
2
Ag (111)
Ag (200)
Ag (220)
30
100nm
40
q
20nm
AgNO3 20mmol / Oleylamine 1L*
heating the mixture at 130'C for 2hours
Intensity(a.u.)
AgNO3 50mmol / Oleylamine 1L*
heating the mixture at 130'C for 2hours
50
60
2 (deg)
5~8nm/5.8X1011cm-2
• High Ag NC density:~1012cm-2
• Acceptable NC size and dot-to-dot distance : ~3nm/~4nm
• Controllable Ag NC size by AgNO3 concentration
• No Ag Oxidizing
KAIST
70
Ag (311)
80
Thermodynamic Agglomeration
XRD After 24h
After Annealing
Au (111)
4
10
Intensity (a.u.)
Au
Target=3nm
3
Si (400)
Au (200)
10
3~8nm/
2
10
Au (220)
Au (311)
Si (400)
Si (200)
8.8X1011cm2
1
10
20
30
40
50
60
70
80
2θ (deg)
Pt
Target=3nm
Ni
Target=3nm
Si (400)
Pt
3~14nm/
11cm4.7X10
2
4
Intensity (a.u.)
S
P
U
T
T
E
R
I
N
G
E
V
A
P
O
R
A
T
O
R
Size/Density
10
3
10
Si (200)
Si (400)
2
10
Ni (200)
Ni (111)
1
10
20
30
40
50
2θ (deg)
KAIST
60
70
80
Ni
3~7nm/
12cm1.2X10
2
Double-Stacked Nanodot Memory
C-V Hysteresis
Retention Time
P/E Efficiency
Ag
12
4
4
DSNC embedded MOS capacitor
w/o Ag NCs
tinter=6nm(HfO2)
12
9
6
∆Vfb=300mV
6
1
0
-1
3
4
2
3
Ag SNC
Ag DSNC,TInter=2nm
Ag DSNC,TInter=6nm
VFB Shift [V]
8
3
VFB Shift [V]
Capacitance [pF]
+7/-7V tcontrol=23nm(SiO2)
+9/-9V ttunnel=4.5nm(SiO2)
tinter=2nm(HfO2)
+1/-1V
+3/-3V
+5/-5V
10
0
-12 -8 -4 0 4 8 12
-2
2
-3
0
3
6
Gate Voltage [V]
9
12
15
-4
DSNC with tinter=2nm
P/E Voltage: +9/-9V
DSNC with tinter=6nm
2
P/E Voltage:+11/-13V
1
τP/E=1sec
0
-1
-3
-6
Programmed state
Ag SNC
P/E Voltage:+9/-9V
Erased state
-15 -12 -9 -6 -3
0
3
6
9
Program Voltage [V]
12 15
-2
0
10
1
10
2
10
3
10
4
10
5
10
6
10
Retention Time [sec]
‰ Interfacial dielectric(HfO2) thickness
ÆTrade-off between program/erase(P/E) efficiency & retention time
‰ Double-stacked Nanocrystals(DSNC) with 6nm interfacial HfO2 layer
ÆWide memory window(>1.5V) & conspicuously extended retention time
Æ Reduced charge loss rate compared to single NCs(SNC) case
KAIST
7
10
8
10
Nanodot Memory Characteristics
<D>avg=3nm,
Density=2.4x1012cm-2
VG-Vth=1.5V
w/o NCs
L/W=1.6µm/50µm
1.2V
2.4
Thermal Decomposition (Ag NCs)
-4
10
ttunnel=4.5nm tcontrol(HfO2)=30nm
L/W=1.4um/50um
-5
10
0.9V
1.6
ID [A]
ID [µ A/µ m]
3.2
-6
10
10
-8
∆Vth=0.7V
10
0.6V
-9
10
-7
0.8
0.0
+7/-7V
+9/-9V
-7
10
-6
0.3V
10
-4 -2 0 2 4 6 8 10
+3/−3V
+7/−7V
-8
0
1
2
3
10
VD [V]
-4
-2
0
2
4
6
+5/−5V
+9/−9V
8
VG [V]
Gate Voltage vs. Drain Current
(Double Sweet Mode)
Drain Voltage vs. Drain
Current For different Gate
Voltages
KAIST
10
Fatigue Characteristics
3
2.4
LG=1.6um
LG=2um
LG=8um
0.8
0.0
2
Programmed and erased
@VG=+9/-9V
τp(Program time))=τe(Erase time)=80µs
∆ Vth [V]
∆ Vth [V]
1.6
1
0
-0.8
-1
-1.6
-2.4
0
10
1
10
2
10
3
10
4
10
5
10
6
10
data "1"
Cycling and readout pulse
+9/-7V, 80µsec
W/L = 10/2um
tcont.(HfO2)=30nm, ttunnel.(SiO2)=4.5nm
data "0"
-2 -1
0
1
2
3
4
5
6
7
8
10 10 10 10 10 10 10 10 10 10
Retention time [sec]
Program/Erase Cycles
• Retention : △Vth=1.2V after 104 second
• Endurance Characteristic : Program/Erase cycling larger than 107 times
KAIST
Nanodot Non-Volatile FinFET
3D Structure
Cross-sectional Images
Electrical Characteristics
6.0
Ag
Al-Gate
HfO2=30nm
Au NCs
0.1um
p-Substrate
Oxide
hard mask
+9/-9V
+7/-7V
+5/-5V
+3/-3V
4.5
4.0
∆Vfb=0.5V
3.5
Gate
Gate
p--Si body
Gate
20um
tside_wall=3µm
tcontrol=30nm(HfO2)
ttunnel=4.5nm(SiO2)
5.0
Gate
Ox. Hard mask
3um
w/o Au NC MOS Capacitor
5.5
Capacitance [pF]
Top Gate (Al)
3.0
p--Si body
-9
-6
-3
0
3
6
Gate Voltage [V]
9
5.0
w/ Au NCs embedded MOS Capacitor
HfO2=30nm
p--Si body
p--Si body
Capacitance [pF]
θ=87
°
Au NCs
3um
Oxide
hard mask
Gate
Tun. Ox. (4nm)
Gate
Gate
ttunnel=4.5nm(SiO2)
tcontrol=30nm(HfO2)
tside_wall=3µm
4.5
4.0
3.5
3.0
+11/-11V
+9/-9V
+7/-7V
+3/-3V
-12 -9 -6
-3
0
3
6
Gate Voltage [V]
KAIST
9
12
Nanodot Non-Volatile FinFET
NCs on the side wall
Cross-Section
‰Size:3~5nm
‰Density:6.3X1011cm-2
Air
NCs
Si-Substrate
‰ Au Nanocrystals on the side wall
of silicon vertical structure
KAIST
Poly-Si Nanogap by Spacer Lithography
SiO
SiO
Poly-Si I
Poly-Si I
SiN
Spacer Deposition
Poly-Si II
Spacer
Poly-Si I
SiN
SiN
Patterning
SiO
Spacer
Etch Back
Poly-Si (II)
Poly-Si (I)
Nano-Gap
Si3N4
SiO
Poly-Si I
Poly-Si II
Poly-Si I
SiN
2nd Poly-Si deposition
SiN
CMP and removal of spacer
KAIST
DNA Chip Configuration
PDMS Microfluidic Channel
ow
Fl
D
n
tio
c
ire
Inlet
Magnified Nanogap
Junctions Image
a
a’
Addressable
Electrode
Common Ground
Outlet
KAIST
Sub-8nm Gap of Poly-Si Electrodes
G
Poly-Si
Poly-Si
G
Opened channel
Si
Si
Sub-8nm
7nm
ion channel
gap
Nitride
Poly-Si
Opened channel
Top View
Poly-Si
Fluid
opened fluidic channel
7.7nm Gap width
< 8nm
KAIST
DNA Hybridization in Nanogap
Inside view
Top view
KAIST
Detection of DNA Hybridization
400
400
SAM
Immobilization (T)
Hybridization (T-A)
300
350
Capacitance (pF)
Capacitance (pF)
350
250
T
200
A
150
300
250
50
50
10
3
4
5
10 10 10
Frequency (Hz)
6
10
G
150
100
2
T
200
100
0
1
10
SAM
Immobilization (T)
Hybridization (T-G)
7
10
0
1
10
Y.-K. Choi et al., MRS, p.185, April 2002
KAIST
2
10
3
4
5
10 10 10
Frequency (Hz)
6
10
7
10
Nano-Chestnuts
a
b
c
Y.K. Choi et. al., Nanotechnology (2006)
KAIST
Nano-Chestnuts (Cont’d)
a
c
b
d
KAIST
Net structure
Bio-Sensor Application
9.0u
Current (A)
6.0u
SWCNT/PS electrode
bare Au electrode
SWCNT electrode
3.0u
0.0
-3.0u
-6.0u
-9.0u
-400
(a)
-200
0
200
400
600
800
Potential (mV)
• Potential windows for bare gold, SWCNT, and SWCNT/PS electrode
in 5×10-4 mol/L potassium ferrocyanide (K3Fe(CN)6/PBS)
KAIST
Summary
1. Sub-5nm Si FET was demonstrated.
2. Nanodots were formed for non-volatile memory devices.
3. Sub-lithographic nanogap devices were fabricated
for DNA chips.
4. Nano-chesnuts were formed for bio-sensors.
KAIST