Nonlinear Equalization Processor q IC for Wideband Receivers and Sensors

Nonlinear Equalization
q
Processor
IC for Wideband Receivers and
Sensors
William S. Song, Joshua I. Kramer, James R. Mann,
Karen
a e M. Gett
Gettings,
gs, G
Gil M. Raz,
a , Joe
Joel I. Good
Goodman,
a ,
Benjamin A. Miller, Matthew Herman, Thomas B.
Emberley, Larry L. Retherford, Albert H. Horst
HPEC 2009
RESEARCH & TECHNOLOGY, INC.
23 September 2009
This work was sponsored by DARPA under Air Force Contract FA8721-05-C-0002.
FA8721 05 C 0002. Opinions, interpretations, conclusions
and recommendations are those of the authors and are not necessarily endorsed by the United States Government.
MIT Lincoln Laboratory
HPEC 2009-1
WSS 9/23/2009
Outline
•
Introduction
– Nonlinear Equalization (NLEQ) applications
– NLEQ program objective
•
•
•
•
HPEC 2009-2
WSS 9/23/2009
NLEQ processor architecture
VLSI NLEQ processors
Performance demonstration results
Summary
MIT Lincoln Laboratory
High Dynamic Range Requirements for
Military and Commercial Sensor Systems
Radar Receiver System
Interference + Noise
Environment
Radar Receiver System Example
Radar
Jamming
Jammer
Clutter
Power (dB
B)
Target
Dynamic
Range
g
80->100 dB
Noise
Small targets at or
below noise level
Range
•
Radar, ELINT, SIGINT, Comm receiver systems must support high
dynamic range operation
–
–
HPEC 2009-3
WSS 9/23/2009
To detect small targets/signals in interference/clutter environment
High signal-to-noise ratio and linearity required
MIT Lincoln Laboratory
Linearity Concerns in Highly Digitized
Arrays and Frequency Channelized Systems
•
Digital Sensor Array
Noise
Intermods
Two-tone
input
Intermods
ods
Frequency
Power
Two-tone
input
•
Power
Power
Receiver
ADC
Receiver
ece e
ADC
C
Receiver
ADC
Receiver
ADC
Receiver
ADC
Receiver
ADC
Receiver
ADC
Receiver
ADC
Digital beamforming and
frequency channelization
increase in-band signal-tonoise ratio (SNR)
Non-linearity generated spurs
and intermods can interfere
with small signal detection
Noise
Two-tone
input
Intermods
ods
Frequency
Noise
Frequency
Signal
ADC
Frequency
Channelizer
Frequency Channelized Receiver
HPEC 2009-4
WSS 9/23/2009
Power
Receiver
In-Band
Noise
Out-of-Band
Noise
Frequency
FNyquist
MIT Lincoln Laboratory
Nonlinear Equalization (NLEQ)
Digital Receiver N
Digital Receiver 1
From
Antennas
Rec
LNA
A/D
Digital
Signal
g
Processor
Sources of
Nonlinearities
HPEC 2009-5
WSS 9/23/2009
MIT Lincoln Laboratory
Nonlinear Equalization (NLEQ)
Digital Receiver N
Digital Receiver 1
Rec
A/D
LNA
Digital
Signal
g
Processor
Sources of
Nonlinearities
Powerr (dB)
Before Equalization
In-Band
Intermodulation
Distortions
Frequency (bin)
HPEC 2009-6
WSS 9/23/2009
MIT Lincoln Laboratory
Nonlinear Equalization (NLEQ)
Digital Receiver N
Digital Receiver 1
From
Antennas
Rec
A/D
Nonlinear
Equalizer
LNA
Sources of
Nonlinearities
Inverts
Nonlinearities
After Equalization
Frequency (bin)
HPEC 2009-7
WSS 9/23/2009
Power ((dB)
Powerr (dB)
Before Equalization
In-Band
Intermodulation
Distortions
Digital
Digital
Signal
Signal
Processor
Processor
Dynamic range
improvement
Frequency (bin)
MIT Lincoln Laboratory
Nonlinear Equalization (NLEQ)
Digital Receiver N
Digital Receiver 1
From
Antennas
Rec
A/D
LNA
Sources of
Nonlinearities
Nonlinear
Equalizer
Digital
Signal
g
Processor
•
•
HPEC 2009-8
WSS 9/23/2009
SFDR/IFDR
@500MHz BW
>1 Teraops
< 2 Watts
After Equalization
Power ((dB)
Powerr (dB)
Frequency (bin)
Digital
Digital
Signal
Signal
Processor
Processor
Inverts
Nonlinearities
Before Equalization
In-Band
Intermodulation
Distortions
+20~25 dB
Dynamic range
improvement
Frequency (bin)
Nonlinear equalizer processor can reduce nonlinear distortion
g and mixed signal
g
circuitry
y
levels in analog
Equivalent to having devices 10-20 years ahead of their time
MIT Lincoln Laboratory
Outline
•
•
Introduction
NLEQ processor architecture
– Processor architecture
– Architecture optimization
•
•
•
HPEC 2009-9
WSS 9/23/2009
VLSI NLEQ processors
Performance demonstration results
Summary
MIT Lincoln Laboratory
NLEQ Polynomial Nonlinear Filter
Architecture
Pass-through
Z-α
Pass-through
Σ
•
Processing Elements
Z-ββ
FIR
X
Z-β
FIR
X
-β
Z
FIR
X
-γ
Z-β Z 1
FIR
X
-γ
γ
1
Z
Z-γ1
Z-γ1
-γ
Z Ν
Z-γΝ
Z-γΝ
Z-γΝ
HPEC 2009-10
WSS 9/23/2009
Σ
Parameters to optimize:
– Number of processing
elements
– Polynomial orders of
processing elements
– Number of taps
– Delay values
MIT Lincoln Laboratory
Wideband NLEQ Processor Parameter
Optimization
Z-α
Z-β
Pass-through
FIR
X
Z-γ1
-γΝ
ZZ
-γΝ
•
Parameter selection
– 10 filters, 10 taps, 0-3 tap delay, 0-3 group delay,
3 pass through delay
HPEC 2009-11
WSS 9/23/2009
MIT Lincoln Laboratory
Parallel NLEQ Processor Architecture
Optimization
Low VT Dynamic Logic IC Layout
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Design
Reassemble
e
Distribute
Distributed Polyphase BlockFloating-Point Residue
Arithmetic Architecture
Design
Feedback
Feedback
(Performance Trades)
(Performance Trades)
Sub-processor Task Distribution & Sizing
P
P
P
P
P
P
P
P
P
P
P
P
FIR1φ1
FIR1φ2
FIR1φ3
P P P P
P P P P
P P P P
P
P
P
P
P
P
P
P
P
P
P
IC Architecture and Floor Plan
Design
P
NLP1φ1
NLP1φ2
NLP1φ3
P P P P
P P P P
P P P P
P
P
P
P
P
P
P
P
P
P
P
P
FIR2φ1
P P P P FIR2φ2
P P P P FIR2φ3
P P P P
Clocks
FIR1φ1
FIR1φN
NLP1φ1
NLP1φN
FIR1φ2
FIR2φN
NLP2φ1
NLP2φN
FIRmφN
NLPmφ1
NLPmφN
Buses
Feedback
(Routing
Efficiency)
FIRmφ1
Memory
HPEC 2009-12
WSS 9/23/2009
I/O
Control
MIT Lincoln Laboratory
Measured Results: PRN Signal
with Amplifier & ADC Distortions
Pow
wer (dBFS)
In-band
i
intermods
d
•
Harmonics
Typical
Response
Equalized
Pow
wer (dBFS)
Unequalized
Non-tonal signal experiment parameters
– Amplifier in saturation region
– Max
M 104 included
i l d d in
i testbed
t tb d system
t
– Pseudo-Random Noise (band-limited) input waveform
•
Greater than 25 dB dynamic range improvement
– In
In-band
band signal component is not distorted by the equalizer
HPEC 2009-13
WSS 9/23/2009
MIT Lincoln Laboratory
NLEQ Adaptive Equalization
Performance
IF
FDR
Improve
ement
(dB)
Spu
ur Redudu
uction
in dB
-12
Fully Adaptive
Partially Adaptive
-14
Non-Adaptive
-16
-18
-20
-22
-24
-26
•
•
Adaptive Equalization Performance
Nominal training
temperature
Minimal performance
losses uses
computationally
efficient
ffi i t adaptive
d ti
algorithm
0
10
20
30
40
50
Ambient Temperature
(oC)
Ambient Temperature
in Degrees
Celcius
Characterized Max 108 device sensitivity to changes in temperature
Applied adaptive equalizations
–
–
HPEC 2009-14
WSS 9/23/2009
Fully temperature adaptive approach achieve good performance
Partially adaptive approach can achieve similar performance with much
higher computational efficiency
MIT Lincoln Laboratory
Outline
•
•
•
Introduction
NLEQ processor architecture
VLSI NLEQ processors
– Enabling technologies
– NLEQ4000 ultra
ultra-wideband
wideband processor IC
– NLEQ500 wideband processor IC
•
•
HPEC 2009-15
WSS 9/23/2009
Performance demonstration results
Summary
MIT Lincoln Laboratory
Nonlinear Equalizer Processor IC
Development Process
Non-Linear Equalizer
Algorithm/Architecture
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Partition FIR #N
H2
+
X(n)
Y(n)
HJ
Reassemble
R
Distribution
D
Distributed Polyphase
yp
Residue Arithmetic
H1
EQ FIR
Partition FIR #1
Partition FIR #2 ×
IC Architecture
Clocks
I/O
FIR1φ1 FIR1φNNLP1φ1NLP1φN
FIR1φ2 FIR2φNNLP2φ1NLP2φN
Buses
FIRmφ1 FIRmφNNLPmφ1
NLPmφN
NLEQ Signal Processor IC
Memory
Control
● 1.5 Tearops
● 1.2 Watts
Architecture
Optimization
8
16
16
4
2
2
8
1
4
8
16
Level of Pipeline
4
2
1
Optimal
Region
Degree
of
Polyphasi
ng
Throughput
Density
Power
Efficiency
Throughput
Density
Times
Power
Efficiency
500 MH
MHz BW MAX108
Power (dB)
1
Low Vt Dynamic
Logic
Before NLEQ
After NLEQ
Frequency Bin
HPEC 2009-16
WSS 9/23/2009
MIT Lincoln Laboratory
Architectural Comparison of Pentium 4
and MIT LL Processor Dies
Pentium 4 Die
MIT LL Processor Die
Processor
Array
•
•
•
•
•
HPEC 2009-17
WSS 9/23/2009
Single processor
Multiple caches and memory bus
Only core runs at high speed
General purpose processing
Large
g design
g team (>100)
(
)
•
•
•
•
•
1000’s of parallel processors
Local memory only
Entire die runs at high speed
Signal processing functions
Small design
g team (<10)
(
)
MIT Lincoln Laboratory
Custom CMOS Circuit Design
Standard Cell Full Adder
•
•
•
HPEC 2009-18
WSS 9/23/2009
Pre-designed logic gates only
Automatic device placement and
routing
Large area and power
consumption
Full Custom Full Adder
•
•
•
Custom logic and devices sizing
Manual device placement and
interconnect
Small area and power
consumption
MIT Lincoln Laboratory
Full Custom Low Threshold Voltage (VT)
Dynamic Logic Circuits
Standard Cell Static Register
Full Custom
Dynamic Register
Low VT Devices
P = ½CV2f
Charge
Leakage
Design Techniques
●
●
●
●
●
•
•
•
HPEC 2009-19
WSS 9/23/2009
Logic based computation and
storage
Many devices
Large area and power consumption
•
•
•
Frequent refresh
Bypass capacitors
Signal isolation
Guard rings
Robust circuits
Charge based computation and
storage
Fewer devices
Small area and power consumption
MIT Lincoln Laboratory
NLEQ4000 Processor IC
Wideband NLEQ
Processor IC Layout
And BGA Package
•
•
–
–
•
•
•
HPEC 2009-20
WSS 9/23/2009
Up to 4,000MSPS
Selectable bit widths
Up to 12 bits input
Up to 16 bits output
LVDS and CMOS I/O
Programmable
g
coefficients
Block floating point residue
arithmetic
Parameter
(IBM 0.13um)
Core
Chip
Die Size
2.6 mm x
3.3 mm
6mm x
6mm
Power
@1500MSPS
266mW
453mW
Power
@4000MSPS
706mW
1219mW
MIT Lincoln Laboratory
NLEQ500 Processor
IBM 0.13µm Die
•
•
Up to 500MSPS
Selectable bit widths
–
–
•
•
•
•
BGA
Up to 18 bits input
Up to 22 bits output
Low voltage CMOS I/O
Programmable
g
configuration
g
and coefficients
Block floating point residue arithmetic
Yield 14/15 for LowVt and 14/15 for RegVt
Parameter
(IBM CMOS 0.13um)
Core
I/O
Chip
Size
0.65mm x
1.4mm
N/A
2.2mm x
2.2mm
Power @100MSPS
P
(Vdd=0.6V)
6 W
6mW
19 W*
19mW*
25 W*
25mW*
Power @500MSPS
(Vdd=1.2V)
122mW
121mW*
243mW*
*With 50 Ohm Load Termination
HPEC 2009-21
WSS 9/23/2009
MIT Lincoln Laboratory
Outline
•
•
•
•
•
HPEC 2009-22
WSS 9/23/2009
Introduction
NLEQ processor architecture
VLSI NLEQ processors
Performance demonstration results
S
Summary
MIT Lincoln Laboratory
MAX108 Demonstration Results
MAX108 ADC with NLEQ4000
Without NLEQ4000
NLEQ4000
MAX108
With NLEQ4000
Q
•
~21 dB linearity
improvement demonstrated
with NLEQ4000 IC at
1.5GSPS
HPEC 2009-23
WSS 9/23/2009
MIT Lincoln Laboratory
Measured NLEQ Performance
Improvement for Other ADCs
Interleaving Architecture
~1 GHz
Improved ~17 dB
National 81000
Flash Architecture
~1.3 GHz
Improved ~12 dB
Maxim 109
HPEC 2009-24
WSS 9/23/2009
Folding Architecture
1.5 GHz
Improved ~13 dB
Atmel AT84AS008
Entire Receiver Chain
30 MHz BW
Improved ~12 dB
LTC 2209
MIT Lincoln Laboratory
X-Band Receiver-on-Chip (RoC)
Development Based on NLEQ DSP
BPF
LO
Top View
BPF
MAX108
ADC
NLEQ
RoC
Bottom View
ADC
LNA
•
Mixer
IF Amp
Integrated RoC Die
360mW
Linear dynamic range limited by the final IF amplifier
NLEQ
– NLEQ DSP to linearize the amplifier and ADC
•
•
HPEC 2009-25
WSS 9/23/2009
High performance and low power achieved with new
analog/digital co-design paradigm
Single die receiver implementation being explored
MIT Lincoln Laboratory
Summary
•
Linearity enhancement required by DoD/commercial
sensor/receiver applications
–
–
•
MIT LL has developed high-throughput low-power nonlinear
equalization signal processor ICs
–
–
–
–
•
Phased array sensors/receivers
Frequency channelized sensors/receivers
Massively
yp
parallel systolic
y
architecture
Polyphase distributed arithmetic processing
Block floating point residue number arithmetic
Full custom low-threshold-voltage dynamic logic
Successful demonstration results
–
–
>20 dB linearity improvement
NLEQ4000
Up to 4GSPS, <1.25W
Up to 12 bit ADCs
–
NLEQ500
Up to 500MSPS, <0.25W
Up to 18bit ADCs
HPEC 2009-26
WSS 9/23/2009
MIT Lincoln Laboratory