Application Note AN6016 LCD Backlight Inverter Drive IC (FAN7311) 1. Description www.fairchildsemi.com

www.fairchildsemi.com
Application Note AN6016
tm
LCD Backlight Inverter Drive IC (FAN7311)
1. Description
(PWM) driver stage, soft start, open lamp regulation, and
Under Voltage Lockout protection (UVLO). The FAN7311
includes an internal shunt regulator that allows operation
with an input voltage from 5V to 25.5V. It supports analog
and burst dimming modes of operation. The FAN7311 provides open lamp regulation and protection. Open lamp regulation protects the transformer from over-voltage during start
up or when an open lamp occurs. The transformer voltage is
regulated by reducing duty cycle when an over-voltage is
detected. Open lamp protection can be used to shut down an
IC when an open lamp condition continues longer than a
specified time.
Design goals for a Cold Cathode Fluorescent Lamp (CCFL)
inverter for use in a notebook computer or other portable
applications include small size, high efficiency, and low cost.
The FAN7311 provides the necessary circuit blocks to
implement a highly efficient CCFL backlight power supply
in 20-SSOP and 20-SOIC packages. The FAN7311 typically
consumes less than 4mA of operating current, improving
overall system efficiency. External parts count is minimized
and system cost is reduced by the integration of features
including; feedback-controlled Pulse Width Modulation
F1
FUSE
C22
220μ
25V
CN5
1
2
3
4
5
6
7
8
9
10
IC1 FAN7311
0
12V
OLP
RT1
OLR
OUTB
R6
ENA
10k
12505WR-10
0
OUTA
0
0
S_S
VIN
DIM (0~3.3V)
R4
22k
0
R2
56k
C21
10n
1μ
GND
PGND
0
10k
SP
DP
GP
DP
0
C27
1μ
0
C7 10μ
LTM190EX
TX1
FDS8958A
1
M2
2
J1
REF
OUTC
ADIM
OUTD
0
0
R27
C5 220p
BDIM
CT
EA_IN
RT
0
10k
R527k
0
C4 4.7n
0
EA_OUT BCT
SN
DN
GN
DN
SP
DP
GP
DP
FDS8958A
C10
15p
OLR
FB
OLR
R26
1k
0
10k
R9
9.1k
OLP2
C14
10n
R13
1k
C30
10n
0
0
0
Q1
R22
10k
1 HOT
OLP2
R28
10k
C12
15p
OLP3
OLP3
BAW56
R20
10k
OLP4
R21
10k
C19
2.2n
0
C20
2.2n
D3
BAV70
R12
1k
0
0
R11
1k
0
C15
10n
0
BAV99
0
D9
R18
1k
R19
1k
BAV99
0
0
0
FB
C17
2.2n
0
C29
10n
CN4
CCFL
OLP4
D8
OLR
0
0
BAW56 C18
2.2n
HOT
2 COLD
C13
15p
BAW56
KST2222
D10
R17
1k
0
CN3
2 COLD CCFL
OLP1
D1
0
FB
1
D11
BAV99
0
TX2
0
REF
C9
1μ
D7
R16
1k
BAV99
0
R14
100k
0
CN2
CCFL
D6
D4
BAV70
R15
100k
2 COLD
C11
15p
OLP1
RT
R8
R1
330k
CN1
CCFL
COLD
1 HOT
4.7n
OLP
HOT
C8 10μ
0
C3
0
R25
DN
1μ
R70
R3
18k
DN
GN
0
C2
REF
SN
C6
0.22μ
0
0
RT
OUTA
C1
C28
10n
0
0.1μ
82k
OUTB
R24
ON/OFF
C25
1μ
M1
C26
0
Figure 1. Application Circuit
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
2. Block Diagram and Basic Operation
2.1 Block Diagram
RT
CT
max. 2V
OUTA
OSCILLATOR
Output
Driver
min. 0.5V
+
+
6μA
S_S
OUTB
Output
Control
Logic
PGND
1mA
OUTC
Output
Driver
OUTD
MRT1
RT1
Striking
Logic
OLP
S_S
1.4μA
EA_OUT
UVLO
+
ADIM
Error Amp.
Q CLR R
-
EA_IN
+
VOLP+α
Q SET S
UVLO
VOLP
2.5V 1.5V
2.5V
+
Solr
BCT
min. 0.5V
OLR
Solr
105μA
-
Sburst 85μA
Va+α
max. 2V
Voltage
Reference
&
Internal
Bias
-
2V
2.5VREF
REF
+
Sburst
BDIM
AGND
OLP
-
+
VIN
+
ENA
1.4V
VIN
UVLO
-
UVLO 5V
Figure 2. Block Diagram
2
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AN6016
APPLICATION NOTE
2.2 Under Voltage Lockout (UVLO)
The UVLO circuit guarantees stable operation of the IC’s
control circuit by stopping and starting it as a function of the
VIN value. The UVLO circuit turns on the control circuit
when VIN exceeds 5V. When VIN is lower than 5V, the IC’s
standby current is less than 200µA.
2.3 ENA
Applying voltage higher than 2V to ENA pin enables the
operation of the IC. Applying voltage lower than 0.7V to
ENA pin disables the operation of the inverter.
Voltage
Reference
&
Internal
Bias
2.5VREF
REF
+
VIN
UVLO
ENA
2.5 Oscillator
VIN
+
-
Figure 5. Soft Start During Initial Operation
1.4V
UVLO 5V
2.5.1 Main Oscillator
Figure 3. Under Voltage Lockout and ENA Circuits
4
Timing capacitor CT is charged by the reference current
source. The source is formed by the timing resistor RT whose
voltage is regulated at 1.25V. The sawtooth waveform of the
main oscillator circuit charges up to 2V, then the capacitor
begins discharging down to 0.5V. The capacitor starts charging again and a new switching cycle begins.
3 1.25
4 RT
(2.1)
I ch arg e = --- ----------
Icc (mA)
2
0
5
10
VIN (V)
15
20
The main frequency can be programmed by adjusting the
values of RT and CT. The main frequency can be calculated
as shown below.
19
f op = ---------------------32 R T C T
Figure 4. Start Voltage and Operating Current
(2.2)
2.4 Soft Start
The soft-start function is provided by the S_S pin and is connected through a capacitor to GND. A soft-start circuit
ensures a gradual increase in the input and output power. The
capacitor connected to S_S pin determines the rise rate of the
duty ratio. It is charged by a current source of 6µA.
Icharge
2V
+
S SET Q
CT
R CLR Q
20 x Icharge
0.5V
+
Figure 6a. Main Oscillator Circuit
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AN6016
APPLICATION NOTE
Figure 6b. Main Oscillator Waveform
Figure 7b. Burst Oscillator Waveform
2.5.2 Burst Dimming Oscillator
Burst dimming timing capacitor BCT is charged by the reference current source, formed by the timing resistor RT whose
voltage is regulated at 1.25V. The sawtooth waveform
charges up to 2V. Once reached, the capacitor begins discharging down to 0.5V, then starts charging again and a new
switching cycle begins.
3 1.25
I ch arg e = ------ ---------32 R T
2.6 Analog Dimming
For analog dimming, the lamp intensity is controlled with
the ADIM signal. A 2.5V on ADIM brings full brightness.
Analog dimming waveforms are shown in Figures 8 and 9.
(2.3)
The burst dimming frequency can be programmed by adjusting the values of RT and BCT. The burst dimming frequency
can be calculated as below.
3.75
f burst = -------------------------96 R T BC T
(2.4)
The burst dimming frequency should be greater than 120Hz
to avoid visible flicker. To compare the input of BDIM pin
with the 0.5~2V triangular wave of burst oscillator makes
the PWM pulse for burst dimming. The PWM pulse controls
EA_OUT voltage by summing 85µA into the EA_IN pin.
Figure 7 shows burst dimming oscillator circuit and waveform.
Icharge
2V
Figure 8. Analog Dimming at Maximum
+
S SET Q
CT
R CLR Q
20 x Icharge
0.5V
+
Figure 7a. Burst Oscillator Circuit
4
Figure 9. Analog Dimming at Minimum
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AN6016
APPLICATION NOTE
2.6.1 Setting Lamp Current Sensing Resistors
The data to input
The calculated data
1) Positive Polarity Analog Dimming
CFB
VCS
RFB
CCFL
CCFL
RCS1 Vsense
–
VREF
+
Error
Amp.
RCS2
Rsense
Rsense
Figure 10. Calculating Value of the
Analog Dimming Circuit Parameter
VREF
2.5
Ilamp
6.5
Rsense
1
kΩ
Rsense_eff
0.95
kΩ
Diode drop voltage
0.3
V
Vsense
5.259453252
V
RCS1/RCS2
1.103781301
RCS1
10
kΩ
RCS2
9.059765727
kΩ
Rsense_effective 0.950148969kΩ = Rsense/(RCS1+RCS2)
Lamp current is sensed at Rsense and the sensed voltage is
divided by RCS1 and RCS2 and is averaged at Error Amp. by
RFB and CFB.
2) Negative Polarity Analog Dimming
CFB
R sense_eq
V DF
1 + ------------------------------------------------I lamp ⋅ ( R cs1 + R cs2 )
= ----------------------------------------------------------- ≈ R sense || ( R cs1 + R cs2 ),
R
RFB
+
⎛1
V sense = ⎜ --⎝π
π
∫0
⎞
2 ⋅ I Lamp ⋅ R sense_eq ⋅ sin θ ⋅ dθ⎟ – V DF
⎠
R cs2
2
V CS = V sense ⋅ ---------------------------- = ⎛ --- ⋅ 2 ⋅ I Lamp ⋅ R sense – V DF⎞
⎝π
⎠
R cs1 + R cs2
R sense_eq
R cs2
V ref = V CS = V sense ⋅ ---------------------------R cs1 + R cs2
R cs1
V sense
---------- = --------------- – 1
R cs2
V ref
VREF
RCS2
Rsense
Rsense
Lamp current is sensed at Rsense and the sensed voltage is
divided by Rcs1 and Rcs2 and is averaged at Error Amp. by
RFB and CFB.
(2.5)
Equation (2.5) assumes that the error amplifier loop is
closed. The relationship between VCS and Vref is given in
equation (2.6).
R cs2
2
= ⎛ --- ⋅ 2 ⋅ I Lamp ⋅ R sense – V DF⎞ ⋅ ---------------------------⎝π
⎠ R cs1 + R cs2
CCFL
Figure 11. Calculating Value of the Analog Dimming
Inverting Circuit Parameter
2
= --- ⋅ 2 ⋅ I Lamp ⋅ R sense_eq – V DF ( 1 )
π
R cs2
⋅ ---------------------------R cs1 + R cs2
CCFL
–
Error
Amp.
V DF is diode forward voltage
VA
Vsense
VCS R
CS1
V DF
1 + ------------------------------------------------I lamp ⋅ ( R cs1 + R cs2 )
= ----------------------------------------------------------- ≈ R sense || ( R cs1 + R cs2 ),
R
V DF is diode forward voltage
⎛1
V sense = ⎜ --⎝π
π
∫0
⎞
2 ⋅ I Lamp ⋅ R sense_eq ⋅ sin θ ⋅ dθ⎟ – V DF
⎠
2
= --- ⋅ 2 ⋅ I Lamp ⋅ R sense_eq – V DF ( 1 )
π
(2.6)
(2.7)
R cs2
2
V CS = V sense ⋅ ---------------------------- = ⎛ --- ⋅ 2 ⋅ I Lamp ⋅ R sense – V DF⎞
⎝π
⎠
R cs1 + R cs2
R cs2
⋅ ---------------------------R cs1 + R cs2
(2.8)
For example, suppose:
V ref = 2.5V, I Lamp = 6.5mA, R sense = 1kΩ, R cs1 = 10kΩ
From these values, an approximate value of Rcs2 can be
derived. To get a more precise value for RCS2, use an iterative calculation. Use Rsense to calculate RCS2, because the
Rsense_eq value is unknown. After finding the value of
Rsense_eq, use Rsense_eq to calculate RCS2. Calculate iteratively until the previous Rsense_eq value is almost equal to the
current Rsense_eq value.
REV. 1.0.1 4/20/06
Equation (2.8) assumes the error amplifier loop is closed.
The relationship between VCS and VA (dimming control
voltage) is given in equation (2.9).
V A ⋅ R FB + V CS ⋅ R A
V ref = --------------------------------------------------R FB + R A
(2.9)
5
AN6016
APPLICATION NOTE
The relationship between dimming control voltage and lamp
current can be programmed for the application. For example,
suppose:
V Amin. = 0, I Lamp.max = 7mA
(2.10)
V Amax. = 3.3, I Lamp.min = 3mA
(2.11)
I Lamp.min = α ⋅ I Lamp.max
(2.12)
Substituting for VA and VCS in equation (2.9) from equation
(2.10) results in:
V CSmax ⋅ R A
V REF = ------------------------------R FB + R A
V ref ⋅ ( R FB + R A )
V ref ⋅ ( 1 + β ) ⋅ R FB
V CSmax = ------------------------------------------- = ---------------------------------------------RA
β ⋅ R FB
V ref ⋅ ( 1 + β )
1
= -------------------------------- = V ref ⋅ ⎛ 1 + ---⎞
⎝
β
β⎠
R cs2
= V sense ⋅ ---------------------------R cs1 + R cs2
R cs2
2
= ⎛ --- ⋅ 2 ⋅ I Lamp ⋅ R sense – V DF⎞ ⋅ ---------------------------⎝π
⎠ R cs1 + R cs2
(2.22)
R cs1
V sense
---------- = ----------------------------- – 1
R cs2
1
V ref ⎛ 1 + ---⎞
⎝
β⎠
(2.13)
(2.23)
For example:
Substituting for VA and VCS in equation (2.9) from equation
(2.11) results in:
V ref = 2.5V, I lampmax = 6.7mA, I lampmin = 4mA,
V Amax ⋅ R FB + V CSmin ⋅ R A
V ref = -------------------------------------------------------------------R FB + R A
R FB = 100kΩ, R sense = 1.5kΩ , R CSI = 10kΩ
V Amax ⋅ R FB + α ⋅ V CSmax ⋅ R A
= ----------------------------------------------------------------------------R FB + R A
(2.14)
Multiplying equation (2.13) by RFB + RA gives:
V ref ⋅ R FB + V ref ⋅ R A = V CSmax ⋅ R A
(2.15)
From these values, it is possible to obtain the value of RCS2.
To get more precise value of RCS2, use an iterative calculation. Use Rsense to calculate RCS2, because Rsense_eq is
unknown. After the first calculation, Rsense_eq can be
resolved. Calculate the RCS2 value using Rsense_eq. Calculate
iteratively until the previous Rsense_eq value becomes almost
equal to the current Rsense_eq value.
The data to input
Multiplying equation (2.14) by RFB + RA gives:
The calculated data
Vref ⋅ R FB + Vref ⋅ R A = VAmax ⋅ R FB + α ⋅ VCSmax ⋅ R A
(2.16)
( V ref – V Amax ) ⋅ R FB + V ref ⋅ R A = α ⋅ V CSmax ⋅ R A
(2.17)
Multiplying equation (2.15) by α gives:
α ⋅ V ref ⋅ R FB + α ⋅ V ref ⋅ R A = α ⋅ V CSmax ⋅ R A
( α – 1)
( V Amax + V ref
) ⋅ R FB + V ref
( α – 1)
( α – 1)
) ⋅ R FB = V ref
⋅ RA = 0
(2.19)
( α – 1)
(2.20)
⋅ RA
Equation (2.20) can be rewritten as:
( α – 1)
( V Amax + V ref
) ⋅ R FB
R A = ----------------------------------------------------------------- = β ⋅ R FB
( α – 1)
V ref
(2.21)
RA is calculated by selecting RFB and solving equation
(2.21). Substituting for RA in equation (2.13) from equation
(2.21) and rewriting gives:
6
VA
Ilamp
Min.
–
0
4
Typ.
2.5
-
–
Max.
–
3.2
6.7
α 0.597014925 6.7
(2.18)
Subtracting equation (2.17) from equation (2.18) gives:
( V Amax + V ref
VREF
Ilamp_max/Ilamp_min
RFB
100
kΩ
RA
217.6296296
kΩ
b
2.176296296
VCSmax
3.64874064
Rsense
1.5
Rsense_eff
1.3861
kΩ
Diode drop voltage
0.3
V
Avg_maxVsense
8.061120587
V
RCS1/RCS2
1.209288459
RCS1
10
kΩ
RCS2
8.269325588
kΩ
Rsense_effective 1.386187316kΩ =Rsense//(RCS1+RCS2)
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
2.7 Burst Dimming
Lamp intensity is controlled with the BDIM signal. 0V on
BDIM commands full brightness. The duty cycle of the burst
dimming comparator determines the lamp brightness as a
percent of the rated lamp current. Burst dimming is implemented by summing 85µA into the feedback node to turn
down the lamp. If there is sufficient voltage for the lamp to
strike, the feedback loop controls the lamp at the rated current using a fixed current-sense resistor. When the voltage of
EA_IN is brought higher than Vref, EA_OUT becomes low
and the MOSFET stops switching. At this time, the resonant
tank voltage decays until the lamp extinguishes. CFB is
reduced, if possible, to speed up the lamp re-strike. Burst
dimming waveforms are shown in Figures 12, 13, and 14.
Figure 14. Burst Dimming at 25%
2.8 Open Lamp Regulation and Open Lamp
Protection
Power stage operation must be suspended if an open lamp
occurs, because the power stage is at high gain. When a voltage higher than 2V is applied to the OLR (Open Lamp Regulation) pin, the part enters the regulation mode and controls
EA_OUT voltage to limit the lamp voltage by adding 105µA
into the feedback node. The OLP (Open Lamp Protection)
capacitor, which is connected to the OLP pin, is charged by
the 1.4µA internal current source.
Figure 12. Burst Dimming at 75%
2.8.1 Open Lamp at Initial Operation
OLP voltage starts from 1V. After reaching 2.5V, the IC
shuts down when all the output are high.
The relationship between the OLP capacitor and the time ΔT
before the IC shuts down is calculated using the approximation I = CΔV/ΔT, where I = 1.4μA, ΔV = 1.5V, resulting in
ΔT(s) = 1.1C(μF).
2.8.2 Normal Operation and Open Lamp
OLP voltage starts at 0V. After reaching 1.5V, the IC shuts
down when all the outputs are high.
The relationship between the OLP capacitor and the time ΔT
before the IC shuts down is calculated using the approximation I = CΔV/ΔT, where I = 1.4μA, ΔV = 1.5V, resulting in
ΔT(s) = 1.1C(μF).
Figure 13. Burst Dimming at 50%
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AN6016
APPLICATION NOTE
2.8.3 OLP Operation
CCFL1
CCFL2
Lamp current 1
Lamp current 2
R1
R3
FB
D1
R4
R2
D2
R5
OLP
VREF
R7
R8
C1
C2
D3
1V
0
1V
0
R6
Q1
C3
1V
0
1V
0
D4
Normal operation
Open lamp
Figure 15. Operating OLP
In normal operation, the voltage of D3’s cathode is over 1V
and D3 is turned off; Q1 is on; and OLP remains low. When
open lamp occurs, the voltage of D3’s cathode is under 1V
and either D3 is turned on. Then Q1 is turned off and OLP
start charging by an internal current source of 1.4µA. If OLP
reaches 2V, the IC is shut down. The base current of Q1
should be more than 1.4µA/hfe. R6 is determined by this
condition. R4, R5, R7, and R8 are determined so that Q1 and
D4 are turned off in the open lamp condition. C1 and C2 are
determined so that the voltage of D3’s cathode is over 1V in
normal operation.
8
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
2.8.4 OLR Operation
D3
D4
OLR>2V
105μA
Solr
-
CCFL2
CCFL1
OLR
+
2V
Lamp current 2
Lamp current 1
R3
R1
D1
+
Error Amp.
R2
VREF
R4
D2
R5
OLR > 2V ↑ → Solr on duty ↑ → EA_IN ↑ → EA_OUT ↑ → Switching duty ↑ → Lamp voltage ↓
→ OLR > 2V ↓ → Solr on duty ↓ → EA_IN → EA_OUT ↓ → Switching duty ↑ → Lamp voltage ↑
Figure 16. Operating OLR
105µA
+
Solr
-
OLR
2V
To EA_IN
Figure 17. Open Lamp Regulation Circuit
To Cont rol Logic
Figure 19. OLR Voltage During Striking Mode
1.4µA
UVLO
OLP
+
Q
Q
SET
CLR
S
R
-
VOLP 2.5V
1.5V
UVLO
Figure 18. Open Lamp Protection Circuit
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AN6016
APPLICATION NOTE
2.9 Output Driver
The four output drives are designed so that the two pairs of
switches, pair A and B and pair C and D, never turn on
simultaneously. The OUTA-OUTB pair is intended to drive
Dead
Time
Dead
Time
Dead
Time
Dead
Time
one half-bridge in the external power stage. The OUTCOUTD pair drives the other half-bridge. The detailed timing
relationship is shown below.
Dead
Time
Dead
Time
Dead
Time
Dead
Time
Dead
Time
EA_OUT
CT
SYNC
T
T1
POUT A
NOUT B
POUT C
NOUT D
A&D
B&C
Figure 20. New Phase Shift Control Waveforms
10
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
2.10 CCFL Striking Sequence
ENA
ENA
4V
S_S
S_S
0.5V
1.5V
OLP
OLP
1V
0.6V
RT1
Normal
RT1
Fnor
Striking frequency
F st =
Open lamp
19 .
1
64 (RT // RT1 ) . C T
shutdown
19
1
= .
64 (RT // RT1) .CT
Normal operation frequency
Fnor =
19 .
1
64 (RT // RT1 ) . CT
Figure 23. Open Lamp
Figure 21. CCFL Ignites
ENA
S_S
0.5V
2.5V
1V
OLP
RT1
Striking frequency
shutdown
19
1
Fst =
64 (RT // RT1 ) .CT
Figure 22. CCFL Does Not Ignite
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AN6016
APPLICATION NOTE
2.11 PCB Layout Guideline
1.
Separating ground for analog and power portions of circuitry is one of the simplest and most effective methods
of noise suppression. This is shown in Figure 24.
2.
The traces between drive output and the MOSFET gates
should be as short as possible and as wide as possible.
3.
The traces of RT, CT, and BCT should be kept away from
high-current components and traces.
FAN7311
OLP
RT1
OLR
OUTB
ENA
OUTA
S_S
VIN
GND
PGND
REF
OUTC
ADIM
OUTD
BDIM
CT
EA_IN
RT
EA_OUT BCT
PGND
AGND
Figure 24. PCB Layout
12
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
3. Power Stage Design
3.1 Resonant Circuit
Cc
L l1
N p:Ns
LM
V
Cp
CCFL A circuit of LCD backlight inverter
Cp
CCFL A circuit of LCD backlight inverter
Ideal
VIN
0
(a)
-VIN
Cc
L l1
N p:Ns
L l2
LM
Vrms
Vrms =
L l2
2 2
V
π IN
Ideal
(b)
Cc /n2
n 2*L l1 Ns /Np =n
L l2
n 2*LM
nVrms
Cp
R lamp Ideal transformer is neglected.
Cp
R lamp Assuming LM is infinite, IM is near zero.
LM is neglected.
Cp
R lamp Primary and secondary side leakage
inductances are combined.
Cp
R lamp DC blocking capacitor is neglected.
(c)
Cc /n2
n 2*L l1
L l2
nVrms
(d)
Cc /n2
Ll
nVrms
(e)
Ll
nVrms
(f)
Z
Ll
Cs
Rs
nVrms
(g)
Transform the parallel resonant circuit
into the series resonant circuit.
Z
Figure 25. Resonant Circuit
REV. 1.0.1 4/20/06
13
AN6016
APPLICATION NOTE
The resonant circuit (f) in Fig. 25 is a second-order low-pass
filter and can be described by the following normalized
parameters:
The loaded quality factors QL and Qr are related by:
ωr L
1
Q r = --------- = ------------------ = ω r C p R lamp
Rs
ωr Cs Rs
• The corner frequency:
1
ω 0 = ---------------LI Cp
ωρ
= Q r ⎛ −−− ⎞ =
⎝ ω 0⎠
(3.1)
2
Q L – 1 , for Q L ≥ 1
(3.12)
3.2 Voltage Transfer Function
• The characteristic impedance:
v(t)
1
Z 0 = ω 0 L I = ------------- =
ω0 Cp
LI
-----Cp
(3.2)
VIN
2Dπ
3
π
2
• The loaded quality factor at the corner frequency fo:
R lamp
R lamp
Q L = ω 0 C p R lamp = -------------- = -------------ω0 LI
Z0
• The resonant frequency that forms the boundary between
capacitive and inductive loads:
ωr LI
1
Q r = ----------- = -----------------Rs
ωr Cs Rs
(3.5)
• The input impedance of the resonant circuit (f) in Fig. 25
is:
ω
1 ω
1
R lamp 1 – ⎛ ------⎞ + j ------- ⎛ ------⎞
R lamp ⋅ ------------⎝ ω 0⎠
Q L ⎝ ω 0⎠
jωC p
Z = jωL + ---------------------------------- = -----------------------------------------------------------------------1
ω
R lamp + ------------1 + jQ L ⎛ ------⎞
⎝ ω 0⎠
jωC p
2
(3.6)
= R S + jX s
ω 2 2 ⎛ ω ⎞2
1 – ⎛ ------⎞
+ -----⎝ ω 0⎠
⎝ ω 0⎠
------------------------------------------------------------2
ω
1 + ⎛ Q L ------⎞
⎝ ω 0⎠
⎧
⎫
ω
1
ω
ϕ = arc tan ⎨ Q L ⎛ ------⎞ ⎛ ------⎞ + --------2- – 1 ⎬
⎝ ω 0⎠ ⎝ ω 0⎠
QL
⎩
⎭
(3.7)
As shown in Fig. 26, the input voltage of the resonant circuit
v is a square wave of magnitude VIN, given by:
1
v = 0, for 0 < ωt ≤ ⎛ --- – D⎞ π
⎝2
⎠
1
1
v = V IN , for ⎛ --- – D⎞ π < ωt ≤ ⎛ --- – D⎞ π
⎝2
⎠
⎝2
⎠
1
3
v = 0, for ⎛ --- + D⎞ π < ωt ≤ ⎛ --- – D⎞ π
⎝2
⎠
⎝2
⎠
3
v = 0, for ⎛ --- – D⎞ π < ωt ≤ 2π
⎝2
⎠
v i1 = V m sin ( ωt ),
(3.14)
(3.8)
(3.9)
X S = Z sin ϕ
(3.10)
• The resonant frequency, fr, is defined as a frequency at
which the phase shift is zero. The ratio of fr to the corner
frequency, fo, is:
(3.11)
4
V m = --- V IN sin Dπ
π
(3.15)
You can obtain the rms value of vi1:
Vm
2 2
V rms = -------- = ---------- V IN sin Dπ
π
2
(3.16)
Which leads to the voltage transfer function from VIN to the
fundamental component at the input of the resonant circuit:
V rms
2 2
M Vs = ------------ = ---------- sin Dπ
V IN
π
14
(3.13)
in which the amplitude of vi1 can be found from Fourier
analysis as:
R S = Z cos ϕ
1
1 – --------2- , for Q L ≥ 1
QL
-VIN
The fundamental component of this voltage is:
2
QL
2
fr
---- =
f0
ωt
2π
3
3
v = – V IN , for ⎛ --- – D⎞ π < ωt ≤ ⎛ --- – D⎞ π
⎝2
⎠
⎝2
⎠
where,
Z
------ =
Z0
2D π
(3.4)
• The loaded quality factor at the resonant frequency fr:
jϕ
π
Figure 26. Input Voltage of the Resonant Circuit
1
ω r = ---------------LI Cs
= Ze
π
2
(3.3)
(3.17)
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
According to Fig. 25(f), the voltage transfer function of the
resonant circuit is:
M Vr
2 2⋅n
1
M Vl ( max ) = ------------------- , for 0 ≤ Q L ≤ ------π
2
R lamp
-------------jωC p
---------------------------------1
R lamp + ------------V Ri
jωC p
= --------------------------- = --------------------------------------------------R lamp
2 ⋅ nV rms
-------------jωC p
jωL + ---------------------------------1
R lamp + ------------jωC p
1
ejϕ
= --------------------------------------------------- = M Vr
ω 2
1 ω
1 – ⎛ ------⎞ + j ------- ⎛ ------⎞
⎝ ω 0⎠
Q L ⎝ ω 0⎠
The maximum magnitude of the DC-to-AC voltage transfer
function of the LCD backlight inverter without losses is:
2 2 ⋅ nQ L
1
M Vl ( max ) = ----------------------------- , for Q L ≥ ------1
2
π 1 – -----------24Q L
3.2 Design Procedure
(3.18)
A LCD monitor backlight circuit illustrates a design based
on the FAN7311. The inverter is designed to drive two
CCFLs with the following specifications.
Panel Model
where,
V Ri
1
M Vr = --------------- = -----------------------------------------------------------------nV rms
1 ω 2
ω ⎞2 2
⎛
+ --------2- ⎛ ------⎞
1 – -----⎝ ω 0⎠
⎝ ⎠
QL ω0
1 ω
------- ⎛ ------⎞
Q L ⎝ ω 0⎠
ϕ = -arctan ----------------------2ω
1 – ⎛ ------⎞
⎝ ω 0⎠
(3.24)
(3.19)
(3.20)
LM151X2(LG.PHILIPS LCD)
Input Voltage
9 ~ 15V
Striking Voltage
880Vrms
Operating Voltage
585Vrms (Typ.)
Operating Current
8mArms (Typ.)
Operating Frequency
50kHz (Typ.)
Rated Power
4.68W/CCFL
Efficiency
85% (Typ.)
1) Select Transformer’s Primary Turns
The maximum value of MVr is obtained by differentiating
the quantity under the square-root sign with respect to f/fo
and setting the result equal to zero. Hence, the normalized
peak frequency is:
f pk
1
------- = 0, for 0 ≤ Q L ≤ ------f0
2
f pk
------- =
f0
(3.21)
VIN,min = Minimum input voltage (Volts)
ΔB = Core magnetic flux density change (Tesla)
resulting in the maximum magnitude of the voltage transfer
function of the resonant circuit:
1
M Vr ( max ) = 1, for 0 ≤ Q L ≤ ------2
(3.22)
The magnitude of the DC-to-AC voltage transfer function of
the LCD backlight inverter without losses is obtained from
(3.17) and (3.22):
V lamp
M VI = -------------- = M Vs ⋅ ( nM Vr )
V IN
2 2 ⋅ n sinDπ
= -------------------------------------------------------------------ω 2
1 ω 2
π 1 – ⎛ ------⎞ + --------2- ⎛ ------⎞
⎝ ω 0⎠
⎝ ⎠
QL ω0
REV. 1.0.1 4/20/06
V IN, min ⋅ Δt max
N p, min = -------------------------------------ΔB ⋅ A e
where Np,min = Minimum number of primary turns
1
1
1 – -----------2-, for Q L ≤ ------2
4Q L
QL
1
M Vr ( max ) = ------------------------- , for Q L ≤ ------2
1
1 – -----------24Q L
The number of primary turns is determined by Faraday’s
law. Np,min is fixed by the minimum voltage across the primary and the maximum on time.
(3.23)
Δtmax = Maximum overlap on-time of diagonal
MOSFET switches (us)
Ae = Core cross-sectional area (mm2)
A transformer used in a full-bridge topology operates in two
quadrants of the B-H curve such that the maximum magnetic
flux density is Bmax = 0.5ΔB. For most cores, saturation
magnetic flux density is about 400mT. Margin considered,
determine that the maximum magnetic flux density Bmax =
0.5 Bsat, so the maximum magnetic flux density is Bmax =
200mT. In an example with a minimum voltage of 9V, operating frequency 50KHz, maximum on time of diagonal
MOSFET switches of 10µs and a core cross-sectional area
(EPC17, EPC19, EFD1820) of 22mm2, the minimum number of primary turns required is:
V IN, min ⋅ Δt max
9 ⋅ 10
N p, min = -------------------------------------- = ------------------- ≈ 10T s
ΔB ⋅ A e
400 ⋅ 22
15
AN6016
APPLICATION NOTE
2) Select QL and Operation Frequency to Determine the
Turns Ratio
Select a value of 1 for QL. Assume that fop = fpk = 50kHz
based on the LCD panel specification. From (3.21), the corner frequency is:
f pk
50
f o = ------------------------- = ------------------------------ = 70.7 ( kHz )
1
1
1 – -----------21 – ----------------22Q L
2 ⋅ 1.1
From (3.11), the resonant frequency that forms the boundary
between capacitive and inductive loads is:
1
1 – --------2QL
1
f r = f o ⋅ 1 – --------2- = f pk ⋅ ------------------------- = 0 ( kHz )
1
QL
1 – -----------22Q L
Therefore, zero-voltage switching (ZVS) can be achieved at
any operating frequency. For the reference design, the
required secondary lamp voltage is 585V and the minimum
voltage is 9V. Therefore, from (3.23), the minimum number
of the turns ratio is:
ω op 2 2
1 ω op 2
+ --------2- ⎛ ---------⎞
1 – ⎛ ---------⎞
⎝ ω0 ⎠
⎝
⎠
QL ω0
585
n ≥ --------- ⋅ --------------------------------------------------------------------------- ≈ 62.5T s ,
9
2 2 sin Dπ
π
2 2 ⋅ n sin Dπ
585
∴M VI = ---------------------------------------------------------------------- ≥ --------9
1 ⎛ ω ⎞2
ω ⎞2 2
⎛
+ --------2- -----π 1 – -----⎝ ω 0⎠
⎝ ω 0⎠
QL
3) Determine the Required Output Capacitance
Using the above specifications, the equivalent resistance of a
CCFL is:
The corner frequency is 70.7kHz. Assume a parasitic capacitance per lamp of 10pF. Each parasitic capacitance is effectively in parallel with each of the output capacitors.
The output capacitor is:
QL
C out = C p – C para = --------------------- – 10pF ≈ 21pF,
ω o R lamp
∴Q L = ω o R lamp C p
Using (3.3), the value of the leakage inductance is:
1
≈ 164.6 ( mH )
L I = --------------2
ωo Cp
Note: Considering minimum primary turns, minimum turns
ratio, and leakage inductance, determine primary turns, turns
ratio, and the gap of core to get the required leakage inductance. For the sample design, the number of primary turns is
30Ts and that of the secondary turns is 2200Ts. Turns ratio is
66.7.
4) Select the Proper Wire Gauges for the Primary and
Secondary Transformer Windings
The approximate primary winding rms current Ip and
approximate secondary winding rms current Is are determined by the following equations.
π P lamp
I p = ---------- ⋅ -------------,
2 2 ηV IN
2 2
∴P lamp = ηV IN I IN , I IN = ----------I p
π
Is =
2
I lamp + [ 2πf op C out V lamp ]
2
V lamp
585
R lamp = -------------- = ------------- ≈ 75 ( kΩ )
I lamp
0.008
16
REV. 1.0.1 4/20/06
AN6016
APPLICATION NOTE
Values that must be known or selected initially:
Parameter
Description
Typical Value
Units
Vlamp
Nominal lamp operating voltage
585
V
Ilamp
Nominal lamp operating current
8
mA
fop
Operating frequency
50
kHz
fpk
Peak frequency
50
kHz
Vin
Input voltage
9
V
D
Duty ratio at input voltage
50
%
QL
Loaded factor at the corner frequency
1
Cpara
Parasitic capacitance
10
pF
Ae
Core cross-sectional area
22
mm2
Bsat
Saturation magnetic flux density
0.4
T
ALleakage
AL value of leakage inductance
22
nH/N2
Values that are calculated:
Bmax
Maximum magnetic flux density
0.2
T
ΔB
Core magnetic flux density change
0.4
T
Δtmax
Maximum overlap on-time of diagonal switches
10
µs
fo
Corner frequency
70.71067812
kHz
fr
Resonant frequency
Rlamp
Equivalent resistance of a CCFL
Np,min
The minimum number of transformer’s primary turns
nmin
The minimum number of the turns ratio
Cout
The output capacitor
20.78
pF
Ll
The leakage inductance of the transformer
164.59
mH
Np
The number of transformer’s primary turns
31
Turns
0
kHz
73.125
k¾
10
Turns
62.5
Values that must be selected with more than minimum turn ratio.
n
The number of the turns ratio
62.5
The values that are calculated:
Ns
The number of transformer’s secondary turns
REV. 1.0.1 4/20/06
1934.1
Turns
17
AN6016
APPLICATION NOTE
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
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THESE
SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS,
SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR
USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN
APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
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