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FDMA6023PZT Dual P-Channel PowerTrench MOSFET
FDMA6023PZT Dual P-Channel PowerTrench® MOSFET -20 V, -3.6 A, 60 mΩ Features General Description Max rDS(on) = 60 mΩ at VGS = -4.5 V, ID = -3.6 A This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultraportable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. When connected in the typical common source configuration, bi-directional current flow is possible. Max rDS(on) = 80 mΩ at VGS = -2.5 V, ID = -3.0 A Max rDS(on) = 110 mΩ at VGS = -1.8 V, ID = -2.0 A Max rDS(on) = 170 mΩ at VGS = -1.5 V, ID = -1.0 A Low Profile-0.55 mm maximum - in the new package MicroFET 2x2 mm Thin HBM ESD protection level > 2.4 kV typical (Note 3) The MicroFET 2X2 Thin package offers exceptional thermal performance for it’s physical size and is well suited to linear mode applications. RoHS Compliant Applications Free from halogenated compounds and antimony oxides Battery protection Battery management Load switch Pin 1 S1 G1 D1 D1 D2 Q1 D2 S1 1 6 D1 G1 2 5 G2 D2 3 4 S2 G2 S2 Q2 MicroFET 2x2 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage -Continuous ID TA = 25 °C (Note 1a) -Pulsed PD TJ, TSTG Ratings -20 Units V ±8 V -3.6 -15 Power Dissipation TA = 25 °C (Note 1a) 1.4 Power Dissipation TA = 25 °C (Note 1b) 0.7 Operating and Storage Junction Temperature Range -55 to +150 A W °C Thermal Characteristics RθJA Thermal Resistance for Single Operation, Junction to Ambient (Note 1a) 86 RθJA Thermal Resistance for Single Operation, Junction to Ambient (Note 1b) 173 RθJA Thermal Resistance for Dual Operation, Junction to Ambient (Note 1c) 69 RθJA Thermal Resistance for Dual Operation, Junction to Ambient (Note 1d) 151 °C/W Package Marking and Ordering Information Device Marking 623 Device FDMA6023PZT ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 Package MicroFET 2X2 Thin 1 Reel Size 7 ’’ Tape Width 8mm Quantity 3000 units www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET June 2009 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 µA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = -250 µA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 µA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 µA -1.5 V -20 V -12 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = -250 µA ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient ID = -250 µA, referenced to 25 °C rDS(on) gFS Drain to Source On Resistance Forward Transconductance -0.4 -0.5 -2.7 mV/°C VGS = -4.5 V, ID = -3.6 A 40 VGS = -2.5 V, ID = -3.0 A 49 60 80 VGS = -1.8 V, ID = -2.0 A 60 110 VGS = -1.5 V, ID = -1.0 A 70 170 VGS = -4.5 V, ID = -3.6 A, TJ = 125 °C 58 72 VDD = -5 V, ID = -3.6 A 15 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = -10 V, VGS = 0 V, f = 1 MHz 665 885 pF 115 155 pF 100 150 pF 13 23 ns 11 20 ns 75 120 ns 47 75 ns 12 17 nC Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = -10 V, ID = -3.6 A, VGS = -4.5 V, RGEN = 6 Ω VGS = 0 V to -4.5 V VDD = -10 V, ID = -3.6 A 1.4 nC 5.2 nC Drain-Source Diode Characteristics IS Maximum Continuous Drain-Source Diode Forward Current VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 VGS = 0 V, IS = -1.1 A -1.1 (Note 2) IF = -3.6 A, di/dt = 100 A/µs 2 A -0.7 -1.2 V 33 53 ns 15 27 nC www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted Notes: 1. RθJA is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user's board design. (a) RθJA= 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. (b) RθJA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) RθJA = 69 °C/Wwhen mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For dual operation. (d) RθJA = 151 °C/W when mounted on a minimum pad of 2 oz copper. For dual operation. a) 86oC/W when mounted on a 1in2 pad of 2 oz copper. b)173oC/W when mounted on a minimum pad of 2 oz copper. c) 69oC/W when mounted on a 1in2 pad of 2 oz copper. d)151oC/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 3 www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 15 3.0 VGS = -2.0V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) VGS = -4.5V VGS = -3.0V 12 VGS = -2.5V VGS = -1.8V 9 VGS = -1.5V 6 3 PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX 0 0.0 0.5 1.0 1.5 PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX 2.5 VGS = -1.5V 2.0 VGS = -2.0V VGS = -1.8V 1.5 1.0 2.0 0 3 6 -VDS, DRAIN TO SOURCE VOLTAGE (V) 12 15 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 200 ID = -3.6A VGS = -4.5V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) 1.6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 9 -ID, DRAIN CURRENT(A) Figure 1. On-Region Characteristics PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX ID = -3.6A 160 120 TJ = 125oC 80 40 TJ = 25oC 0 1.0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 4. On-Resistance vs Gate to Source Voltage Figure 3. Normalized On- Resistance vs Junction Temperature 10 -IS, REVERSE DRAIN CURRENT (A) 15 PULSE DURATION = 300 µs DUTY CYCLE = 2.0% MAX -ID, DRAIN CURRENT (A) VGS = -4.5V VGS = -3.0V VGS = -2.5V 0.5 12 VDS = -5V 9 6 TJ = 125oC 3 TJ = 25oC 0 0.0 0.5 TJ = -55oC 1.0 1.5 2.0 1 TJ = 125oC 0.1 TJ = 25oC 0.01 0.001 0.0 2.5 TJ = -55oC 0.2 0.4 0.6 0.8 1.0 1.2 -VSD, BODY DIODE FORWARD VOLTAGE (V) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 VGS = 0V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2000 ID = -3.6A 1000 VDD = -5V 3.0 VDD = -10V VDD = -15V 1.5 Coss 100 4 8 12 16 1 10 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 1 P(PK), PEAK TRANSIENT POWER (W) 10 -ID, DRAIN CURRENT (A) Crss f = 1MHz VGS = 0V 50 0.1 0.0 0 Ciss CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE(V) 4.5 1 ms THIS AREA IS LIMITED BY rDS(on) 10 ms SINGLE PULSE TJ = MAX RATED 1s 10 s 0.1 100 ms o RθJA = 173 C/W DC TA = 25 oC 0.01 0.1 1 10 50 VGS = -4.5 V SINGLE PULSE RθJA = 173 oC/W TA = 25 oC 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (s) -VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Forward Bias Safe Operation Area Figure 10. Single Pulse Maximum Power Dissipation 2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE RθJA = 173 C/W 0.01 0.005 -4 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (s) Figure 11. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 5 www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMA6023PZT Dual P-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I40 ©2009 Fairchild Semiconductor Corporation FDMA6023PZT Rev.B1 www.fairchildsemi.com FDMA6023PZT Dual P-Channel PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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