AD8250 i Programmable Gain Instrumentation Amplifier

10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS
Programmable Gain Instrumentation Amplifier
AD8250
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Small package: 10-lead MSOP
Programmable gains: 1, 2, 5, 10
Digital or pin-programmable gain setting
Wide supply: ±5 V to ±15 V
Excellent dc performance
High CMRR 98 dB (minimum), G = 10
Low gain drift: 10 ppm/°C (maximum)
Low offset drift: 1.7 μV/°C (maximum), G = 10
Excellent ac performance
Fast settling time: 615 ns to 0.001% (maximum)
High slew rate: 20 V/μs (minimum)
Low distortion: −110 dB THD at 1 kHz
High CMRR over frequency: 80 dB to 50 kHz (minimum)
Low noise: 18 nV/√Hz, G = 10 (maximum)
Low power: 4.1 mA
DGND WR
2
A1
A0
5
4
6
LOGIC
–IN 1
OUT
7
+IN 10
8
3
9
+VS
–VS
REF
06288-001
AD8250
Figure 1.
25
G = 10
20
APPLICATIONS
Data acquisition
Biomedical analysis
Test and measurement
G=5
15
GAIN (dB)
www.BDTIC.com/ADI
10
G=2
5
GENERAL DESCRIPTION
G=1
0
The AD8250 user interface consists of a parallel port that allows
users to set the gain in one of two ways (see Figure 1). A 2-bit word
sent via a bus can be latched using the WR input. An alternative is
to use the transparent gain mode where the state of the logic levels
at the gain port determines the gain.
–5
–10
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06288-023
The AD8250 is an instrumentation amplifier with digitally
programmable gains that has GΩ input impedance, low output
noise, and low distortion making it suitable for interfacing with
sensors and driving high sample rate analog-to-digital converters
(ADCs). It has a high bandwidth of 10 MHz, low THD of −110
dB and fast settling time of 615 ns (maximum) to 0.001%. Offset
drift and gain drift are guaranteed to 1.7 μV/°C and 10 ppm/°C,
respectively, for G = 10. In addition to its wide input common
voltage range, it boasts a high common-mode rejection of 80 dB
at G = 1 from dc to 50 kHz. The combination of precision dc
performance coupled with high speed capabilities makes the
AD8250 an excellent candidate for data acquisition. Furthermore,
this monolithic solution simplifies design and manufacturing
and boosts performance of instrumentation by maintaining a
tight match of internal resistors and amplifiers.
Figure 2. Gain vs. Frequency
Table 1. Instrumentation Amplifiers by Category
General
Purpose
AD82201
AD8221
AD8222
AD82241
AD8228
1
Zero Drift
AD82311
AD85531
AD85551
AD85561
AD85571
Mil
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD6271
AD6231
AD82231
High Speed
PGA
AD8250
AD8251
AD8253
Rail-to-rail output.
The AD8250 is available in a 10-lead MSOP package and is
specified over the −40°C to +85°C temperature range, making
it an excellent solution for applications where size and packing
density are important considerations.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
AD8250
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Bias Current Return Path ............................................... 17
Applications....................................................................................... 1
Input Protection ......................................................................... 17
General Description ......................................................................... 1
Reference Terminal .................................................................... 18
Functional Block Diagram .............................................................. 1
Common-Mode Input Voltage Range ..................................... 18
Revision History ............................................................................... 2
Layout .......................................................................................... 18
Specifications..................................................................................... 3
RF Interference ........................................................................... 19
Timing Diagram ........................................................................... 5
Driving an ADC ......................................................................... 19
Absolute Maximum Ratings............................................................ 6
Applications..................................................................................... 20
Maximum Power Dissipation ..................................................... 6
Differential Output .................................................................... 20
ESD Caution.................................................................................. 6
Setting Gains with a Microcontroller ...................................... 20
Pin Configuration and Function Descriptions............................. 7
Data Acquisition......................................................................... 21
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 22
Theory of Operation ...................................................................... 15
Ordering Guide .......................................................................... 22
Gain Selection ............................................................................. 15
www.BDTIC.com/ADI
Power Supply Regulation and Bypassing ................................ 17
REVISION HISTORY
5/08—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 6
Added Figure 17; Renumbered Sequentially ................................ 9
Changes to Figure 23...................................................................... 10
Changes to Figure 24 to Figure 26................................................ 11
Added Figure 29.............................................................................. 11
Changes to Figure 31...................................................................... 12
Deleted Figure 43 to Figure 46; Renumbered Sequentially ...... 14
Inserted Figure 45 and Figure 46.................................................. 14
Changes to Timing for Latched Gain Mode Section ................. 16
Changes to Layout Section and Coupling Noise Section .......... 18
Changes to Figure 59...................................................................... 21
1/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD8250
SPECIFICATIONS
+VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION RATIO (CMRR)
CMRR to 60 Hz with 1 kΩ Source Imbalance
G=1
G=2
G=5
G = 10
CMRR to 50 kHz
G=1
G=2
G=5
G = 10
NOISE
Voltage Noise, 1 kHz, RTI
G=1
G=2
G=5
G = 10
0.1 Hz to 10 Hz, RTI
G=1
G=2
G=5
G = 10
Current Noise, 1 kHz
Current Noise, 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Offset RTI VOS
Over Temperature
Average Temperature Coefficient
Offset Referred to the Input vs. Supply (PSR)
INPUT CURRENT
Input Bias Current
Over Temperature
Average Temperature Coefficient
Input Offset Current
Over Temperature
Average Temperature Coefficient
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1
G=2
G=5
G = 10
Settling Time 0.01%
G=1
G=2
G=5
G = 10
Conditions
Min
Typ
80
86
94
98
98
104
110
110
Max
Unit
+IN = −IN = −10 V to +10 V
dB
dB
dB
dB
+IN = −IN = −10 V to +10 V
80
86
90
90
dB
dB
dB
dB
40
27
21
18
www.BDTIC.com/ADI
2.5
2.5
1.5
1.0
μV p-p
μV p-p
μV p-p
μV p-p
pA/√Hz
pA p-p
±(70 + 200/G)
±(90 + 300/G)
±(64 + 1.5/G)
±(2 + 7/G)
±(200 + 600/G)
±(260 + 900/G)
±(1.2 + 5/G)
±(6 + 20/G)
μV
μV
μV/°C
μV/V
5
30
40
400
30
30
160
nA
nA
pA/°C
nA
nA
pA/°C
5
60
G = 1, 2, 5, 10
T = −40°C to +85°C
T = −40°C to +85°C
VS = ±5 V to ±15 V
T = −40°C to +85°C
T = −40°C to +85°C
5
T = −40°C to +85°C
T = −40°C to +85°C
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
10
10
10
3
MHz
MHz
MHz
MHz
ΔOUT = 10 V step
585
605
605
648
Rev. A | Page 3 of 24
ns
ns
ns
ns
AD8250
Parameter
Settling Time 0.001%
G=1
G=2
G=5
G = 10
Slew Rate
G=1
G=2
G=5
G = 10
Total Harmonic Distortion
GAIN
Gain Range
Gain Error
G=1
G = 2, 5, 10
Gain Nonlinearity
G=1
G=2
G=5
G = 10
Gain vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range
Over Temperature
OUTPUT
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
DIGITAL LOGIC
Digital Ground Voltage, DGND
Digital Input Voltage Low
Digital Input Voltage High
Digital Input Current
Gain Switching Time 1
tSU
tHD
t WR -LOW
t WR -HIGH
Conditions
ΔOUT = 10 V step
Min
Typ
Max
Unit
615
635
635
685
ns
ns
ns
ns
20
25
25
25
−110
f = 1 kHz, RL = 10 kΩ, ±10 V,
G = 1, 10 Hz to 22 kHz
band-pass filter
G = 1, 2, 5, 10
OUT = ±10 V
V/μs
V/μs
V/μs
V/μs
dB
1
OUT = −10 V to +10 V
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
RL = 10 kΩ, 2 kΩ, 600 Ω
All gains
10
V/V
0.03
0.04
%
%
6
8
8
10
10
ppm
ppm
ppm
ppm
ppm/°C
GΩ||pF
GΩ||pF
V
V
www.BDTIC.com/ADI
5.3||0.5
1.25||2
VS = ±5 V to ±15 V
T = −40°C to +85°C
−VS + 1.5
−VS + 1.6
+VS − 1.5
+VS − 1.7
T = −40°C to +85°C
−13.5
−13.5
+13.5
+13.5
37
20
+IN, −IN, REF = 0
1
+VS
−VS
1 ± 0.0001
Referred to GND
Referred to GND
Referred to GND
−VS + 4.25
DGND
2.8
0
+VS − 2.7
2.1
+VS
1
325
See Figure 3 timing diagram
See Figure 3 timing diagram
See Figure 3 timing diagram
See Figure 3 timing diagram
Rev. A | Page 4 of 24
20
10
20
40
V
V
mA
kΩ
μA
V
V/V
V
V
V
μA
ns
ns
ns
ns
ns
AD8250
Parameter
POWER SUPPLY
Operating Range
Quiescent Current, +IS
Quiescent Current, −IS
Over Temperature
TEMPERATURE RANGE
Specified Performance
1
Conditions
Min
Typ
Max
Unit
4.1
3.7
±15
4.5
4.5
4.5
V
mA
mA
mA
+85
°C
±5
T = −40°C to +85°C
−40
Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
tWR-HIGH
tWR-LOW
WR
tSU
tHD
06288-057
A0, A1
Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
www.BDTIC.com/ADI
Rev. A | Page 5 of 24
AD8250
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Output Short-Circuit Current
Common-Mode Input Voltage
Differential Input Voltage
Digital Logic Inputs
Storage Temperature Range
Operating Temperature Range3
Lead Temperature (Soldering, 10 sec)
Junction Temperature
θJA (Four-Layer JEDEC Standard Board)
Package Glass Transition Temperature
Rating
±17 V
See Figure 4
Indefinite1
+VS + 13 V, −VS − 13 V
+VS + 13 V, −VS − 13 V2
±VS
−65°C to +125°C
−40°C to +85°C
300°C
140°C
112°C/W
140°C
1
Assumes that the load is referenced to midsupply.
Current must be kept to less than 6 mA.
3
Temperature for specified performance is −40°C to +85°C. For performance
to 125°C, see the Typical Performance Characteristics section.
2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load (RL) is referenced
to midsupply, the total drive power is VS/2 × IOUT, some of which
is dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
⎛V V
PD = (VS × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
⎞ VOUT 2
⎟–
⎟
RL
⎠
In single-supply operation with RL referenced to −VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a four-layer JEDEC
standard board.
www.BDTIC.com/ADI
2.00
The still-air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
TJ = TA + (PD × θJA)
Rev. A | Page 6 of 24
06288-004
The maximum safe power dissipation in the AD8250 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8250. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
MAXIMUM POWER DISSIPATION (W)
MAXIMUM POWER DISSIPATION
AD8250
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN 1
DGND 2
10 +IN
AD8250
9
REF
8 +VS
TOP VIEW
A0 4 (Not to Scale) 7 OUT
A1 5
6
WR
06288-005
–VS 3
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
−IN
DGND
−VS
A0
A1
WR
OUT
+VS
REF
+IN
Description
Inverting Input Terminal. True differential input.
Digital Ground.
Negative Supply Terminal.
Gain Setting Pin (LSB).
Gain Setting Pin (MSB).
Write Enable.
Output Terminal.
Positive Supply Terminal.
Reference Voltage Terminal.
Noninverting Input Terminal. True differential input.
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Rev. A | Page 7 of 24
AD8250
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted.
500
1400
1200
400
NUMBER OF UNITS
NUMBER OF UNITS
1000
800
600
300
200
400
100
–120
–90
–60
–30
0
30
60
90
120
CMRR (µV/V)
0
06288-006
0
–30
–20
–10
0
10
20
30
INPUT OFFSET CURRENT (nA)
06288-009
200
Figure 9. Typical Distribution of Input Offset Current
Figure 6. Typical Distribution of CMRR, G = 1
350
90
300
80
70
NOISE RTI (nV/ Hz)
NUMBER OF UNITS
250
60
www.BDTIC.com/ADI
200
150
50
G=1
40
G=2
30
100
G=5
20
50
–200
–150
–100
–50
0
50
100
150
200
OFFSET VOLTAGE RTI (µV)
06288-010
0
06288-007
0
G = 10
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 10. Voltage Spectral Density Noise vs. Frequency
Figure 7. Typical Distribution of Offset Voltage, VOSI
600
400
300
200
2µV/DIV
0
–30
–20
–10
0
10
20
INPUT BIAS CURRENT (nA)
30
1s/DIV
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
Figure 8. Typical Distribution of Input Bias Current
Rev. A | Page 8 of 24
06288-011
100
06288-008
NUMBER OF UNITS
500
AD8250
150
G = 10
130
G=5
PSRR (dB)
110
G=2
90
G=1
70
50
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 10
Figure 15. Positive PSRR vs. Frequency, RTI
150
18
16
130
14
G = 10
110
12
PSRR (dB)
G=5
10
8
2
0
G=2
70
G=1
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30
1
10
100
1k
10k
10
100k
1
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 13. Current Noise Spectral Density vs. Frequency
06288-017
4
90
50
06288-013
6
Figure 16. Negative PSRR vs. Frequency, RTI
1s/DIV
9
8
7
6
5
4
3
2
1
0
0.01
Figure 14. 0.1 Hz to 10 Hz Current Noise
1
0.1
WARMUP TIME (Minutes)
Figure 17. Change in Offset Voltage, RTI vs. Warmup Time
Rev. A | Page 9 of 24
10
06288-117
140pA/DIV
CHANGE IN OFFSET VOLTAGE, RTI (µV)
10
06288-014
CURRENT NOISE (pA/ Hz)
06288-016
1s/DIV
06288-012
30
1µV/DIV
10
15
8
10
6
4
ΔCMRR (µV/V)
IB–
0
IB+
2
0
–2
–5
–4
IOS
–6
–10
06288-049
5
–8
–15
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–10
–50
06288-019
INPUT BIAS CURRENT AND OFFSET CURRENT (nA)
AD8250
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
Figure 21. CMRR vs. Temperature, G = 1
Figure 18. Input Bias Current and Offset Current vs. Temperature
25
140
G = 10
G=5
G = 10
20
120
G=5
15
G=1
GAIN (dB)
G=2
80
10
G=2
5
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60
G=1
0
40
20
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
–10
1k
10k
40
GAIN NONLINEARITY (10ppm/DIV)
G=5
80
G=1
60
40
100M
f = 1kHz
30
20
10
0
–10
–20
20
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance
1M
–40
–10
06288-024
–30
06288-021
CMRR (dB)
100
G=2
10M
Figure 22. Gain vs. Frequency
140
120
1M
FREQUENCY (Hz)
Figure 19. CMRR vs. Frequency
G = 10
100k
06288-023
–5
06288-020
CMRR (dB)
100
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω
Rev. A | Page 10 of 24
AD8250
16
0V, +13.8V
f = 1kHz
20
10
0
–10
–20
–40
–10
06288-025
–30
–8
–6
–4
–2
0
2
4
6
8
12
–3.8V, +1.9V
–3.8V, –1.9V
–4
–8
–13.8V, –6.9V
+13.8V, –6.9V
–12
0V, –14V
–12
–8
INPUT COMMON-MODE VOLTAGE (V)
10
0
8
0V, +13.8V
–14.1V, +13.6V
12
16
+13.6V, +13.1V
VS = ±15V
12
8
+0V, +3.5V
4
–4.2V, +2.2V
+4.3V, +2.1V
VS = ±5V
0
+4.3V, –2.1V
–4.2V, –2.0V
–4
–8
–6
–4
–2
0
2
4
6
8
0V, –4.1V
–8
–12
–14.1V, –13.6V
–16
–16
–12
–8
10
OUTPUT VOLTAGE (V)
0
4
8
16
35
IB+
IB–
IOS
30
30
25
10
0
–10
–20
06288-027
–30
–6
–4
–2
0
2
4
6
8
20
15
10
5
0
–5
06288-129
INPUT BIAS CURRENT AND
OFFSET CURRENT (nA)
20
–8
12
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 10
f = 1kHz
–40
–10
+13.6V, –13.1V
0V, –14V
–4
OUTPUT VOLTAGE (V)
Figure 25. Gain Nonlinearity vs. Output Voltage, G = 5, RL = 10 kΩ, 2 kΩ, 600 Ω
GAIN NONLINEARITY (10ppm/DIV)
4
06288-029
–40
–10
40
0
www.BDTIC.com/ADI
06288-026
GAIN NONLINEARITY (10ppm/DIV)
16
20
–30
–4
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1
f = 1kHz
30
–20
+3.8V, –2.1V
0V, –4.0V
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, RL = 10 kΩ, 2 kΩ, 600 Ω
–10
+3.9V, +1.9V
VS = ±5V
0
OUTPUT VOLTAGE (V)
40
+13.8V, +6.9V
0V, +3.7V
4
–16
–16
10
VS = ±15V
–13.8V, +6.9V
8
06288-028
30
INPUT COMMON-MODE VOLTAGE (V)
GAIN NONLINEARITY (10ppm/DIV)
40
–10
–15
–15
10
OUTPUT VOLTAGE (V)
–10
–5
0
5
10
15
COMMON-MODE VOLTAGE (V)
Figure 26. Gain Nonlinearity vs. Output Voltage, G = 10, RL = 10 kΩ, 2 kΩ, 600 Ω
Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage
Rev. A | Page 11 of 24
AD8250
+VS
OUTPUT VOLTAGE SWING
REFERRED TO SUPPLY VOLTAGE (V)
–1
+85°C
+125°C
–2
+25°C
–40°C
+2
+85°C
–40°C
+25°C
+1
–VS
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±VS)
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ
+125°C
–0.4
–0.6
–0.8
–1.0
+85°C
+1.0
+25°C
–40°C
+25°C
–40°C
+0.8
+0.6
+0.4
+0.2
–VS
+125°C
06288-030
INPUT VOLTAGE
REFERRED TO SUPPLY VOLTAGE (V)
–0.2
+85°C
+125°C
4
6
8
10
12
14
16
SUPPLY VOLTAGE (±VS)
06288-033
+VS
Figure 33. Output Voltage Swing vs. Supply Voltage, G = 10, RL = 10 kΩ
15
15
+25°C
+VS
10
FAULT CONDITION
(OVER DRIVEN INPUT)
G = 10
5
OUTPUT VOLTAGE SWING (V)
FAULT CONDITION
(OVER DRIVEN INPUT)
G = 10
+IN
0
–IN
–40°C
5
+85°C
+125°C
0
+85°C
www.BDTIC.com/ADI
–5
+125°C
–10
–10
–40°C
–VS
–12
–8
–4
0
4
8
12
+25°C
16
DIFFERENTIAL INPUT VOLTAGE (V)
–15
100
06288-031
–15
–16
Figure 31. Fault Current Draw vs. Input Voltage, G = 10, RL = 10 kΩ
+VS
+VS
OUTPUT VOLTAGE SWING
REFERRED TO SUPPLY VOLTAGE (V)
–0.4
+125°C
–0.6
–0.8
–1.0
+25°C
+85°C
–40°C
+25°C
–40°C
+85°C
+1.0
+0.8
+0.6
+125°C
+0.4
–0.4 +85°C
+125°C
–0.8
–1.2
+25°C
–1.6
4
6
8
10
12
SUPPLY VOLTAGE (±VS)
14
16
Figure 32. Output Voltage Swing vs. Supply Voltage, G = 10, RL = 2 kΩ
Rev. A | Page 12 of 24
–40°C
–2.0
+2.0
+1.6
+25°C
–40°C
+1.2
+0.8
+0.4
06288-032
OUTPUT VOLTAGE SWING
REFERRED TO SUPPLY VOLTAGE (V)
10k
Figure 34. Output Voltage Swing vs. Load Resistance
–0.2
+0.2
–VS
1k
LOAD RESISTANCE (Ω)
06288-034
–5
–VS
+125°C
+85°C
0
2
4
06288-035
CURRENT (mA)
10
6
8
10
12
14
OUTPUT CURRENT (mA)
Figure 35. Output Voltage Swing vs. Output Current
16
AD8250
NO
LOAD
47pF
100pF
VOUT (V)
5V/DIV
605ns TO 0.01%
635ns TO 0.001%
2µs/DIV
2µs/DIV
06288-036
20mV/DIV
TIME (µs)
06288-039
0.002%/DIV
TIME (µs)
Figure 36. Small Signal Pulse Response for Various Capacitive Loads
Figure 39. Large Signal Pulse Response and Settling Time
G = 5, RL = 10 kΩ
5V/DIV
5V/DIV
585ns TO 0.01%
615ns TO 0.001%
648ns TO 0.01%
685ns TO 0.001%
0.002%/DIV
2µs/DIV
06288-037
www.BDTIC.com/ADI
2µs/DIV
TIME (µs)
06288-040
0.002%/DIV
TIME (µs)
Figure 37. Large Signal Pulse Response and Settling Time,
G = 1, RL = 10 kΩ
Figure 40. Large Signal Pulse Response and Settling Time
G = 10, RL = 10 kΩ
VOUT (V)
5V/DIV
605ns TO 0.01%
635ns TO 0.001%
20mV/DIV
2µs/DIV
TIME (µs)
TIME (µs)
Figure 38. Large Signal Pulse Response and Settling Time
G = 2, RL = 10 kΩ
Figure 41. Small Signal Response
G = 1, RL = 2 kΩ, CL = 100 pF
Rev. A | Page 13 of 24
06288-042
2µs/DIV
06288-038
0.002%/DIV
AD8250
–50
G
G
G
G
–55
–60
–65
=1
=2
=5
= 10
VOUT (V)
THD + N (dB)
–70
–75
–80
–85
–90
–95
–100
–105
TIME (µs)
–115
06288-043
2µs/DIV
06288-149
–110
20mV/DIV
–120
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 45. Total Harmonic Distortion + Noise vs. Frequency,
10 Hz to 22 kHz Band-Pass Filter, RL = 2 kΩ
Figure 42. Small Signal Response
G = 2, RL = 2 kΩ, CL = 100 pF
–50
G
G
G
G
–60
=1
=2
=5
= 10
VOUT (V)
THD + N (dB)
–70
–80
www.BDTIC.com/ADI
–90
TIME (µs)
–110
10
100
1k
10k
100k
06288-150
2µs/DIV
06288-044
–100
20mV/DIV
1M
FREQUENCY (Hz)
Figure 43. Small Signal Response
G = 5, RL = 2 kΩ, CL = 100 pF
20mV/DIV
2µs/DIV
TIME (µs)
06288-045
VOUT (V)
Figure 46. Total Harmonic Distortion + Noise vs. Frequency,
10 Hz to 500 kHz Band-Pass Filter, RL = 2 kΩ
Figure 44. Small Signal Response,
G = 10, RL = 2 kΩ, CL = 100 pF
Rev. A | Page 14 of 24
AD8250
THEORY OF OPERATION
+VS
+VS
A0
A1
2.2kΩ
+VS
–IN
–VS
–VS
2.2kΩ
10kΩ
A1
10kΩ
–VS
+VS
DIGITAL
GAIN
CONTROL
OUT
A3
–VS
+VS
+VS
10kΩ
A2
REF
2.2kΩ
+VS
–VS
–VS
+VS
2.2kΩ
DGND
WR
–VS
06288-054
+IN
10kΩ
–VS
Figure 47. Simplified Schematic
www.BDTIC.com/ADI
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a
logic high or logic low voltage applied to A0 and A1. Figure 48
shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative
supply to engage transparent gain mode. In this mode, any change
in voltage applied to A0 and A1 from logic low to logic high, or
vice versa, immediately results in a gain change. Table 5 is the
truth table for transparent gain mode, and Figure 48 shows the
AD8250 configured in transparent gain mode.
All internal amplifiers employ distortion cancellation circuitry
and achieve high linearity and ultralow THD. Laser trimmed
resistors allow for a maximum gain error of less than 0.03%
for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout
optimized for high CMRR over frequency enables the AD8250
to offer a guaranteed minimum CMRR over frequency of 80 dB
at 50 kHz (G = 1). The balanced input reduces the parasitics
that, in the past, adversely affected CMRR performance.
+15V
10μF
0.1µF
WR
A1
A0
+IN
REF
–IN
10μF
Logic low and logic high voltage limits are listed in the
Specifications section. Typically, logic low is 0 V and logic high
is 5 V; both voltages are measured with respect to DGND. See
Table 2 for the permissible voltage range of DGND. The gain of
the AD8250 can be set using two methods.
+5V
G = 10
AD8250
DGND
GAIN SELECTION
–15V
+5V
DGND
0.1µF
–15V
NOTE:
1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS.
THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE
THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE
SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.
06288-055
The AD8250 is a monolithic instrumentation amplifier based
on the classic, 3-op-amp topology as shown in Figure 47. It is
fabricated on the Analog Devices, Inc., proprietary iCMOS®
process that provides precision, linear performance, and a
robust digital interface. A parallel interface allows users to
digitally program gains of 1, 2, 5, and 10. Gain control is achieved
by switching resistors in an internal, precision resistor array (as
shown in Figure 47). Although the AD8250 has a voltage feedback
topology, the gain bandwidth product increases for gains of 1, 2,
and 5 because each gain has its own frequency compensation.
This results in maximum bandwidth at higher gains.
Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10
Rev. A | Page 15 of 24
AD8250
Table 5. Truth Table Logic Levels for Transparent Gain Mode
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
WR
A1
A0
Gain
−VS
−VS
−VS
−VS
Low
Low
High
High
Low
High
Low
High
1
2
5
10
High to low
High to low
High to low
High to low
Low to low
Low to high
High to high
Low
Low
High
High
X1
X1
X1
Low
High
Low
High
X1
X1
X1
Change to 1
Change to 2
Change to 5
Change to 10
No change
No change
No change
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8250 can be set using WR as a latch,
allowing other devices to share A0 and A1. Figure 49 shows a
schematic using this method, known as latched gain mode. The
AD8250 is in this mode when WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0
and A1 are read on the downward edge of the WR signal as it
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table in Table 6 for more information on these gain changes.
+15V
WR
10μF
0.1µF
A1
A1
+
A0
G = PREVIOUS
STATE
+5V
0V
G = 10
AD8250
REF
–
–IN
DGND
On power-up, the AD8250 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8250 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, tSU, before the downward edge of
WR latches in the gain. Similarly, they must be held for a
minimum hold time of tHD after the downward edge of WR to
ensure that the gain is latched in correctly. After tHD, A0 and A1
can change logic levels, but the gain does not change (until the
next downward edge of WR). The minimum duration that WR
can be held high is t WR -HIGH, and the minimum duration that
WR can be held low is t WR -LOW. Digital timing specifications are
listed in Table 2. The time required for a gain change is dominated
by the settling time of the amplifier. A timing diagram is shown
in Figure 50.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8250. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
DGND
0.1µF
–15V
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.
06288-056
10μF
X = don’t care.
www.BDTIC.com/ADI
A0
+IN
+5V
0V
+5V
0V
WR
1
Figure 49. Latched Gain Mode, G = 10
tWR-HIGH
tWR-LOW
WR
tSU
tHD
06288-057
A0, A1
Figure 50. Timing Diagram for Latched Gain Mode
Rev. A | Page 16 of 24
AD8250
INCORRECT
POWER SUPPLY REGULATION AND BYPASSING
CORRECT
+VS
The AD8250 has high PSRR. However, for optimal performance,
a stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be
used to decouple the amplifier.
+VS
AD8250
AD8250
REF
Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum
capacitor can be used farther away from the part (see Figure 51)
and, in most cases, it can be shared by other precision integrated
circuits.
REF
–VS
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
+VS
0.1µF
WR
A1
+IN
10µF
AD8250
AD8250
REF
A0
REF
10MΩ
OUT
–VS
LOAD
–IN
–VS
THERMOCOUPLE
REF
THERMOCOUPLE
+VS
DGND
+VS
DGND
10µF
–VS
06288-058
C
0.1µF
C
1
fHIGH-PASS = 2πRC
AD8250
R
AD8250
www.BDTIC.com/ADI
C
Figure 51. Supply Decoupling, REF, and Output Referred to Ground
REF
C
REF
R
INPUT BIAS CURRENT RETURN PATH
The AD8250 input bias current must have a return path to its
local analog ground. When the source, such as a thermocouple,
cannot provide a return current path, one should be created
(see Figure 52).
–VS
–VS
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
06288-059
AD8250
Figure 52. Creating an IBIAS Return Path
INPUT PROTECTION
All terminals of the AD8250 are protected against ESD. Note
that 2.2 kΩ series resistors precede the ESD diodes as shown in
Figure 47. The resistors limit current into the diodes and allow
for dc overload conditions 13 V above the positive supply and
13 V below the negative supply. An external resistor should be
used in series with each input to limit current for voltages greater
than 13 V beyond either supply rail. In either scenario, the
AD8250 safely handles a continuous 6 mA current at room
temperature. For applications where the AD8250 encounters
extreme overload voltages, external series resistors and low
leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s,
should be used.
Rev. A | Page 17 of 24
AD8250
REFERENCE TERMINAL
The reference terminal, REF, is at one end of a 10 kΩ resistor
(see Figure 47). The instrumentation amplifier output is referenced
to the voltage on the REF terminal; this is useful when the output
signal needs to be offset to voltages other than its local analog
ground. For example, a voltage source can be tied to the REF
pin to level shift the output so that the AD8250 can interface
with a single-supply ADC. The allowable reference voltage
range is a function of the gain, common-mode input, and
supply voltages. The REF pin should not exceed either +VS
or −VS by more than 0.5 V.
For best performance, especially in cases where the output is
not measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic
resistance can adversely affect CMRR and gain accuracy.
INCORRECT
CORRECT
AD8250
AD8250
VREF
The output voltage of the AD8250 develops with respect to the
potential on the reference terminal. Take care to tie REF to the
appropriate local analog ground or to connect it to a voltage that
is referenced to the local analog ground.
Coupling Noise
To prevent coupling noise onto the AD8250, do the following
guidelines:
•
Do not run digital lines under the device.
•
Run the analog ground plane under the AD8250.
•
Shield fast switching signals with digital ground to avoid
radiating noise to other sections of the board, and never
run them near analog signal paths.
•
Avoid crossover of digital and analog signals.
•
Connect digital and analog ground at one point only
(typically under the ADC).
•
Use the large traces on power supply lines to ensure a low
impedance path. Decoupling is necessary; follow the
guidelines listed in the Power Supply Regulation and
Bypassing section.
VREF
+
OP1177
06288-060
www.BDTIC.com/ADI
–
Common-Mode Rejection
Figure 53. Driving the Reference Pin
COMMON-MODE INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8250 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8250 experience a combination of both the gained
signal and the common-mode signal. This combined signal can be
limited by the voltage supplies even when the individual input and
output signals are not. Figure 27 and Figure 28 show the allowable
common-mode input voltage ranges for various output voltages,
supply voltages, and gains.
LAYOUT
Grounding
In mixed-signal circuits, low level analog signals need to be
isolated from the noisy digital environment. Designing with the
AD8250 is no exception. Its supply voltages are referenced to an
analog ground. Its digital circuit is referenced to a digital ground.
Although it is convenient to tie both grounds to a single ground
plane, the current traveling through the ground wires and PCB
can cause errors. Therefore, use separate analog and digital ground
planes. Analog and digital ground should meet at only one point:
star ground.
The AD8250 has high CMRR over frequency, giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical instrumentation amplifiers
whose CMRR falls off around 200 Hz. Typical instrumentation
amplifiers often need common-mode filters at their inputs to
compensate for this shortcoming. The AD8250 is able to reject
CMRR over a greater frequency range, reducing the need for
input common-mode filtering.
Careful board layout maximizes system performance. To
maintain high CMRR over frequency, lay out the input traces
symmetrically. Ensure that the traces maintain resistive and
capacitive balance; this holds for additional PCB metal layers
under the input pins and traces. Source resistance and capacitance should be placed as close to the inputs as possible. Should a
trace cross the inputs (from another layer), route it perpendicular
to the input traces.
Rev. A | Page 18 of 24
AD8250
RF INTERFERENCE
DRIVING AN ADC
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 54. The filter
limits the input signal bandwidth according to the following
relationship:
An instrumentation amplifier is often used in front of an ADC
to provide CMRR. Usually, instrumentation amplifiers require a
buffer to drive an ADC. However, the low output noise, low
distortion, and low settle time of the AD8250 make it an excellent
ADC driver.
FilterFreq DIFF =
FilterFreqCM =
1
2π R(2C D + CC )
1
2π RCC
where CD ≥ 10 CC.
+15V
0.1µF
10µF
In this example, a 1 nF capacitor and a 49.9 Ω resistor create an
antialiasing filter for the AD7612. The 1 nF capacitor stores and
delivers the necessary charge to the switched capacitor input of
the ADC. The 49.9 Ω series resistor reduces the burden of the
1 nF load from the amplifier and isolates it from the kickback
current injected from the switched capacitor input of the AD7612.
Selecting too small a resistor improves the correlation between
the voltage at the output of the AD8250 and the voltage at the
input of the AD7612 but may destabilize the AD8250. A tradeoff must be made between selecting a resistor small enough to
maintain accuracy and large enough to maintain stability.
+15V
CC
R
+IN
10μF
AD8250
CD
R
0.1µF
WR
OUT
+12V
A1
A0
+IN
REF
–IN
–12V
0.1μF
0.1μF
49.9Ω
www.BDTIC.com/ADI
AD8250
CC
REF
10µF
06288-061
–15V
+5V
–IN
ADR435
DGND
10μF
Figure 54. RFI Suppression
Values of R and CC should be chosen to minimize RFI. A
mismatch between the R × CC at the positive input and the
R × CC at the negative input degrades the CMRR of the AD8250.
By using a value of CD that is 10 times larger than the value of
CC, the effect of the mismatch is reduced and performance is
improved.
Rev. A | Page 19 of 24
DGND
0.1µF
06288-062
0.1µF
AD7612
1nF
–15V
Figure 55. Driving an ADC
AD8250
APPLICATIONS
DIFFERENTIAL OUTPUT
SETTING GAINS WITH A MICROCONTROLLER
+15V
In certain applications, it is necessary to create a differential
signal. High resolution ADCs often require a differential input.
In other cases, transmission over a long distance can require
differential signals for better immunity to interference.
10μF
0.1µF
WR
A1
A0
+IN
Figure 57 shows how to configure the AD8250 to output a
differential signal. An op amp, the AD817, is used in an inverting
topology to create a differential voltage. VREF sets the output
midpoint according to the equation shown in the figure. Errors
from the op amp are common to both outputs and are thus
common mode. Likewise, errors from using mismatched resistors
cause a common-mode dc offset error. Such errors are rejected
in differential signal processing by differential input ADCs or
instrumentation amplifiers.
MICROCONTROLLER
+
AD8250
REF
–
–IN
DGND
DGND
0.1µF
06288-063
10μF
–15V
Figure 56. Programming Gain Using a Microcontroller
When using this circuit to drive a differential ADC, VREF can be
set using a resistor divider from the ADC reference to make the
output ratiometric with the ADC.
+12V
0.1μF
AMPLITUDE
WR
+5V
www.BDTIC.com/ADI
A1
A0
+IN
–5V
AMPLITUDE
+
VOUTA = VIN + VREF
2
AD8250
VIN
G=1
–
0.1μF
+2.5V
0V
–2.5V
REF
TIME
4.99kΩ
DGND
–
–12V
–12V
4.99kΩ
10pF
+
AD817
+12V
VREF
0V
AMPLITUDE
10μF
0.1µF
–12V
0.1µF
10μF
DGND
VOUTB = –VIN + VREF
2
Figure 57. Differential Output with Level Shift
Rev. A | Page 20 of 24
+2.5V
0V
–2.5V
TIME
06288-064
+12V
AD8250
0
DATA ACQUISITION
–10
–20
The AD8250 makes an excellent instrumentation amplifier for
use in data acquisition systems. Its wide bandwidth, low distortion,
low settling time, and low noise enable it to condition signals in
front of a variety of 16-bit ADCs.
–30
AMPLITUDE (dB)
–40
Figure 59 shows a schematic of the AD825x data acquisition
demonstration board. The quick slew rate of the AD8250 allows
it to condition rapidly changing signals from the multiplexed
inputs. An FPGA controls the AD7612, AD8250, and ADG1209.
In addition, mechanical switches and jumpers allow users to pin
strap the gains when in transparent gain mode.
–50
–60
–70
–80
–90
–100
–110
–120
–140
0
5
10
15
20
25
30
35
40
45
Figure 58. FFT of the AD825x DAQ Demo Board Using the AD8250,
1 kHz Signal
JMP
+12V +
+12V
0.1µF
10µF
VDD
JMP
–12V
+5V
–VS
2kΩ
10µF
GND
14
806Ω
+
2
EN
DGND
DGND
JMP
www.BDTIC.com/ADI
+CH2
+CH3
+CH4
–CH4
–CH3
–CH2
–CH1
806Ω
806Ω
806Ω
806Ω
806Ω
806Ω
806Ω
4 S1A
+5V
DGND
5 S2A
6 S3A
0Ω
DA 8
0Ω
ADG1209
10 S4B
0Ω
DB 9
11 S3B
13
ALTERA
EPF6010ATC144-3
DGND 6
7 S4A
12 S2B
2kΩ
2
0Ω
CC +IN
CD
GND 15
10
+
5
A1 4
A0
AD8250 REF
–IN
9
1 –
–VS
CC
+VS 3
8
A0
S1B A1
VSS 16
WR
1
7
+IN
OUT
0Ω 49.9Ω
AD7612
1nF
ADR435
C4
0.1µF
C3
0.1µF
3
DGND
+12V –12V
JMP
0.1µF
–12V
+5V
2kΩ
DGND
JMP
+5V
R8
2kΩ
06288-065
+CH1
50
FREQUENCY (kHz)
This system achieved −111 dB of THD at 1 kHz and a signal-tonoise ratio of 91 dB during testing, as shown in Figure 58.
DGND
Figure 59. Schematic of ADG1209, AD8250, and AD7612 in the AD825x DAQ Demo Board
Rev. A | Page 21 of 24
06288-066
–130
AD8250
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
6
5
5.15
4.90
4.65
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 60. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
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ORDERING GUIDE
Model
AD8250ARMZ 1
AD8250ARMZ-RL1
AD8250ARMZ-R71
AD8250-EVALZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Package Option
RM-10
RM-10
RM-10
Branding
H00
H00
H00
AD8250
NOTES
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Rev. A | Page 23 of 24
AD8250
NOTES
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©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06288-0-5/08(A)
Rev. A | Page 24 of 24