DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter AD8333

DC to 50 MHz, Dual I/Q Demodulator and
Phase Shifter
AD8333
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PH1x
RF1P
RF1N
0°
ENBL
I1PO/
I1NO
Φ
Q1PO/
Q1NO
Φ
Q2PO/
Q2NO
Φ
I2PO/
I2NO
AD8333
90°
4LOP
4LON
Φ
÷4
90°
RSET
0°
RF2P
RF2N
PH2x
APPLICATIONS
05543-001
Dual integrated I/Q demodulator
16 phase select options on each output (22.5° per step)
Quadrature demodulation accuracy
Phase accuracy: ±0.1°
Amplitude balance: ±0.05 dB
Bandwidth
4 × LO: 100 kHz to 200 MHz
RF: dc to 50 MHz
Baseband: determined by external filtering
Output dynamic range: 159 dB/Hz
LO drive > 0 dBm (50 Ω); 4 × LO > 1 MHz
Supply: ±5 V
Power consumption: 190 mW/channel (380 mW total)
Power-down
Figure 1.
Medical imaging (CW ultrasound beamforming)
Phased array systems (radar and adaptive antennas)
Communication receivers
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GENERAL DESCRIPTION
The AD8333 is a dual-phase shifter and I/Q demodulator that
enables coherent summing and phase alignment of multiple
analog data channels. It is the first solid-state device suitable for
beamformer circuits, such as those used in high performance
medical ultrasound equipment featuring CW Doppler. The RF
inputs interface directly with the outputs of the dual-channel,
low noise preamplifiers included in the AD8332.
A divide-by-4 circuit generates the internal 0° and 90° phases
of the local oscillator (LO) that drive the mixers of a pair of
matched I/Q demodulators.
The AD8333 can be applied as a major element in analog
beamformer circuits in medical ultrasound equipment.
The AD8333 features an asynchronous reset pin. When used
in arrays, the reset pin sets all the LO dividers in the same state.
Sixteen discrete phase rotations in 22.5° increments can be selected
independently for each channel. For example, if Channel 1 is used
as a reference and the RF signal applied to Channel 2 has an I/Q
phase lead of 45°, Channel 2 can be phase aligned with Channel 1
by choosing the correct code.
Phase shift is defined by the output of one channel relative to
another. For example, if the code of Channel 1 is adjusted to
0000 and that of Channel 2 is adjusted to 0001 and the same
signal is applied to both RF inputs, the output of Channel 2
leads that of Channel 1 by 22.5°.
The I and Q outputs are provided as currents to facilitate
summation. The summed current outputs are converted to
voltages by a high dynamic range, current-to-voltage (I-V)
converter, such as the AD8021, configured as a transimpedance
amplifier. The resultant signal is then applied to a high resolution
ADC, such as the AD7665 (16 bit/570 kSPS).
The two I/Q demodulators can be used independently in other
nonbeamforming applications. In that case, a transimpedance
amplifier is needed for each of the I and Q outputs, four in total
for the dual I/Q demodulator.
The dynamic range is 159 dB/Hz at the I and Q outputs, but the
following transimpedance amplifier is an important element in
maintaining the overall dynamic range, and attention needs to
be paid to optimal component selection and design.
The AD8333 is available in a 32-lead LFCSP (5 mm × 5 mm)
package for the industrial temperature range of −40°C to +85°C.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2008 Analog Devices, Inc. All rights reserved.
AD8333
TABLE OF CONTENTS
Features .............................................................................................. 1 Dynamic Range Inflation .......................................................... 22 Applications ....................................................................................... 1 Disabling the Current Mirror and Decreasing Noise ............ 22 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 24 General Description ......................................................................... 1 Logic Inputs and Interfaces ....................................................... 24 Revision History ............................................................................... 2 Reset Input .................................................................................. 24 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Connecting to the LNA of the
AD8331/AD8332/AD8334/AD8335 VGAs ............................ 24 ESD Caution .................................................................................. 5 Interfacing to Other Amplifiers ............................................... 25 Pin Configuration and Function Descriptions ............................. 6 LO Input ...................................................................................... 25 Equivalent Input Circuits ................................................................ 7 Evaluation Board ............................................................................ 26 Typical Performance Characteristics ............................................. 8 Features and Options ................................................................. 26 Test Circuits ..................................................................................... 14 Measurement Setup.................................................................... 27 Theory of Operation ...................................................................... 17 Evaluation Board Schematic and Artwork.................................. 28 Quadrature Generation ............................................................. 17 Board Layout ............................................................................... 30 I/Q Demodulator and Phase Shifter ........................................ 17 Ordering Information .................................................................... 31 Dynamic Range and Noise ........................................................ 18 Bill of Materials ........................................................................... 31 Summation of Multiple Channels (Analog Beamforming) ........ 19 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 www.BDTIC.com/ADI
Phase Compensation and Analog Beamforming ................... 19 Channel Summing...................................................................... 20 REVISION HISTORY
9/08—Rev. B to Rev. C
Changes to Figure 1 .......................................................................... 1
Changes to General Description Section ...................................... 1
Change to Table 2 ............................................................................. 5
Changes to Figure 4 and Figure 6 ................................................... 7
Change to Figure 18 ......................................................................... 9
Changes to Dynamic Range and Noise Section ......................... 18
Changes to Connecting to the LNA of the AD8331/AD8332/
AD8334/AD8335 VGAs Section ............................................. 24
Added Interfacing to Other Amplifiers Heading ....................... 25
Changes to Figure 61 ...................................................................... 25
Incorporated AD8333-EVALZ Data Sheet.................................. 26
Changes to Evaluation Board Section ................................. 26
Changes to Features and Options Section .......................... 26
Changes to Table 5 ................................................................. 26
Replaced the Phase Bits Section with the Phase Nibble
Section ................................................................................ 26
Deleted Table 2 ......................................................................... 3
Changes to LNA Input Impedance Section ........................ 26
Changes to Current Summing Section ................................ 26
Changes to Measurement Setup Section ............................. 27
Moved Figure 63; Changes to Figure 63.............................. 27
Changes to Figure 64 ............................................................. 28
Moved Figure 70 ..................................................................... 30
Changes to Table 7 ................................................................. 31
Deleted Figure 62; Renumbered Sequentially ............................ 26
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
5/07—Rev. A to Rev. B
Changes to Features and Figure 1 ...................................................1
Changes to Table 1.............................................................................3
Changes to Figure 41 to Figure 43................................................ 14
Changes to Figure 44 to Figure 47................................................ 15
Changes to Figure 48 to Figure 51................................................ 16
Changes to Figure 55...................................................................... 20
Changes to Evaluation Board Section.......................................... 25
Changes to Ordering Guide .......................................................... 27
5/06—Rev. 0 to Rev. A
Changes to Figure 62...................................................................... 26
10/05—Revision 0: Initial Version
Rev. C | Page 2 of 32
AD8333
SPECIFICATIONS
VS = ±5 V, TA = 25°C, f4LO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm, single-ended, sine wave; per channel performance, dBm
(50 Ω), unless otherwise noted (see Figure 41).
Table 1.
Parameter
OPERATING CONDITIONS
LO Frequency Range
RF Frequency Range
Baseband Bandwidth
LO Input Level
VSUPPLY (VS)
Temperature Range
DEMODULATOR PERFORMANCE
RF Differential Input Impedance
LO Differential Input Capacitance
Transconductance
Dynamic Range
Maximum RF Input Swing
Peak Output Current (No Filtering)
Conditions
Min
4× internal LO at Pin 4LOP and Pin 4LON
Square wave
Sine wave, see Figure 22
Mixing
Limited by external filtering
See Figure 22
0.01
2
DC
DC
±4.5
−40
Demodulated IOUT/VIN, each I or Q output after low-pass
filtering measured from RF inputs, all phases
IP1dB, input-referred noise (dBm)
Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN
0° phase shift
45° phase shift
Reference = 50 Ω
Reference = 1 V rms
fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz
Baseband tones: −7 dBm at 8 kHz and 13 kHz
Baseband tones: −1 dBm at 8 kHz and −31 dBm at 13 kHz
fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz
Measured at RF inputs, worst phase, measured into 50 Ω
(limited by measurement)
Measured at baseband outputs, worst phase, AD8021 disabled,
measured into 50 Ω
All codes
Output noise/conversion gain
Output noise ÷ 787 Ω
With AD8332 LNA
RS = 50 Ω, RFB = ∞
RS = 50 Ω, RFB = 1.1 kΩ
RS = 50 Ω, RFB = 274 Ω
Pin 4LOP and Pin 4LON
Pin RFxP and Pin RFxN
Pin 4LOP and Pin 4LON (each pin)
For maximum differential swing; Pin RFxP and Pin RFxN
(dc-coupled to AD8332 LNA output)
Pin IxPO and Pin QxPO
One channel is reference; the other channel is stepped
16 phase steps per channel
I1xO to Q1xO and I2xO to Q2xO, 1σ
I1xO to Q1xO and I2xO to Q2xO, 1σ
Phase match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C
Amplitude match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C
Typ
0
±5
Max
Unit
200
200
50
50
13
±6
+85
MHz
MHz
MHz
MHz
dBm
V
°C
6.7||6.5
0.6
2.17
kΩ||pF
pF
mS
159
2.8
±4.7
±6.6
14.5
1.5
dB/Hz
V p-p
mA
mA
dBm
dBV
−75
−77
30
<−97
dBc
dBc
dBm
dBm
−60
dBm
4.7
10
22
dB
nV/√Hz
pA/√Hz
7.8
9.0
11.0
−3
−70
dB
dB
dB
μA
μA
V
V
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Input P1dB
Third-Order Intermodulation (IM3)
Equal Input Levels
Unequal Input Levels
Third-Order Input Intercept (IP3)
LO Leakage
Conversion Gain
Input-Referred Noise
Output Current Noise
Noise Figure
Bias Current
LO Common-Mode Voltage Range
RF Common-Mode Voltage
Output Compliance Range
PHASE ROTATION PERFORMANCE
Phase Increment
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel-to-Channel Matching
Rev. C | Page 3 of 32
0.2
3.8
2.5
−1.5
−2
+0.7
22.5
±0.1
±0.05
±1
±0.25
+2
V
Degrees
Degrees
dB
Degrees
dB
AD8333
Parameter
LOGIC INTERFACES
Logic Level High
Logic Level Low
Bias Current
Pin PHxx and Pin ENBL
Pin RSET
Input Resistance
Reset Hold Time
Minimum Reset Pulse Width
Reset Response Time
Phase Shifting Response Time
Enable Response Time
POWER SUPPLY
Supply Voltage
Quiescent Current, All Phase Bits = 0
Over Temperature
Conditions
Min
Pin PHxx, Pin RSET, and Pin ENBL
Pin PHxx, Pin RSET, and Pin ENBL
1.7
0
Logic high
Logic low
Logic high
Logic low
Pin PHxx and Pin ENBL
Pin RSET
Reset is asynchronous; clock disabled when RSET goes high
until 300 ns after RSET goes low; see Figure 58
10
−30
50
−70
Typ
40
−7
120
−20
60
20
Max
Unit
5
1.3
V
V
90
+10
180
0
μA
μA
μA
μA
kΩ
kΩ
ns
300
300
See Figure 35
See Figure 38
See Figure 34
Pin VPOS and Pin VNEG
At 25°C
Pin VPOS
Pin VNEG
−40°C < TA < 85°C
Pin VPOS, all phase bits = 0
Pin VNEG
Per channel, all phase bits = 0
Per channel, any 0 or 1 combination of phase bits
All channels disabled
Pin VPOS
Pin VNEG
ns
ns
μs
ns
300
5
300
±4.5
±5
±6
V
38
−24
44
−20
51
−16
mA
mA
54
−19
mA
mA
mW
mW
1.5
−100
mA
μA
40
−24
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Quiescent Power
Disable Current
170
190
1.0
−300
1.25
−200
PSRR
Pin VPOS to I/Q outputs (measured at AD8021 output)
Pin VNEG to I/Q outputs (measured at AD8021 output)
Rev. C | Page 4 of 32
−81
−75
dB
dB
AD8333
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Voltages
Supply Voltage, VS
RF Pins Input
LO Inputs
Code Select Inputs Voltage
Thermal Data1
θJA
θJB
θJC
ΨJT
ΨJB
Maximum Junction Temperature
Maximum Power Dissipation
(Exposed Pad Soldered to PC Board)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
6V
VS, GND
VS, GND
VS, GND
41.0°C/W
23.6°C/W
4.4°C/W
0.4°C/W
22.4°C/W
150°C
1.5 W
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
300°C
4-layer JEDEC board no airflow (exposed pad soldered to PCB).
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Rev. C | Page 5 of 32
AD8333
25
27
28
29
30
26
24 I1PO
1
PIN 1
INDICATOR
2
3
23 Q1PO
22 Q1NO
AD8333
4
21 VNEG
TOP VIEW
(Not to Scale)
5
6
20 COMM
19 Q2NO
16
15
14
13
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PADDLE BE SOLDERED
TO THE GROUND PLANE.
05543-002
PH21
PH20
VPOS
RF2P
RF2N
VPOS
RSET
I2NO
11
17 I2PO
12
18 Q2PO
8
9
7
10
PH12
PH13
COMM
4LOP
4LON
LODC
PH23
PH22
31
32
PH11
PH10
VPOS
RF1P
RF1N
VPOS
ENBL
I1NO
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. 32-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2,
7, 8
Mnemonic
PH12, PH13,
PH23, PH22
3, 20
4, 5
COMM
4LOP, 4LON
6
9, 10,
31, 32
11, 14,
27, 30
LODC
PH21, PH20,
PH10, PH11
VPOS
12, 13,
28, 29
RF2P, RF2N,
RF1N, RF1P
15
RSET
16, 19,
22, 25
I2NO, Q2NO,
Q1NO, I1NO
17, 18,
23, 24
I2PO, Q2PO,
Q1PO, I1PO
21
VNEG
26
ENBL
Description
Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0° to 90°, 90° to 180°,
180° to 270°, 270° to 360° (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by
3 V CMOS logic (see Figure 3).
Ground. These two pins are internally tied together.
LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum
performance, these inputs should be driven differentially with a signal level that is not less than what is
shown in Figure 22. Bias current is only −3 μA. Single-ended drive is also possible if the inputs are biased
correctly (see Figure 4).
Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground (see Figure 5).
Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0°, 22.5°, 45°, 67.5°
(see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3).
Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set
of supply decoupling components for all four pins should be sufficient.
RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to
the output pins of the AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input
differential swing is 2.5 V if ±5 V supplies are used (see Figure 6).
Reset for Divide-by-4 in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by
3 V CMOS logic (see Figure 3).
Negative I/Q Outputs. These outputs are not connected for normal usage but can be used for filtering if needed.
Together with the positive I/Q outputs, they allow bypassing of the internal current mirror if a lower noise output
circuit is available; VNEG needs to be tied to GND to disable the current mirror (see Figure 7).
Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via
a transimpedance amplifier. Multiple outputs can be summed together by connecting them together. The bias
voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 7).
Negative Supply. This pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the pin and ground.
Chip Enable. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3).
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Rev. C | Page 6 of 32
AD8333
EQUIVALENT INPUT CIRCUITS
VPOS
VPOS
RFxP
LOGIC
INTERFACE
05543-003
COMM
RFxN
05543-006
PHxx
ENBL
RSET
COMM
Figure 6. RF Inputs
Figure 3. Logic Inputs
COMM
VPOS
IxNO
QxNO
IxPO
QxPO
4LOP
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COMM
VNEG
Figure 4. Local Oscillator Inputs
Figure 7. Output Drivers
VPOS
COMM
05543-005
LODC
Figure 5. Local Oscillator Decoupling Pin
Rev. C | Page 7 of 32
05543-007
05543-004
4LON
AD8333
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5 V, TA = 25°C, f4LO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm (50 Ω); single-ended sine wave;
per channel performance, differential voltages, dBm (50 Ω), phase select code = 0000, unless otherwise noted (see Figure 41).
2
f = 1MHz
1.0
f = 5MHz
CODE 0100
CODE 0011
Q
I
1
CODE 0010
PHASE ERROR (Degrees)
CODE 0001
0.5
CODE 1000
CODE 0000
0
–0.5
0
–1
–2
2
f = 1MHz
1
0
–1.0
05543-008
CODE 1100
–1.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–1
–2
0000
2.0
05543-011
IMAGINARY PHASE (Normalized)
1.5
0010
REAL PHASE (Normalized)
0100
0110
1000
1010
1100
1111
1110
CODE (Binary)
Figure 8. Normalized Vector Plot of Phase, Channel 2 with Respect to
Channel 1; Channel 1 Is Fixed at 0°, Channel 2 Stepped 22.5°/Step,
All Codes Displayed
Figure 11. Phase Error of Channel 2 with Respect to Channel 1 vs.
Code at 1 MHz and 5 MHz
360
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270
PHASE (Degrees)
500mV
1MHz
5MHz
315
225
180
135
0
0000
20µs
05543-009
45
0010
0100
0110
1000
1010
1100
1110
05543-012
90
1111
CODE (Binary)
Figure 9. Phase of Channel 2 with Respect to Channel 1 vs. Code
at 1 MHz and 5 MHz
Figure 12. I or Q Output of Channel 2 with Respect to Channel 1,
First Quadrant Shown
7
1.0
CHANNEL 1, I OUTPUT SHOWN
f = 5MHz
0.5
6
CODE 0000
CODE 0001
CODE 0010
CODE 0011
–0.5
GAIN (dB)
–1.0
1.0
f = 1MHz
5
0.5
4
0
–1.0
0000
05543-010
–0.5
0010
0100
0110
1000
1010
1100
1110
3
1M
1111
05543-013
AMPLITUDE ERROR (dB)
0
10M
50M
RF FREQUENCY (Hz)
CODE (Binary)
Figure 10. Amplitude Error of Channel 2 with Respect to Channel 1 vs. Code
at 1 MHz and 5 MHz
Rev. C | Page 8 of 32
Figure 13. Conversion Gain vs. RF Frequency, First Quadrant,
Baseband Frequency = 10 kHz
AD8333
0.5
0.4
I/Q AMPLITUDE IMBALANCE (dB)
1.5
0.5
0
–0.5
–1.0
–1.5
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–2.0
1M
10M
05543-017
1.0
05543-014
–0.4
–0.5
100
100M
1k
RF FREQUENCY (Hz)
2.0
1.5
1.5
1.0
1.0
AMPLITUDE MATCH (dB)
2.0
0.5
–1.0
fBB = 10kHz
I2/I1 DISPLAYED
CODE 0000
–40°C
+25°C
+85°C
CODE 0001
–40°C
+25°C
+85°C
0.5
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–1.5
–2.0
100
1k
10k
0
CODE 0010
–40°C
+25°C
+85°C
–0.5
–1.0
CODE 0011
–40°C
+25°C
+85°C
–1.5
05543-018
–0.5
–2.0
1M
100k
10M
BASEBAND FREQUENCY (Hz)
Figure 18. Typical I2xO/I1xO or Q2xO/Q1xO Amplitude Match vs. RF Frequency,
First Quadrant, at Three Temperatures
8
0.5
0.4
6
PHASE ERROR (Degrees)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
4
CODE 0000
–40°C
+25°C
+85°C
CODE 0010
–40°C
+25°C
+85°C
CODE 0001
–40°C
+25°C
+85°C
CODE 0011
–40°C
+25°C
+85°C
2
0
–2
fBB = 10kHz
I2/I1 DISPLAYED
05543-016
–0.4
–0.5
1M
50M
RF FREQUENCY (Hz)
Figure 15. Representative Range of Quadrature Phase Error vs. Baseband
Frequency, Channel 1 and Channel 2 (see Figure 43)
I/Q AMPLITUDE IMBALANCE (dB)
100k
Figure 17. Representative Range of I/Q Amplitude Imbalance vs.
Baseband Frequency, Channel 1 and Channel 2 (see Figure 43)
05543-015
QUADRATURE PHASE ERROR (Degrees)
Figure 14. Representative Range of Quadrature Phase Errors vs.
RF Frequency, Channel 1 or Channel 2, All Codes
0
10k
BASEBAND FREQUENCY (Hz)
10M
05543-043
QUADRATURE PHASE ERROR (Degrees)
2.0
–4
1M
50M
RF FREQUENCY (Hz)
10M
50M
RF FREQUENCY (Hz)
Figure 16. Representative Range of I/Q Amplitude Imbalance vs.
RF Frequency, Channel 1 or Channel 2, All Codes
Figure 19. I2xO/I1xO or Q2xO/Q1xO Phase Error vs. RF Frequency,
Baseband Frequency = 10 kHz, at Three Temperatures
Rev. C | Page 9 of 32
AD8333
2.8
10
CHANNEL 1, I OUTPUT SHOWN
TRANSCONDUCTANCE = [(VBB/787Ω)V RF]
GAIN = VBB/VRF
5
2.6
+85°C
+25°C
–40°C
0
CODE 0000
CODE 0001
CODE 0010
CODE 0011
–5
2.4
–10
2.3
–15
2.2
–20
2.1
–25
2.0
1M
–30
50M
10M
05543-019
GAIN (dB)
2.5
05543-020
0
RF FREQUENCY (Hz)
2.0
2.5
3.0
3.5
4.0
5.0
4.5
20
18
0
f = 5MHz
GAIN = VBB/VRF
–10
16
14
IP1dB (dBm)
–20
12
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–30
CODE 0000
CODE 0001
CODE 0010
CODE 0011
–40
–50
10
8
6
–60
4
–80
–20
05543-021
–70
–15
–10
2
0
1M
0
–5
05543-023
GAIN (dB)
1.5
Figure 23. LO Common-Mode Range at Three Temperatures
10
POWER (dBm)
10M
50M
RF FREQUENCY (Hz)
Figure 21. Conversion Gain vs. LO Level, First Quadrant
Figure 24. IP1dB vs. RF Frequency, Baseband Frequency = 10 kHz,
First Quadrant (see Figure 42)
5
0
BOTH CHANNELS
ALL CODES
–10
–5
–20
REGION OF USEABLE
LO LEVELS
IM3 (dBc)
–10
–15
–20
3
8 13 18
IM3 PRODUCTS
–40
LO = 5.023MHz
RF1 = 5.015MHz
RF2 = 5.010MHz
–50
–60
–30
–70
–35
–40
100k
1M
10M
100M
–7dBm
–30
–25
05543-022
MINIMUM LO LEVEL (dBm)
1.0
COMMON-MODE VOLTAGE (V)
Figure 20. Transconductance vs. RF Frequency, First Quadrant
0
0.5
–80
–90
1M
05543-024
TRANSCONDUCTANCE (mS)
2.7
10M
RF FREQUENCY (Hz)
RF FREQUENCY (Hz)
Figure 25. Representative Range of IM3 vs. RF Frequency,
First Quadrant (see Figure 49)
Figure 22. Minimum LO Level vs. RF Frequency, Single-Ended,
Sine Wave LO Drive to Pin 4LOP or Pin 4LON
Rev. C | Page 10 of 32
50M
AD8333
0
40
LO LEVEL = 0dBm
BOTH CHANNELS
35
–20
LO LEAKAGE (dBm)
25
20
15
10
–80
–100
RF FREQUENCY (Hz)
Figure 29. LO Leakage vs. RF Frequency at RF Inputs
35
16
30
14
12
CHANNEL 1 RF
CHANNEL 2 RF
10
NOISE (nV/ Hz)
OIP3 (dBm)
25
15
–142.9
–144.1
I1
Q1
–145.4
10
–147.0
8
–148.9
6
–151.4
4
–154.9
2
–161.0
www.BDTIC.com/ADI
05543-026
5
0
1k
0
1M
100k
10k
Figure 30. Input-Referred Noise vs. RF Frequency
Figure 27. OIP3 vs. Baseband Frequency (see Figure 48)
0
20
LO LEVEL = 0dBm
18
–10
16
–40
NOISE FIGURE (dB)
–20
–30
50M
10M
RF FREQUENCY (Hz)
BASEBAND FREQUENCY (Hz)
I1
I2
Q1
Q2
–50
14
12
10
8
6
–60
4
–70
–80
1M
05543-027
LO LEAKAGE (dBm)
50M
10M
RF FREQUENCY (Hz)
Figure 26. Representative Range of OIP3 vs. RF Frequency,
First Quadrant (see Figure 49)
20
05543-028
–140
1M
50M
NOISE (dBm)
10M
RF1P
RF2P
RF1N
RF2N
05543-029
0
1M
–60
–120
05543-025
5
–40
10M
50M
RF FREQUENCY (Hz)
05543-064
OIP3 (dBm)
30
2
0
1M
10M
RF FREQUENCY (Hz)
Figure 28. LO Leakage vs. RF Frequency at Baseband Outputs
Figure 31. Noise Figure vs. RF Frequency with AD8332 LNA
Rev. C | Page 11 of 32
50M
AD8333
172
170
DYNAMIC RANGE (dB)
168
I1
Q1
I1 + I2
Q1 + Q2
2V
166
164
162
160
158
500mV
05543-030
154
152
1M
200ns
05543-046
156
50M
10M
RF FREQUENCY (Hz)
Figure 35. Reset Response—Top: Signal at RSET Pin,
Bottom: Output Signal (see Figure 45)
Figure 32. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level,
Single Channel and Two Channels Summed
6
5V
4
GAIN = VBB/VRF
2
CODE 0000
CODE 0010
www.BDTIC.com/ADI
–2
–4
–10
–3.0
1V
05543-044
–8
–2.5
–2.0
–1.5
–1.0
–0.5
0
1V
40µs
05543-047
–6
1.0
0.5
VOLTAGE (V)
Figure 33. Output Compliance Range (IxPO, QxPO) (see Figure 50)
Figure 36. Phase Switching Response—Channel 2 Leads Channel 1 by 45°,
Top: Input to PH21, Select Code = 0010;
Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase
Shifted 45°, Channel 1 Reference Phase Select Code = 0000
2V
200ns
Figure 34. Enable Response—Top: Enable Signal,
Bottom: Output Signal (see Figure 44)
1V
1V
40µs
05543-048
5V
500mV
05543-045
GAIN (dB)
0
Figure 37. Phase Shifting Response—Channel 2 Leads Channel 1 by 90°,
Top: Input to PH21, Select Code = 0100;
Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase
Shifted 90°, Channel 1 Reference Phase Code = 0000
Rev. C | Page 12 of 32
AD8333
60
40µs
50
VPOS
40
30
20
VNEG
10
0
–50
05543-051
1V
05543-049
1V
QUIESCENT SUPPLY CURRENT (mA)
5V
–30
–10
10
30
50
70
TEMPERATURE (°C)
Figure 38. Phase Shifting Response—Channel 2 Leads Channel 1 by 180°,
Top: Input to PH23 Select Code = 1000;
Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase
Shifted 180°, Channel 1 Reference Phase Code = 0000
Figure 40. Quiescent Supply Current vs. Temperature
0
–10
–20
–40
–50
–60
www.BDTIC.com/ADI
–70
VNEG
VPOS
–80
–90
100k
05543-050
PSRR (dB)
–30
1M
10M
50M
FREQUENCY (Hz)
Figure 39. PSRR vs. Frequency (see Figure 51)
Rev. C | Page 13 of 32
90
AD8333
TEST CIRCUITS
AD8021
120nH
0.1µF
FB
787Ω
AD8332
LNA
20Ω
LPF
RFxP
2.2nF
IxxO
AD8333
50Ω
0.1µF
20Ω
RFxN
2.2nF
4LOP
SIGNAL
GENERATOR
OSCILLOSCOPE
QxxO
787Ω
50Ω
05543-032
AD8021
SIGNAL
GENERATOR
Figure 41. Default Test Circuit
AD8021
120nH
0.1µF
FB
100Ω
AD8332
LNA
20Ω
LPF
RFxP
10nF
IxxO
AD8333
50Ω
0.1µF
20Ω
RFxN
10nF
4LOP
SIGNAL
GENERATOR
OSCILLOSCOPE
QxxO
www.BDTIC.com/ADI
100Ω
50Ω
05543-033
AD8021
SIGNAL
GENERATOR
Figure 42. P1dB Test Circuit
AD8021
AD8332
LNA
20Ω
LPF
50Ω
RFxP
IxxO
AD8333
1µF
20Ω
RFxN
SIGNAL
GENERATOR
QxxO
787Ω
787Ω
OSCILLOSCOPE
4LOP
50Ω
AD8021
SIGNAL
GENERATOR
Figure 43. Phase and Amplitude vs. Baseband Frequency
Rev. C | Page 14 of 32
05543-034
120nH
1µF
FB
AD8333
AD8021
AD8332
LNA
20Ω
RFxP
LPF
787Ω
IxxO
AD8333
50Ω
1µF
RFxN
20Ω
ENBL
SIGNAL
GENERATOR
4LOP
AD8021
50Ω
50Ω
OSCILLOSCOPE
787Ω
QxxO
SIGNAL
GENERATOR
SIGNAL
GENERATOR
05543-035
120nH
1µF
FB
Figure 44. Enable Response
AD8021
AD8332
LNA
20Ω
RFxP
LPF
787Ω
IxxO
AD8333
50Ω
1µF
RFxN
20Ω
RST
SIGNAL
GENERATOR
50Ω
OSCILLOSCOPE
787Ω
QxxO
4LOP
AD8021
50Ω
SIGNAL
GENERATOR
SIGNAL
GENERATOR
05543-036
120nH
1µF
FB
www.BDTIC.com/ADI
Figure 45. Reset Response
120nH
FB 0.1µF
AD8332
LNA
20Ω
LPF
RFxP
IxxO
AD8333
50Ω
0.1µF
20Ω
RFxN
QxxO
4LOP
SIGNAL
GENERATOR
OSCILLOSCOPE
50Ω 50Ω
50Ω
05543-037
SIGNAL
GENERATOR
Figure 46. RF Input Range
AD8021
6.98kΩ
RFxP
IxxO
AD8333
RFxN
270pF
SPECTRUM
ANALYZER
QxxO
4LOP
6.98kΩ
50Ω
SIGNAL
GENERATOR
AD8021
Figure 47. Noise Test Circuit
Rev. C | Page 15 of 32
05543-052
0.1µF
270pF
AD8333
AD8021
COMBINER
AD8332
–6dB
120nH
LNA
20Ω
0.1µF
FB
50Ω
787Ω
100pF
RFxP
SIGNAL
GENERATOR
IxxO
AD8333
0.1µF
50Ω
RFxN
20Ω
SPECTRUM
ANALYZER
100pF
QxxO
4LOP
787Ω
SIGNAL
GENERATOR
50Ω
05543-053
AD8021
SIGNAL
GENERATOR
Figure 48. OIP3 vs. Baseband Frequency
AD8021
COMBINER
AD8332
–6dB
120nH
LNA
20Ω
0.1µF
FB
50Ω
787Ω
2.2nF
RFxP
SIGNAL
GENERATOR
IxxO
AD8333
0.1µF
50Ω
RFxN
20Ω
SPECTRUM
ANALYZER
2.2nF
QxxO
4LOP
787Ω
SIGNAL
GENERATOR
50Ω
www.BDTIC.com/ADI
05543-054
AD8021
SIGNAL
GENERATOR
Figure 49. OIP3 and IM3 vs. RF Frequency
AD8021
120nH
0.1µF
FB
787Ω
AD8332
LNA
20Ω
RFxP
LPF
2.2nF
IxxO
AD8333
50Ω
0.1µF
RFxN
20Ω
2.2nF
4LOP
SIGNAL
GENERATOR
OSCILLOSCOPE
QxxO
787Ω
50Ω
05543-055
AD8021
SIGNAL
GENERATOR
Figure 50. Output Compliance Range
AD8332
LNA
20Ω
LPF
50Ω
SIGNAL
GENERATOR
RFxP
IxxO
AD8333
0.1µF
20Ω
RFxN
NETWORK
ANALYZER
QxxO
4LOP
50Ω
SIGNAL
GENERATOR
Figure 51. PSRR Test Circuit
Rev. C | Page 16 of 32
05543-056
120nH
0.1µF
FB
AD8333
THEORY OF OPERATION
The AD8333 is a dual I/Q demodulator with a programmable
phase shifter for each channel. The primary applications are
phased array beamforming in medical ultrasound, phased array
radar, and smart antennae for mobile communications. The
AD8333 can also be used in applications that require two wellmatched I/Q demodulators.
PH10
VPOS
RF1P
RF1N
VPOS
ENBL
I1NO
29
28
27
26
25
BIAS
CHANNEL 1
Φ SEL
LOGIC
AD8333
Φ
The minimum LO level is frequency dependent (see Figure 22).
For optimum noise performance, it is important to ensure that
the LO source has very low phase noise (jitter) and adequate input
level to ensure stable mixer-core switching. The gain through the
divider determines the LO signal level vs. RF frequency. The
AD8333 can be operated to very low frequencies at the LO inputs
if a square wave is used to drive the LO.
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. A
reset pin (RSET) is provided to synchronize the 4LOx divider
circuits when AD8333s are used in arrays. The RSET pin resets
the counters to a known state after power is applied to multiple
AD8333s. A logic input must be provided to the RSET pin when
using more than one AD8333. See the Reset Input section for
more details.
I/Q DEMODULATOR AND PHASE SHIFTER
www.BDTIC.com/ADI
÷4
21 VNEG
90°
20 COMM
Φ
19 Q2NO
0°
Φ
18 Q2PO
CHANNEL 2
Φ SEL
LOGIC
10
11
12
13
14
15
16
05543-057
PH21
9
17 I2PO
I2NO
PH22 8
22 Q1NO
90°
RSET
PH23 7
23 Q1PO
VPOS
LODC 6
0°
Φ
BUF
4LON 5
24 I1PO
RF2N
4LOP 4
30
RF2P
COMM 3
31
VPOS
PH13 2
32
PH20
PH12 1
PH11
Figure 52 shows the block diagram and pinout of the AD8333.
Three analog and nine quasilogic level inputs are required. Two
RF inputs accept signals from the RF sources and a local oscillator
(applied to the differential input pins marked 4LOx) common
to both channels constitute the analog inputs. Four logic inputs
per channel define one of 16 delay states/360° (or 22.5°/step),
selectable with PHx0 to PHx3. The reset input is used to
synchronize AD8333s used in arrays.
For optimum performance, the 4LOx inputs are driven differentially but can also be driven in a single-ended fashion. A good
choice for a drive is an LVDS device. The common-mode range
on each pin is approximately 0.2 V to 3.8 V with nominal ±5 V
supplies.
Figure 52. Block Diagram and Pinout
Each of the current formatted I and Q outputs sum together for
beamforming applications. Multiple channels are summed and
converted to a voltage using a transimpedance amplifier. If
desired, channels can also be used individually.
QUADRATURE GENERATION
The internal 0° and 90° LO phases are digitally generated by a
divide-by-4 logic circuit. The divider is dc-coupled and inherently
broadband; the maximum LO frequency is limited only by its
switching speed. The duty cycle of the quadrature LO signals
is intrinsically 50% and is unaffected by the asymmetry of the
externally connected 4LOx inputs. Furthermore, the divider is
implemented such that the 4LOx signals reclock the final flipflops that generate the internal LO signals and thereby minimizes
noise introduced by the divide circuitry.
The I/Q demodulators consist of double-balanced Gilbert cell
mixers. The RF input signals are converted into currents by
transconductance stages that have a maximum differential input
signal capability of 2.8 V p-p. These currents are then presented
to the mixers, which convert them to baseband: RF − LO and
RF + LO. The signals are phase shifted according to the code
applied to Pin PHx0 to Pin PHx3 (see Table 4). The phase shift
function is an integral part of the overall circuit (patent pending).
The phase shift listed in Column 1 of Table 4 is defined as being
between the baseband I or Q channel outputs. As an example,
for a common signal applied to the RF inputs of an AD8333, the
baseband outputs are in phase for matching phase codes.
However, if the phase code for Channel 1 is 0000 and that of
Channel 2 is 0001, Channel 2 leads Channel 1 by 22.5°.
Following the phase shift circuitry, the differential current
signal is converted from differential to single ended via a
current mirror. An external transimpedance amplifier is
needed to convert the I and Q outputs to voltages.
Rev. C | Page 17 of 32
AD8333
Judicious selection of the RF amplifier ensures the least
degradation in dynamic range. The input-referred spectral
voltage noise density (en) of the AD8333 is nominally 9 nV/√Hz
to 10 nV/√Hz. For the noise of the AD8333 to degrade the
system noise figure (NF) by 1 dB, the combined noise of the
source and the LNA should be about twice that of the AD8333,
or 18 nV/√Hz. If the noise of the circuitry before the AD8333 is
<18 nV/√Hz, the system NF degrades more than 1 dB. For
example, if the noise contribution of the LNA and source is
equal to the AD8333, or 9 nV/√Hz, the degradation is 3 dB. If
the circuit noise preceding the AD8333 is 1.3× as large as that of
the AD8333 (or about 11.7 nV/√Hz), the degradation is 2 dB.
For a circuit noise of 1.45× that of the AD8333 (13.1 nV/√Hz),
the degradation is 1.5 dB.
Table 4. Phase Nibble Select Codes
φ Shift
0°
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
180°
202.5°
225°
247.5°
270°
292.5°
315°
337.5°
PHx3
PHx2
PHx1
PHx0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
To determine the input-referred noise, it is important to know
the active low-pass filter (LPF) values RFILT and CFILT, shown in
Figure 53. Typical filter values (for example, those used on the
evaluation board) are 787 Ω and 2.2 nF and implement a 90 kHz
single-pole LPF. If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel
mixing gain from the RF input to the AD8021 output (for example,
ΣI, ΣQ) is approximately 1.7 × 4.7 dB. This together with the
9 nV/√Hz AD8333 noise results in about 15.3 nV/√Hz at the
AD8021 output. Because the AD8021, including the 787 Ω
feedback resistor, contributes another 4.4 nV/√Hz, the total
output-referred noise is about 16 nV/√Hz. This value can be
adjusted by increasing the filter resistor while maintaining the
corner frequency, thereby increasing the gain. The factor limiting
the magnitude of the gain is the output swing and drive capability
of the op amp selected for the I-to-V converter, in this instance
the AD8021.
DYNAMIC RANGE AND NOISE
Figure 53 is an interconnection block diagram of the AD8333.
For optimum system noise performance, the RF input signal
is provided by a very low noise amplifier, such as the LNA of
an AD8332 or the preamplifier of an AD8335. In beamformer
applications, the I and Q outputs of a number of receiver channels
are summed (for example, the two channels illustrated in Figure
53). The dynamic range of the system increases by the factor 10
log10(N), where N is the number of channels (assuming random
uncorrelated noise). The noise in the two-channel example of
Figure 53 is increased by 3 dB while the signal doubles (6 dB),
yielding an aggregate SNR improvement of
(6 dB − 3 dB) = 3 dB.
www.BDTIC.com/ADI
RFB
TRANSMITTER
T/R
SW
AD8332 LNA OR
AD8335 PREAMP
TRANSDUCER
CHANNEL 1
PHASE
SELECT
CH1
RF
AD8333
0°
2
4
2
CFILT
2
I1
2
Q1
AD8021
2
Q2
CFILT
Φ
*
2
90°
CLOCK
GENERATOR
Φ
÷4
2
90°
Φ
*
2
0°
Φ
2
CH2
RF
TRANSMITTER
AD8332 LNA OR
AD8335 PREAMP
T/R
SW
I2
RFILT
AD8021
ΣI
ADC 16-BIT I DATA
570kSPS
AD7665 OR
AD7686
ΣQ
ADC 16-BIT
570kSPS Q DATA
4
CHANNEL 2
PHASE
SELECT
*UP TO EIGHT CHANNELS
PER AD8021
RFB
05543-038
TRANSDUCER
2
RFILT
Figure 53. Interconnection Block Diagram
Rev. C | Page 18 of 32
AD8333
Beamforming, as applied to medical ultrasound, is defined as
the phase alignment and summation of signals generated from a
common source but received at different times by a multielement
ultrasound transducer. Beamforming has two functions: it imparts
directivity to the transducer, enhancing its gain, and it defines
a focal point within the body from which the location of the
returning echo is derived. The primary application for the
AD8333 is in analog beamforming circuits for ultrasound.
PHASE COMPENSATION AND ANALOG
BEAMFORMING
Modern ultrasound machines used for medical applications
employ a 2n binary array of receivers for beamforming, with
typical array sizes of 16 or 32 receiver channels phase-shifted
and summed together to extract coherent information. When
used in multiples, the desired signals from each of the channels
can be summed to yield a larger signal (increased by a factor N,
where N is the number of channels), while the noise is increased
by the square root of the number of channels. This technique
enhances the signal-to-noise performance of the machine. The
critical elements in a beamformer design are the means to align
the incoming signals in the time domain and the means to sum
the individual signals into a composite whole.
Alternatively, the RF signal can be processed by downconversion
on each channel individually, phase shifting the downconverted
signal and then combining all channels. The AD8333 provides
the means to implement this architecture. The downconversion
is done by an I/Q demodulator on each channel, and the summed
current output is the same as in the delay line approach. The
subsequent filters after the I-to-V conversion and the ADCs
are similar.
The AD8333 integrates the phase shifter, frequency conversion,
and I/Q demodulation into a single package and directly yields
the baseband signal. To illustrate this, Figure 54 is a simplified
diagram showing two channels. The ultrasound wave (USW)
is received by two transducer elements, TE1 and TE2, in an
ultrasound probe and generates the E1 and E2 signals. In this
example, the phase at TE1 leads the phase at TE2 by 45°.
TRANSDUCER
ELEMENTS TE1
AND TE2
CONVERT USW TO
ELECTRICAL
AD8332
USW AT TE1
SIGNALS
LEADS USW
ES1 LEADS
AT TE2 BY
ES2 BY 45°
19dB
45°
45°
LNA
AD8333
PHASE BIT
SETTINGS
CH 1 REF
(NO PHASE
LEAD)
E1
E2
S1 AND S2
ARE NOW IN
PHASE
S1
19dB
LNA
CH 2
PHASE
LEAD 45°
S2
Figure 54. Simplified Example of the AD8333 Phase Shifter
www.BDTIC.com/ADI
In traditional analog beamformers incorporating Doppler, a
V-to-I converter per channel and a crosspoint switch precede
passive delay lines used as a combined phase shifter and
summing circuit. The system operates at the receive frequency
(RF) through the delay line, and then the signal is downconverted by a very large dynamic range I/Q demodulator.
The resultant I and Q signals are filtered and sampled by two
high resolution ADCs. The sampled signals are processed to
extract the relevant Doppler information.
SUMMED
OUTPUT
S1 + S2
05543-063
SUMMATION OF MULTIPLE CHANNELS
(ANALOG BEAMFORMING)
In a real application, the phase difference depends on the
element spacing, λ (wavelength), speed of sound, angle of
incidence, and other factors. The ES1 and ES2 signals are
amplified 19 dB by the low noise amplifiers in the AD8332.
For optimum signal-to-noise performance, the output of the
LNA is applied directly to the input of the AD8333. To sum the
ES1 and ES2 signals, ES2 is shifted 45° relative to ES1 by setting
the phase code in Channel 2 to 0010. The phase-aligned current
signals at the output of the AD8333 are summed in an I-to-V converter to provide the combined output signal with a theoretical
improvement in dynamic range of 3 dB for the sum of two channels.
Rev. C | Page 19 of 32
AD8333
summing amplifiers and low-pass filters, the very small CW signal
can be ignored. The number of channels that can be summed is
limited by the output drive current capacity of the op amp selected:
60 mA to 70 mA for a linear output current for ±5 V and ±12 V,
respectively, for the AD8021. Because the AD8021 implements
an active LPF together with R1x and C1x, it must absorb the
worst-case current provided by the AD8333, for example, 6.6 mA.
Therefore, the maximum number of channels that the AD8021
can sum is 10 for ±12 V or eight for ±5 V supplies. In practical
applications, CW channels are used in powers of two, thus the
maximum number per AD8021 is eight.
CHANNEL SUMMING
In a beamformer using the AD8333, the bipolar currents at
the I and Q outputs are summed directly. Figure 55 illustrates
16 summed channels (for clarity, these channels are shown as
current sources) as an example of an active current summing
circuit using the AD8333. This figure also illustrates AD8021s
as first-order current summing circuits and AD797s as low
noise second-order summing circuits. Beginning with the op
amps, there are a few important considerations in the circuit
shown in Figure 55.
The op amps selected for the first-order summing amplifiers
must have good frequency response over the full operating
frequency range of the AD8333s and be able to source the
current required at the AD8333 I and Q outputs.
Another consideration for the op amp selected as an I-to-V
converter is the compliance voltage of the AD8333 I and Q
outputs. The maximum compliance voltage is 0.5 V, and a dc
bias must be provided at these pins. The AD8021 active LPF
satisfies these requirements; it keeps the outputs at 0 V via the
virtual ground at the op amp inverting input while providing
any needed dc bias current.
The total current of each AD8333 is 6.6 mA for the multiples of
the 45° phase settings (Code 0010, Code 0110, Code 1010, and
Code 1110) and is divided nearly equally between the baseband
frequencies (including a dc component) and the second harmonic
of the local oscillator frequency. The desired CW signal tends to be
much less (<40 dB) than the unwanted interfering signals. When
determining the large signal requirements of the first-order
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FIRST-ORDER
SUMMING AMPLIFIERS
C1A
18nF
EIGHT AD8333 I OR Q OUTPUTS,
6.6mA PEAK EACH
(IF THE PHASE SETTING IS 45°)
3.3mA AT DC + 3.3mA AT 2 × LO
R1A
100Ω
LPF1A
88kHz
+2.8V BASEBAND
SIGNAL
+5V
2
–
0.1µF
ΣA
3
+
AD8021
HPF1A
100Hz
C2A R2A
1µF 698Ω
–5V
LPF2A
81kHz
R3A
698Ω
C3A
5.6nF
SECOND-ORDER
SUMMING AMPLIFIER
0.1µF
R4
+10V
2
C1B
18nF
3
R1B
100Ω
–
0.1µF
ΣB
3
+
AD8021
+
–10V
+5V
2
AD797
C2B R2B
1µF 698Ω
–5V
0.1µF
Figure 55. A 16-Channel Beamformer
Rev. C | Page 20 of 32
0.1µF
R3B
698Ω
C3B
5.6nF
05543-058
(SAME AS ABOVE)
–
0.1µF
AD8333
As previously noted, a typical CW signal has a large dc and
very low frequency component compared with its desired low
CW Doppler baseband frequency, and another unwanted
component at the 2 × LO. The dc component flows through the
gain resistors R1x, and the 2 × LO flows through the capacitors
C1x. The smaller desired CW Doppler baseband signal is in the
frequency range of 1 kHz to 50 kHz.
Because the output current of the AD8333 contains the baseband
frequency, a dc component, and the 2 × LO frequency voltages,
the desired small amplitude baseband signal must be extracted
after a series of filters. These are shown in Figure 55 as LPFnA,
HPFnA, and gain stages.
Before establishing the value of CLPF1, the resistor RLPF1 is
selected based on the peak operating current and the linear
range of the op amp. Because the peak current for each AD8333
is 6.6 mA and there are eight channels to be summed, the total
peak current required is 52.8 mA. Approximately half of this
current is dc, and the other half is at a frequency of 2 × LO.
Therefore, about 26.4 mA flows through the resistor, and the
remaining 26.4 mA flows through the capacitor. R1 was selected
as 100 Ω and, after filtering, generates a peak dc and very low
frequency voltage of 2.64 V at the AD8021 output. For power
supplies of ±5 V, 100 Ω is a good choice for R1.
The filter LPF1A establishes the upper frequency limit of the
baseband frequency and is selected well below the 2 × LO
frequency, typically 100 kHz or less (for example, 88 kHz in
Figure 55).
A useful equation for calculating C1 is
C1 =
1
2πR1f LPF1
(1)
As previously mentioned, the AD8333 output current contains a
dc current component. This dc component is converted to a
large dc voltage by the AD8021 LPF. Capacitor C2 filters this dc
component and, with R2 + R3, establishes a high-pass filter with
a low frequency cutoff of about 100 Hz. Capacitor C3 is much
smaller than C2 and, consequently, can be neglected. C2 can be
calculated by
C2 =
1
2π(R2 + R3) f HPF1
(2)
To achieve maximum attenuation of the 2 × LO frequency, a
second low-pass filter, LPF2, is established using the parallel
combination of R2 and R3, and C3. Its −3 dB frequency is
f LPF 2 =
1
2π(R2 || R3)C 3
(3)
In the example shown in Figure 55, fLPF2 = 81 kHz.
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However, because the CW signal needs to be amplified as
much as possible and the noise degradation of the signal path
minimized, the value of R1 should be as large as possible. A
larger supply helps in this regard, and the only factor limiting
the largest supply voltage is the required power.
For a ±10 V supply on the AD8021, R1 can be increased to
301 Ω to realize the same headroom as with a ±5 V supply. If a
higher value of R1 is used, C1 must be adjusted accordingly (in
this example, 1/3 the value of the original value) to maintain the
desired LPF roll-off. The principal advantage of a higher supply
is greater dynamic range, and the trade-off is power consumption.
The user must weigh the trade-offs associated with the supply
voltage, R1, C1, and the following circuitry. A suggested design
sequence is as follows:
1.
2.
3.
4.
Select a low noise, high speed op amp. The spectral density
noise (en) should be <2 nV/√Hz, and the 3 dB bandwidth
should be ≥3× the expected maximum 2 × LO frequency.
Divide the maximum linear output current by 6.6 mA to
determine the maximum number of AD8333 channels that
can be summed.
Select the largest value of R1 that permits the output
voltage swing within the power supply rails.
Calculate the value of C1 to implement the LPF corner that
allows the CW Doppler signal to pass with maximum
attenuation of the 2 × LO signal.
Finally, the feedback resistor of the AD797 must be calculated.
This is a function of the input current (number of channels)
and the supply voltage.
The second-order summing amplifier requires a very low noise
op amp, such as the AD797, with 0.9 nV/√Hz, because the
amplifier gain is determined by Feedback Resistor R4 divided
by the parallel combination of the LPF2A resistors seen looking
back toward the AD8021s. Referring to Figure 55, the AD797
in-band (100 Hz to 88 kHz) gain is expressed as
R4
[(R2A + R3A) || (R2B + R2B)]
(4)
The AD797 noise gain can increase to unacceptable levels
because the denominator of the gain equation is the parallel
resistance of all the R2 + R3 resistors in the AD8021 outputs.
For example, for a 64-channel beamformer, the resistance seen
looking back toward the AD8021s is about 1.4 kΩ/8 = 175 Ω.
For this reason, the value of (R2x + R3x) should be as large as
possible to minimize the noise gain of the AD797. (Note that
this is the case for the AD8021 stages because they look back
into the high impedance current sources of the AD8333s.)
Due to these considerations, it is advantageous to increase the
gain of the AD8021s as much as possible because the value of
(R2x + R3x) can be increased proportionally. Resistors (R2x +
R3x) convert the CW voltages to currents that are summed at
the inverting inputs of the AD797 op amp, and then amplified
and converted to voltages by R4.
Rev. C | Page 21 of 32
AD8333
The value of R4 needs to be chosen iteratively as follows:
2.
3.
4.
5.
6.
7.
Determine the number of AD8021 first-order summing
amplifiers. In Figure 55, there are two; for a 32-channel
beamformer, there would be four, and for a 64-channel
beamformer, there would be eight.
Determine the output noise from the AD8021s. A firstorder calculation can be based on a value of AD8333
output current noise of about 20 pA/√Hz. For the values in
Figure 55, this results in about 6 nV/√Hz for eight channels
after the AD8021s. Adding the noise of the AD8021 and
the 100 Ω feedback resistor results in about 6.5 nV/√Hz
total noise after the AD8021 LPF in the CW Doppler band.
Determine the noise of the circuitry after the AD797 and
determine the desired signal level.
Determine the voltage and current noise of the secondorder summing amplifiers.
Choose a value for (R2x + R3x) and for R4. Determine the
resulting output noise after the AD797 for one channel, and
then multiply this value by the square root of the number
of summed AD8021s. Next, check AD797 output noise
(both current and voltage noise). Ideally, the sum of the
noise of the resistors and the AD797 should be less than a
factor-of-3 than the noise due to the AD8021 outputs.
Check the following stages output noise against the
calculated noise from the combiner circuit and AD8333s.
Ideally, the noise from the following stage should be less
than 1/3 of the calculated noise.
If the combined noise is too large, experiment with
increasing/decreasing values for (R2x + R3x) and R4.
DISABLING THE CURRENT MIRROR AND
DECREASING NOISE
The noise contribution of the AD8333 can potentially be reduced
if the current mirrors that convert the internal differential signals to
single-ended signals are bypassed (see Figure 56). Current mirrors
interface to the AD8021 I-V converters shown in Figure 53, and
output capacitors across the positive and negative outputs provide
low-pass filtering. The AD8021s force the AD8333 output voltage
to 0 V and then process the bipolar output current; however, the
internal current mirrors introduce a significant amount of noise.
This noise can be reduced if the mirrors are disabled and the
outputs are externally biased.
The mirrors are disabled by connecting VNEG to ground and
providing external bias networks, as shown in Figure 56. The
larger the drop across the resistors, the less noise they contribute to
the output; however, the voltage on the I and Q output nodes
cannot exceed 0.5 V. Voltages exceeding approximately 0.7 V
turn on the PNP devices and forward bias the ESD protection
diodes. Inductors provide an alternative to resistors, enabling
reduced static power by eliminating the power dissipation in the
bias resistors.
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COMM
To simplify, the user can also simulate or build a combiner
circuit for optimum performance. It should be noted that the
~20 pA/√Hz output from the AD8333 is for the AD8333 with
shorted RF inputs. In an actual system, the current noise output
from the AD8333 is most likely dominated by the noise from the
AD8332 LNA and the noise from the source and other circuitry
before the LNA. This helps ease the design of the combiner. The
preceding procedures for determining the optimum values for
the combiner are based on the noise floor of the AD8333 only.
As an example, for a 32-channel beamformer using four lowpass filters, as shown in Figure 55, (R2x + R3x) = 1.4 kΩ and
R4 = 6.19 kΩ. The theoretical noise increase of √N is degraded
by only about 1 dB.
DYNAMIC RANGE INFLATION
Although all 64 channels can theoretically be summed together
at a single amplifier, it is important to realize that the dynamic
range of the summed output increases by 10 log10(N) if all
channels have uncorrelated noise, where N is the number of
channels to be summed.
IxNO
QxNO
OTHER
CHANNELS
I-V
I-V
IxPO
QxPO
VNEG1
1NOTE
THAT PIN VNEG AND PIN COMM
ARE CONNECTED TOGETHER.
05543-039
1.
The summed signal level increases by a factor of N, whereas the
noise increases only as √N. In the case of 64 channels, this is an
increase in dynamic range of 18 dB. Note that the AD8333 dynamic
range is already about 160 dB/Hz; the summed dynamic range
is 178 dB/Hz (equivalent to about 29.5 bits/Hz). In a 50 kHz
noise bandwidth, this is 131 dB (21.7 bits).
Figure 56. Bypassing the Internal Current Mirrors
With inductors, the main limitation might be low frequency
operation, as is the case in CW Doppler in ultrasound where
the frequency range of interest goes from a few hundred hertz
to about 30 kHz. In addition, it is still important to provide
enough gain through the I-to-V circuitry to ensure that the bias
resistor and I-to-V converter noise do not contribute significantly
to the noise from the AD8333 outputs. Another approach is to
provide a single external current mirror that combines all
channels; it is also possible to implement a high-pass filter with
this circuit to help with offset and low frequency reduction.
Rev. C | Page 22 of 32
AD8333
The main disadvantage of the external bias approach is that two
I-V amplifiers are needed because of the differential output (see
Figure 56). For beamforming applications, the outputs are still
summed, but there is twice the number of lines. Only two bias
resistors are needed for all outputs that are connected together.
The resistors are scaled by dividing the value of a single output
bias resistor through N, the number of channels connected in
parallel. The bias current depends on the phase selected: for
phase 0°, it is about 2.5 mA per side, whereas in the case of 45°,
it is about 3.5 mA per side. The bias resistors should be chosen
based on the larger bias current value of 3.5 mA and the chosen
VNEG. VNEG should be at least −5 V and can be larger for
additional noise reduction.
Excessive noise or distortion at high signal levels degrades the
dynamic range of the signal. Transmitter leakage and echoes
from slow moving tissue generate the largest signal amplitudes
in ultrasound CW Doppler mode and are largest near dc and at
low frequencies. A high-pass filter introduced immediately
following the AD8333 reduces the dynamic range. This is
shown by the two coupling capacitors after the external bias
resistors in Figure 56. Users have to determine what is acceptable
for a particular application. Care must be taken in designing the
external circuitry to avoid introducing noise via the external
bias and low frequency reduction circuitry.
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Rev. C | Page 23 of 32
AD8333
APPLICATIONS INFORMATION
The AD8333 is the key component of a phase-shifter system
that aligns time-skewed information contained in RF signals.
Combined with a variable gain amplifier (VGA) and low noise
amplifier (LNA), the AD8333 forms a complete analog receiver
for a high performance ultrasound system. Figure 57 is a block
diagram of a complete receiver using the AD8333, AD8331,
AD8332, and AD8334.
AD8332
I1
Q1
LNA2
FROM
TRANSDUCER
T/R SWITCH
AD8333
16-BIT
ADC
4 × LO
PROCESSOR
RSET
I2
Q2
16-BIT
ADC
PROCESSOR
HS ADC
PROCESSOR
tPW-MIN
tHOLD
THE TIMING OF THE RISING
EDGE OF RSET IS NOT
CRITICAL AS LONG AS THE
tPW-MIN IS SATISFIED
05543-060
LNA1
FROM
TRANSDUCER
T/R SWITCH
The rising edge of the active high RSET pulse can occur at any
time, but the duration must be ≥300 ns minimum (tPW-MIN). When
the RSET pulse transitions from high to low, the LO dividers are
reactivated; however, there is a short delay until the divider
recovers to a valid state. To guarantee synchronous operation of
an array of AD8333s, the 4 × LO clock must be disabled when
the RSET transitions high, and then remain disabled for at least
300 ns after RSET transitions low.
HS ADC
PROCESSOR
05543-059
tHOLD = HOLD TIME
tPW-MIN = MINIMUM PULSE WIDTH
Figure 57. Block Diagram—Ultrasound Receiver Using the AD8333
and AD8332 LNA
Figure 58. Timing of the RSET Signal to 4 × LO
Synchronization of multiple AD8333s can be checked as follows:
1.
As a major element of an ultrasound system, it is important to
consider the many I/O options of the AD8333 that are necessary
to perform its intended function. Figure 61 shows the basic
connections.
2.
3.
Set the phase code of all AD8333 channels to the same
setting, for example, 0000.
Apply a test signal to a single channel that generates a sine
wave in the baseband output, and then measure the output.
Apply the same test signal to all channels simultaneously,
and then measure the output.
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LOGIC INPUTS AND INTERFACES
The logic inputs of the AD8333 are all bipolar-level sensitive
inputs. They are not edge triggered, nor are they to be confused
with classic TTL or other logic family input topologies. The
voltage threshold for these inputs is VPOS × 0.3, so for a 5 V
supply the threshold is 1.5 V, with a hysteresis of ±0.2 V.
Although the inputs are not of themselves logic inputs, any 5 V
logic family can drive them.
Because all the phase codes of the AD8333s are the same, the
combined signal should be N times bigger than the single channel.
The combined signal is less than N times one channel if any of the
LO phases of individual AD8333s are in error.
CONNECTING TO THE LNA OF THE
AD8331/AD8332/AD8334/AD8335 VGAs
+5V
RESET INPUT
The RSET pin is used to synchronize the LO dividers in
AD8333 arrays. Because they are driven by the same internal
LO, the two channels in any AD8333 are inherently synchronous.
However, when multiple AD8333s are used, it is possible that their
dividers wake up in different phase states. The function of the
RSET pin is to phase align all the LO signals in multiple AD8333s.
Figure 59. Connecting the AD8333 to the LNA of an AD8332
The 4 × LO divider of each AD8333 can initiate in one of four
possible states: 0°, 90°, 180°, or 270°. The internally generated
I/Q signals of each AD8333 LO are always at a 90° angle relative
to each other, but a phase shift can occur during power-up
between the internal LOs of the different AD8333s.
The RFxx inputs (Pin 12, Pin 13, Pin 28, and Pin 29) are
optimized for maximum dynamic range when dc-coupled to
the differential output pins of the LNA of the AD8331/AD8332/
AD8334 or the AD8335 series of VGAs and can be connected
directly, as shown in Figure 59.
RFxP
AD8332
LNA
AD8333
–5V
The RSET pin provides an asynchronous reset of the LO
dividers by forcing the internal LO to hang. This mechanism
also allows the measurement of nonmixing gain from the RF
input to the output.
Rev. C | Page 24 of 32
05543-061
RFxN
AD8333
INTERFACING TO OTHER AMPLIFIERS
LO INPUT
If amplifiers other than the AD8332 LNA are connected to the
input, attention must be paid to their bias and drive levels. For
maximum input signal swing, the optimum bias level is 2.5 V,
and the RF input must not exceed 5 V to avoid turning on the
ESD protection circuitry. If ac coupling is used, a bias circuit,
such as that illustrated in Figure 60, is recommended. An
internal bias network is provided; however, additional external
biasing can center the RF input at 2.5 V.
The LO input is a high speed, fully differential analog input
that responds to differences in the input levels, not in the logic
levels. The LO inputs can be driven with a low common-mode
voltage amplifier, such as the National Semiconductor DS90C401
LVDS driver.
Figure 22 and Figure 23 show the range of common-mode
voltages and useable LO levels when the LO input is driven with
a single-ended sine wave. Logic families, such as TTL or CMOS,
are unsuitable for direct coupling to the LO input.
+5V
5.23kΩ
1.4kΩ
AD8333
0.1µF
RFxP
RF IN
0.1µF
RFxN
3.74kΩ
05543-062
1.4kΩ
–5V
Figure 60. AC Coupling the AD8333 RF Input
To realize the full range of performance, the AD8333 must be
driven from a differential source. Using a single-ended source is
strongly discouraged because of internal supply headroom
constraints.
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VPOS
120nH FB
CHANNEL 1 –
RF IN +
+5V
CHANNEL 1
PHASE
SELECT BITS
0.1µF
5
31.6kΩ
0.1µF 6
7
8
ENBL
VPOS
RF1P
RF1N
25
I1NO
I1PO
PH13
Q1PO
COMM
Q1NO
4LOP
VNEG
AD8333
4LON
COMM
LODC
Q2NO
PH23
Q2PO
PH22
PH21
CHANNEL 2
PHASE
SELECT BITS
26
9
10
11
12
13
14
RSET
0.1µF
27
VPOS
4
–
31.6kΩ
3
28
RF2N
LOCAL
OSCILLATOR
33.2kΩ
0.1µF
29
RF2P
33.2kΩ
+
2
PH10
+5V
30
VPOS
*
PH11
PH12
PH20
1
31
VPOS
32
15
I2PO
I2NO
24
23
22
CHANNEL 1
+ I OUT
CHANNEL 1
+ Q OUT
120nH FB
21
–5V
20
0.1µF
19
18
17
CHANNEL 2
+ Q OUT
CHANNEL 2
+ I OUT
16
+
CHANNEL 2 –
RF IN
0.1µF
VPOS
*OPTIONAL BIAS NETWORK. THESE COMPONENTS CAN BE DELETED IF THE LO IS DC-COUPLED FROM
AN LVDS SOURCE BIASED AT 1.2V.
Figure 61. AD8333 Basic Connections
Rev. C | Page 25 of 32
05543-040
RESET
INPUT
AD8333
EVALUATION BOARD
The AD8333-EVALZ evaluation board provides a platform for
test and evaluation of the AD8333 I/Q demodulator and phase
shifter. The board is shipped fully assembled and tested and is
signal ready. A pair of AD8332 low-noise amplifiers (LNA)
provide input matching and amplification for the differential
input of the AD8333. A photograph of the board is shown in
Figure 62 and a schematic diagram is shown in Figure 64. The
board requires dual 5 V supplies capable of supplying 300 mA
or greater. Except for the optional components shown in
grayscale, the board is completely built and tested.
Phase Nibble
The phase nibble configures the phase delay for each channel in
sixteen 22.5° increments from 0° to 337.5°. The increments
increase proportionally in a simple binary format from 0H
(hexadecimal) to FH. Table 4 lists the phase shift and
corresponding code for each bit. The bits are labeled 0 and 1,
corresponding to low and high, respectively, on the silkscreen.
Jumpers select the desired state.
Enable and Reset Jumpers
For normal operation, place a jumper in the upper position of
ENBL. To disable the AD8333, move the jumper to the lower
position. For normal operation, the jumper for RST is in its
right position. When the jumper is in the left position, the
device counter is held in reset and no mixing occurs.
Fixed Options
Several options can be realized by adding or changing resistors.
LNA Input Impedance
The shipping configuration of the input impedance of the LNA
is 50 Ω to match the output impedance of most signal generators.
Input impedances up to 6 kΩ are obtained by selecting the R9 and
R10 values. Details concerning this circuit feature are found in
the AD8332 data sheet. For reference, Table 6 lists common values
of input impedance and corresponding feedback resistor values.
05543-067
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Figure 62. Evaluation Board (Actual Size)
FEATURES AND OPTIONS
The evaluation board has several user-configurable features and
options. Table 5 lists the configuration jumpers and their
functions.
Table 5. Jumper Functions
Jumper
ENBL
PH10
PH11
PH12
PH13
PH20
PH21
PH22
PH23
RST
Function
Enable or disable
the AD8333
Channel 1 Phase
Bit 0 (LSB)
Channel 1 Phase
Bit 1
Channel 1 Phase
Bit 2
Channel 1 Phase
Bit 3 (MSB)
Channel 2 Phase
Bit 0 (LSB)
Channel 2 Phase
Bit 1
Channel 2 Phase
Bit 2
Channel 2 Phase
Bit 3 (MSB)
Reset pin
Configuration
Bottom = disable; top = enable
Table 6. LNA External Component Values for Typical Values
of Source Impedance
RIN (Ω)
50
75
100
200
500
6k
RFB, Nearest STD 1% Value (Ω)
280
412
562
1.13 k
3.01 k
∞
CSH (pF)
22
12
8
1.2
None
None
Current Summing
Top = 0; bottom = 1
Top = 0; bottom = 1
Top = 0; bottom = 1
Top = 0; bottom = 1
Top = 1; bottom = 0
Top = 1; bottom = 0
Top = 1; bottom = 0
Top = 1; bottom = 0
The output transimpedance amplifiers, A1 through A4, are
configured as I-to-V converters to convert the output current of
the AD8333 to a voltage. The low-pass filters formed by the
feedback components are designed for single-channel operation
with ±5 V supplies.
Optional Resistors R4 and R5 sum the two channels. With R4
and R5 installed, R2 and R3 are removed, and then the sum of
the outputs is seen at the I1xO and Q1xO output SMA
connectors.
The user has the option to adjust the values of R39, R40, R41, or
R42 according to the power supply voltages and expected input
current levels. For the same supply voltages, if two channels are
summed together, the feedback resistors are halved and the
filter capacitor values doubled to optimize the output swing.
Left = reset; right = normal
Rev. C | Page 26 of 32
AD8333
Filter Capacitors C26, C29, C31, and C 32 establish the roll-off
characteristic according to the following well-known equation:
1
ωRC
where R is the value of R39, R40, R41, or R42, and C is the value
of C26, C29, C31, or C32.
Reset Input
For normal operation, the reset input is high (no reset). To drive
the reset with a dynamic signal, a provision is made to connect a
signal generator at the RST input. A 49.9 Ω, 0603 surface-mount
resistor can be installed at R15 to terminate the reset input for
pulsed experiments. In this configuration, the jumper at RST is
not used and must be removed to avoid loading the power supply.
Take care to avoid overdriving the LNA input of the AD8332.
The LNA gain is 19 dB (9.5×) and the maximum output swing
must not be exceeded; −10 dBm suffices for many experiments.
The f4LO input is ac-coupled to a 5 V LVDS buffer to provide an
ideal interface to the AD8333.
MEASUREMENT SETUP
The f4LO level is frequency dependent; refer to Figure 22 for
minimum signal levels, and then adjust the generator output level
accordingly.
Figure 63 is a layout of the AD8333-EVALZ showing the connectors and jumpers. Figure 65 shows a typical board and test
equipment setup with two signal generators, a power splitter,
and a ±5 V, 300 mA (minimum) power supply. For ease in
f4LO INPUT CHANNEL 1
PHASE BITS
+5V, GND, –5V
ENABLE
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CHANNEL 1
I OUTPUT
CHANNEL 1
RF INPUT
CHANNEL 1
Q OUTPUT
CHANNEL 2
I OUTPUT
CHANNEL 2
RF INPUT
CHANNEL 2
Q OUTPUT
CHANNEL 2
PHASE BITS
RESET
Figure 63. Evaluation Board Layout
Rev. C | Page 27 of 32
05543-066
f =
observing waveforms, the signal generators can be synchronized.
Remember that the f4LO signal generator frequency is four times
that of the nominal frequency of the RF source. For example, to
detect signals with a nominal center frequency of 5 MHz, an f4LO
frequency of 20 MHz is applied to the oscillator input. For an
applied RF signal of 5.01 MHz, the mix frequencies are 10 kHz
and 10.01 MHz. Because of the low-pass active filter of the
transconductance amplifiers (A1 through A4), the 10.01 MHz
component is suppressed, and only the 10 kHz is observed at
the output.
Rev. C | Page 28 of 32
Figure 64. Evaluation Board Schematic
IN2
L2
120 nH
FB
IN1
L1
120 nH
FB
VPS
R10
274Ω
VPS
C5
0.1 µF
C40
.018 µF
C3
22 pF
TP1
C4
TP2 0.1 µF
C6
0.1 µF
C2
22 pF
TP3
8
7
6
5
4
3
2
1
LOP1
9
10
LOP2
LON2
VPS2
INH2
LMD2
LMD1
INH1
VPS1
LON1
COM2
C1
TP4 0.1 µF
COM1
31
30
VIP1
11
VIP2
32
29
28
13
26
15
5
NC
COMM
VOH2
VOL2
1
6
7
16
C42
0.1 µF
22 VPS
23
24
R23
20Ω
R22
20Ω
R6
3.48kΩ
3
LOP
4
R1
100Ω
C43
1 nF
2
C17
0. 1µF
R13
49.9Ω
R7
1. 5kΩ
8
7
6
5
4
2
3
+5V
1
31
10
PH23
PH22
PH21
L
PH20
9
PH21
PH22
PH23
LODC
4LON
4LOP
COMM
PH13
PH12
PH11
32
PH10
PH11
PH12
L PH13 H
www.BDTIC.com/ADI
L5 120
nH FB
C9
0.1 µF
Z3
C13
0.1 µF DS90C401
17
18
19
20
VPSV 21
VOL1
VOH1
COMM
ENBV
25
RCLMP
VPS
+5V
C12
0.1 µF
Z3 SPARE 8
C11
0.1 µF
12
14
Z1
AD8332
27
HILO
MODE
C14
0.1 µF
ENBL
GAIN
C39
. 018 µF
R25
20Ω
PH10
PH20
R9
274Ω
VIN1
VIN2
30
H
11
29
VPOS
+
28
C7
10µF
10V
+5V
12
13
26
15
TP8
TP7
RST
C41
0.1µF
14
H
23
24
17
18
19
RST
R15
OPT
L
R2
0Ω
C51
0. 1µF
+5VS
+5VS
VPO S
H +5V
I2NO
16
I2PO
Q2PO
Q2NO
22 R4
Q1NO
OPT
21
VNEG
20
COMM
Q1PO
I1PO
I1NO
25
ENBL
+5VS
C44
0.1µF
-
7
+
4
+5VS
3
+5VS
-
7
+
4
-
7
3 +
4
-
7
3
+
4
C28
5PF
-5VS
C33
5PF
C52
0.1µF
5
6
C32
2.2NF
R42
787Ω
C30
5PF
6
R41
787Ω
C48
0.1µF
C31
2.2NF
A4
8 AD8021
1
2
5
5
6
C29
2.2NF
R40
787Ω
-5VS
I1
-5VS
R38
0Ω
I2
R35
0Ω Q 2
-5V
R33
0Ω Q1
-5VS
C47
0.1µF
L4
120nH FB
C50
0.1µF
A3
8 AD8021
1
2
C49
0.1µF
C36
0.1µF
R5
OPT
+5VS
3
R32
0Ω
L7
C27
5PF 120nH FB -5V
6
C26
2.2NF
R39
787Ω
A2
8 AD8021
1
2
5
C45
0.1µF
A1
8 AD8021
1
2
C46
0.1µF
R3
0Ω
L6 +5VS
120nH FB
-5V
C8
10µF
10V
L3
120nH FB
TP5
TP6
+
-5V
C24
0.1µF
27
DUT
AD8333
RF1P
RF2P
VCM1
VCM2
RF1N
RF2N
R26
20Ω
VPOS
VPOS
+5V
VPOS
VPOS
+5V
ENBL
RSET
G ND1 G ND2 G ND3 G ND4
AD8333
EVALUATION BOARD SCHEMATIC AND ARTWORK
05543-042
AD8333
TOP GENERATOR:
SIGNAL GENERATOR FOR f4LO INPUT,
TYPICAL SETTING: 20MHz
SIGNAL 1V p-p
BOTTOM GENERATOR:
SIGNAL GENERATOR FOR RF INPUT,
TYPICAL SETTING: 5.01MHz
POWER
SUPPLY
SYNCHRONIZE
GENERATORS
+5V
–5V
www.BDTIC.com/ADI
SIGNAL
INPUT(S)
Figure 65. Typical Board Test Connections (One Channel Shown)
Rev. C | Page 29 of 32
05543-065
POWER
SPLITTER
AD8333
BOARD LAYOUT
05543-070
05543-068
The AD8333 evaluation board has four layers. The interconnecting circuitry is located on the outer layers with the inner layers dedicated
as power and ground planes. Figure 66, Figure 67, Figure 69, and Figure 70 illustrate the copper patterns.
Figure 69. Ground Plane Copper
Figure 66. Component Side Copper
05543-069
05543-071
www.BDTIC.com/ADI
Figure 70. Power Plane Copper
05543-072
Figure 67. Wiring Side Copper
Figure 68. Component Side Silkscreen
Rev. C | Page 30 of 32
AD8333
ORDERING INFORMATION
BILL OF MATERIALS
Table 7.
Qty
4
23
Type
IC
Capacitor
Description
AD8021
0.1 μF, 16 V, 0603, X7R
2
2
4
4
2
1
1
7
7
1
6
1
1
2
1
4
4
10
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
IC
Connector
Ferrite bead
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Header
22 pF, 50 V, 5%, 0603
10 μF, 10 V, A size, tantalum
2.2 nF, 50 V, X7R, 10%, 0603
5 pF, 50 V, 0603
0.018 μF, 10%, 50 V, X7R, 0603
1 nF, 100 V, 10%, 0603, X7R
AD8333 I/Q demodulator
SMA female PC mount, RA
120 nH, 0603
100 Ω, 1%, 1/10 W, 0603
0 Ω, 5%, 1/16 W, 0603
3.48 kΩ, 1%, 1/10 W, 0603
1.5 kΩ, 1%, 1/10 W, 0603
274 Ω, 1/16 W, 1%, 0603
49.9 Ω, 1%, 1/16 W, 0603
20 Ω, 1%, 1/10 W, 0603
787 Ω, 1/16 W, 1%, 0603
3-pin 0.025" sq., 0.1" spacing
1
4
1
5
1
1
Test loop
Test loop
Test loop
Test loop
IC
IC
0.125" diameter, red
0.125" diameter, black
0.125" diameter, blue
0.125" diameter, purple
VGA AD8332
DRV LVDS dual differential
signal 8-lead SOIC
1
4
PC board
Bumper
10
Jumper
Reference Designator
A1 to A4
C1, C4, C5, C6, C9, C11, C12, C13,
C14, C17, C24, C36, C41, C42,
C44, C45, C46, C47, C48, C49,
C50, C51, C52
C2, C3
C7, C8
C26, C29, C31, C32
C27, C28, C30, C33
C39, C40
C43
DUT
I1, I2, IN1, IN2, LOP, Q1, Q2
L1, L2, L3, L4, L5, L6, L7
R1
R2, R3, R32, R33, R35, R38
R6
R7
R9, R10
R13
R22, R23, R25, R26
R39 to R42
ENBL, PH10, PH11, PH12, PH13,
PH20, PH21, PH22, PH23, RST
+5 V
GND1 to GND4
−5 V
TP5 to TP8, RST
Z1
Z3
Mfg. Part Number
AD8021ARZ
C0603C104K4RACTU
Manufacturer
Analog Devices, Inc.
KEMET Corporation
ECJ-1VC1H220J
T491A106M010AS
ECJ-1VB1H222K
ECJ-1VC1H050C
06035C183KAT2A
ECJ-1VB2A102K
AD8333ACPZ-WP
901-143-6RFX
BLM18BA750SN1D
ERJ-3EKF1000V
ERJ-2GE0R00X
ERJ-3EKF3481V
ERJ-3EKF1501V
ERJ-3EKF2740V
ERJ-3EKF49R9V
ERJ-3EKF20R0V
ERJ-3EKF7870V
22-11-2032
Panasonic
KEMET Corporation
Panasonic
Panasonic
AVX Corp.
Panasonic
Analog Devices, Inc.
Amphenol
Murata Manufacturing Co.
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Molex, Inc.
TP-104-01-02
TP-104-01-00
TP-104-01-06
TP-104-01-07
AD8332ACPZ
DS90C401M
Components Corp.
Components Corp.
Components Corp.
Components Corp.
Analog Devices, Inc.
National Semiconductor
09-A00941E
SJ-67A11
3M Worldwide
65474-001
FCI
www.BDTIC.com/ADI
Mount to wiring side of board,
black
Install at ENBL: top, PH10: top,
PH11: top, PH12: top, PH13: top,
PH20: bottom, PH21: bottom,
PH22: bottom, PH23: bottom,
and RST: right; orient when
board is in normal viewing
position with IN1 and IN2 SMA
connectors at left
Rev. C | Page 31 of 32
AD8333
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
17
16
0.80 MAX
0.65 TYP
0.30
0.23
0.18
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
011708-A
TOP
VIEW
1.00
0.85
0.80
PIN 1
INDICATOR
32
25
24
Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
www.BDTIC.com/ADI
Model
AD8333ACPZ-REEL 1
AD8333ACPZ-REEL71
AD8333ACPZ-WP1, 2
AD8333-EVALZ1
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
WP = waffle pack.
©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05543-0-9/08(C)
Rev. C | Page 32 of 32
Package Option
CP-32-2
CP-32-2
CP-32-2