I C CMOS 8 × 12 Unbuffered Analog Switch Array With Dual/Single Supplies

I2C® CMOS 8 × 12 Unbuffered Analog
Switch Array With Dual/Single Supplies
ADG2128
FEATURES
GENERAL DESCRIPTION
I2C-compatible interface
3.4 MHz high speed I2C option
32-lead LFCSP_VQ (5 mm × 5 mm)
Double-buffered input logic
Simultaneous update of multiple switches
Up to 300 MHz bandwidth
Fully specified at dual ±5 V/single +12 V operation
On resistance 35 Ω maximum
Low quiescent current < 20 μA
The ADG2128 is an analog cross point switch with an
array size of 8 × 12. The switch array is arranged so that
there are eight columns by 12 rows, for a total of 96 switch
channels. The array is bidirectional, and the rows and columns
can be configured as either inputs or outputs. Each of the 96
switches can be addressed and configured through the I2Ccompatible interface. Standard, full speed, and high speed
(3.4 MHz) I2C interfaces are supported. Any simultaneous
switch combination is allowed. An additional feature of the
ADG2128 is that switches can be updated simultaneously,
using the LDSW command. In addition, a RESET option
allows all of the switch channels to be reset/off. At power-on,
all switches are in the off condition. The device is packaged
in a 32-lead, 5 mm × 5 mm LFCSP_VQ.
APPLICATIONS
AV switching in TV
Automotive infotainment
AV receivers
CCTV
Ultrasound applications
KVM switching
Telecom applications
Test equipment/instrumentation
PBX systems
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FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
VL
ADG2128
SDA
INPUT
REGISTER
AND
7 TO 96
DECODER
1
LATCHES
96
LDSW
A2 A1 A0
1
8 × 12 SWITCH ARRAY
X0 TO X11 (I/O)
96
LDSW
GND
Y0 TO Y7 (I/O)
05464-001
SCL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADG2128
TABLE OF CONTENTS
Features ..............................................................................1
Load Switch (LDSW)................................................. 18
Applications.......................................................................1
Readback ..................................................................... 18
General Description .........................................................1
Serial Interface................................................................ 19
Functional Block Diagram ..............................................1
High Speed I2C Interface........................................... 19
Revision History ...............................................................2
Serial Bus Address...................................................... 19
Specifications.....................................................................3
Writing to the ADG2128............................................... 20
I2C Timing Specifications............................................7
Input Shift Register .................................................... 20
Timing Diagram ...........................................................8
Write Operation ......................................................... 22
Absolute Maximum Ratings............................................9
Read Operation .......................................................... 22
ESD Caution..................................................................9
Evaluation Board............................................................ 24
Pin Configuration and Function Descriptions...........10
Using the ADG2128 Evaluation Board ................... 24
Typical Performance Characteristics ...........................11
Power Supply .............................................................. 24
Test Circuits.....................................................................15
Schematics................................................................... 25
Terminology ....................................................................17
Outline Dimensions....................................................... 27
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Theory of Operation ......................................................18
Ordering Guide .......................................................... 27
RESET/Power-On Reset ............................................18
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Added I2C Information......................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 4............................................................................ 9
Changes to Figure 24...................................................................... 14
Changes to Terminology Section.................................................. 17
Changes to Figure 35...................................................................... 23
Changes to the Ordering Guide.................................................... 27
1/06—Revision 0: Initial Version
Rev. A | Page 2 of 28
ADG2128
SPECIFICATIONS
VDD = 12 V ± 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1
Table 1.
B Version
−40°C to
+25°C
+85°C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
Y Version
−40°C to
+25°C
+125°C
VDD − 2 V
On Resistance Matching
Between Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Channel Off Leakage, IOFF
Channel On Leakage, ION
DYNAMIC CHARACTERISTICS 2
COFF
CON
tON
30
35
32
37
45
50
4.5
8
2.3
3.5
14.5
18
40
42
57
9
4
20
±0.03
±0.03
VDD − 2 V
30
35
32
37
45
50
4.5
8
2.3
3.5
14.5
18
42
47
62
10
5
22
±0.03
±0.03
Unit
V max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
μA typ
μA typ
Conditions
VDD = +10.8 V, VIN = 0 V, IS = −10 mA
VDD = +10.8 V, VIN = +1.4 V, IS = −10 mA
VDD = +10.8 V, VIN = +5.4 V, IS = −10 mA
VDD = +10.8 V, VIN = 0 V, IS = −10 mA
VDD = 10.8 V, VIN = 0 V to +1.4 V, IS = −10 mA
VDD = 10.8 V, VIN = 0 V to +5.4 V, IS = −10 mA
VDD = 13.2 V
VX = 7 V/1 V, VY = 1 V/7 V
VX = VY = 1 V or 7 V
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tOFF
THD + N
11
18.5
170
185
210
250
0.04
190
255
PSRR
−3 dB Bandwidth
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Differential Gain
Differential Phase
Charge Injection
LOGIC INPUTS (Ax, RESET)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
11
18.5
170
185
210
250
0.04
260
90
dB typ
210
16.5
−69
210
16.5
−69
MHz typ
MHz typ
dB typ
−63
−76
0.4
0.6
−3.5
−63
−76
0.4
0.6
−3.5
dB typ
dB typ
% typ
° typ
pC typ
2.0
0.8
0.005
2.0
0.8
0.005
±1
Input Capacitance, CIN
195
pF typ
pF typ
ns typ
ns max
ns typ
ns max
% typ
7
±1
7
Rev. A | Page 3 of 28
V min
V max
μA typ
μA max
pF typ
RL = 300 Ω, CL = 35 pF
RL = 300 Ω, CL = 35 pF
RL = 10 kΩ, f = 20 Hz to 20 kHz,
VS = 1 V p-p
f = 20 kHz; without decoupling;
see Figure 24
Individual inputs to outputs
8 inputs to 1 output
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
VS = 4 V, RS = 0 Ω, CL = 1 nF
ADG2128
B Version
−40°C to
+85°C
+25°C
Parameter
LOGIC INPUTS (SCL, SDA)2
Input High Voltage, VINH
Y Version
−40°C to
+125°C
+25°C
0.7 VL
VL + 0.3
−0.3
0.3 VL
Input Low Voltage, VINL
Input Leakage Current, IIN
0.005
0.7 VL
VL + 0.3
−0.3
0.3 VL
0.005
±1
0.05 VL
Input Hysteresis
Input Capacitance, CIN
LOGIC OUTPUT (SDA)2
Output Low Voltage, VOL
7
Floating State Leakage Current
POWER REQUIREMENTS
IDD
±1
0.05 VL
7
0.4
0.6
±1
0.05
0.4
0.6
±1
0.05
1
ISS
0.05
1
0.05
1
1
Unit
V min
V max
V min
V max
μA typ
μA max
V min
pF typ
Conditions
VIN = 0 V to VL
V max
V max
μA max
ISINK = 3 mA
ISINK = 6 mA
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VL
IL
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Interface Inactive
0.3
Interface Active: 400 kHz fSCL
0.1
Interface Active: 3.4 MHz fSCL
0.4
0.3
2
2
0.1
μA typ
μA max
mA typ
mA max
mA typ
mA max
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0.2
1.2
1
2
0.2
0.4
1.7
Temperature range is as follows: B version: −40°C to +85°C; Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 28
-HS model only
ADG2128
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
B Version
−40°C to
+25°C +125°C
Y Version
−40°C to
+25°C +125°C
34
40
50
55
66
75
4.5
8
17
20
34
42
34
40
50
55
66
75
4.5
8
17
20
34
42
VDD − 2 V
On Resistance Matching
Between Channels, ∆RON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Channel Off Leakage, IOFF
Channel On Leakage, ION
DYNAMIC CHARACTERISTICS 2
COFF
CON
tON
45
65
85
9
23
45
50
70
95
10
25
48
Unit
V max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
±0.03
±0.03
±0.03
±0.03
μA typ
μA typ
6
9.5
170
200
210
250
0.04
300
18
−66
6
9.5
170
200
210
250
0.04
90
300
18
−64
pF typ
pF typ
ns typ
ns max
ns typ
ns max
% typ
dB typ
MHz typ
MHz typ
dB typ
−62
−79
1.5
1.8
−3
−62
−79
1.5
1.8
−3
Conditions
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = 0 V, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = +1.4 V, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to 0 V, IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VIN = VSS to +1.4 V, IS = −10 mA
VDD = 5.5 V, VSS = 5.5 V
VX = +4.5 V/−2 V, VY = −2 V/+4.5 V
VX = VY = −2 V or +4.5 V
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tOFF
THD + N
PSRR
−3 dB Bandwidth
Off Isolation
Channel-to-Channel Crosstalk
Adjacent Channels
Nonadjacent Channels
Differential Gain
Differential Phase
Charge Injection
LOGIC INPUTS (Ax, RESET)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
215
255
Input Low Voltage, VINL
260
dB typ
dB typ
% typ
° typ
pC typ
2.0
0.8
0.005
2.0
0.8
0.005
±1
Input Capacitance, CIN
LOGIC INPUTS (SCL, SDA)2
Input High Voltage, VINH
220
7
±1
7
0.7 VL
VL + 0.3
−0.3
0.3 VL
0.7 VL
VL + 0.3
−0.3
0.3 VL
Rev. A | Page 5 of 28
V min
V max
μA typ
μA max
pF typ
V min
V max
V min
V max
RL = 300 Ω, CL = 35 pF
RL = 300 Ω, CL = 35 pF
RL = 10 kΩ, f = 20 Hz to 20 kHz, VS = 1 V p-p
f = 20 kHz; without decoupling; see Figure 24
Individual inputs to outputs
8 inputs to 1 output
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
RL = 75 Ω, CL = 5 pF, f = 5 MHz
VS = 0 V, RS = 0 Ω, CL = 1 nF
ADG2128
B Version
−40°C to
+25°C +125°C
0.005
±1
0.05 VL
7
Parameter
Input Leakage Current, IIN
Input Hysteresis
Input Capacitance, CIN
LOGIC OUTPUT (SDA)2
Output Low Voltage, VOL
Floating State Leakage Current
POWER REQUIREMENTS
IDD
Y Version
−40°C to
+25°C +125°C
0.005
±1
0.05 VL
7
0.4
0.6
±1
0.05
0.4
0.6
±1
0.005
1
ISS
0.05
1
0.005
1
1
Unit
μA typ
μA max
V min
pF typ
Conditions
VIN = 0 V to VL
V max
V max
μA max
ISINK = 3 mA
ISINK = 6 mA
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VL
IL
Digital inputs = 0 V or VL
Interface Inactive
0.3
Interface Active: 400 kHz fSCL
0.1
Interface Active: 3.4 MHz fSCL
0.4
0.3
2
2
0.1
0.1
2
0.1
0.4
0.3
1
Digital inputs = 0 V or VL
0.3
Temperature range is as follows: B version: –40°C to +85°C; Y version: –40°C to +125°C.
Guaranteed by design, not subject to production test.
μA typ
μA max
mA typ
mA max
mA typ
mA max
-HS model only
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Rev. A | Page 6 of 28
ADG2128
I2C TIMING SPECIFICATIONS
VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 3.
Parameter 1
fSCL
t1
t2
t3
t4 3
t5
t6
t7
t8
t9
t10
Conditions
Standard mode
Fast mode
High speed mode 2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode2
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
ADG2108 Limit at TMIN, TMAX
Min
Max
100
400
3.4
1.7
Unit
kHz
kHz
4
0.6
MHz
MHz
μs
μs
60
120
4.7
1.3
ns
ns
μs
μs
160
320
250
100
10
0
0
ns
ns
ns
ns
ns
μs
μs
3.45
0.9
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
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0
0
4.7
0.6
160
4
0.6
160
4.7
1.3
4
0.6
160
70
150
1000
300
ns
ns
μs
μs
ns
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
20 + 0.1 CB
80
160
300
300
ns
ns
ns
ns
10
20
80
160
ns
ns
20 + 0.1 CB
B
10
20
B
Rev. A | Page 7 of 28
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time for a repeated start condition
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
ADG2128
Parameter 1
t11
t11A
t12
tSP
ADG2108 Limit at TMIN, TMAX
Min
Max
1000
20 + 0.1 CB
300
Conditions
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Standard mode
Fast mode
High speed mode2
CB = 100 pF maximum
CB = 400 pF maximum
Fast mode
High speed mode2
B
10
20
Unit
ns
ns
40
80
1000
300
ns
ns
ns
ns
20 + 0.1 CB
80
160
300
300
ns
ns
ns
ns
10
20
0
0
40
80
50
10
ns
ns
ns
ns
20 + 0.1 CB
B
10
20
B
Description
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
tFCL, fall time of SCL signal
Pulse width of suppressed spike
1
Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line; tR and tF are measured between
0.3 VDD and 0.7 VDD.
High speed I2C is available only in -HS models.
3
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
2
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TIMING DIAGRAM
t2
t11
t12
t6
SCL
t6
t4
t5
t3
t8
t1
t9
t10
SDA
t7
S
S
P
05464-002
P
S = START CONDITION
P = STOP CONDITION
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. A | Page 8 of 28
ADG2128
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog Inputs
Digital Inputs
Rating
15 V
−0.3 V to +15 V
+0.3 V to −7 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VL + 0.3 V or 30 mA,
whichever occurs first
Continuous Current
10 V on Input; Single Input
Connected to Single Output
1 V on Input; Single Input
Connected to Single Output
10 V on Input; Eight Inputs
Connected to Eight Outputs
Operating Temperature Range
Industrial (B Version)
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
32-Lead LFCSP_VQ
θJA Thermal Impedance
Reflow Soldering (Pb Free)
Peak Temperature
Time at Peak Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
65 mA
90 mA
25 mA
–40°C to +85°C
–40°C to +125°C
–65°C to +150°C
150°C
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108.2°C/W
260°C (+0/–5)
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 9 of 28
ADG2128
VL
28
SCL
29
SDA
30
A1
31
A0
RESET
32
VSS 1
A2
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
27
26
25
VDD
23
NC
22
X11
21
X10
20
X9
19
X8
7
18
X7
8
17
X6
6
X4
X5
9
10
11
12
13
14
15
16
Y7
X3
12 × 8
TOP VIEW
(Not to Scale)
Y6
5
Y5
X2
ADG2128
Y4
4
Y3
X1
Y2
3
Y1
X0
PIN 1
INDICATOR
Y0
2
NC = NO CONNECT
05464-003
24
NC
Exposed Paddle Soldered to VSS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions 1
Pin No.
1
2, 23
3 to 8,
17 to 22
9 to 16
24
25
26
27
Mnemonic
VSS
NC
X0 to X11
Description
Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin should be tied to GND.
No Connect.
Can be inputs or outputs.
Y0 to Y7
VDD
VL
SDA
SCL
28
29
30
31
32
A0
A1
A2
RESET
GND
Can be inputs or outputs.
Positive Power Supply Input.
Logic Power Supply Input.
Digital I/O. Bidirectional open drain data line. External pull-up resistor required.
Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data into the
device. External pull-up resistor required.
Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.
Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.
Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.
Ground Reference Point for All Circuitry on the ADG2128.
1
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It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.
Rev. A | Page 10 of 28
ADG2128
TYPICAL PERFORMANCE CHARACTERISTICS
90
200
TA = 25°C
IDS = 10mA
TA = 25°C
180 IDS = 10mA
80
160
VDD = 7.2V
VSS = –5V
VDD = +5V
120
RON (Ω)
RON (Ω)
70
VSS = 0V
VDD = +8V
140
100
80
VDD = 8V
60
50
60
VDD = 8.8V
VSS = 0V
VDD = +12V
20
0
–5 –4 –3 –2 –1 0
1
2
3
4
5
6
7
8
30
9 10 11 12
05464-025
40
05464-007
40
0
0.5
1.0
SOURCE VOLTAGE (V)
80
TA = 25°C
IDS = 10mA
3.5
4.0
4.5
5.0
TA = +125°C
60
65
TA = +85°C
50
RON (Ω)
VDD/VSS = ±5V
55
40
TA = +25°C
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30
25
–5.5
10
05464-017
35
–4.5
–3.5
–2.5
–1.5
–0.5
0.5
TA = –40°C
20
VDD/VSS = ±5.5V
0
–5
1.5
05464-026
45
–4
60
70
TA = 25°C
IDS = 10mA
VDD = 10.8V
60
–1
0
VDD = 12V
VSS = 0V
IDS = 10mA
50
55
1
TA = +125°C
TA = +85°C
40
VDD = 12V
RON (Ω)
50
–2
Figure 8. RON vs. Temperature, Dual ±5 V Supplies
Figure 5. RON vs. Source Voltage, Dual ±5 V Supplies
65
–3
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
45
TA = +25°C
30
TA = –40°C
40
20
35
VDD = 13.2V
30
0
1
2
3
4
5
6
7
0
8
05464-027
05464-018
10
25
20
3.0
VDD = +5V
VSS = –5V
IDS = 10mA
70
VDD/VSS = ±4.5V
RON (Ω)
2.5
Figure 7. RON vs. Source Voltage, VDD = 8 V ± 10%
85
RON (Ω)
2.0
SOURCE VOLTAGE (V)
Figure 4. Signal Range
75
1.5
0
1
2
3
4
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 9. RON vs. Temperature, VDD = 12 V
Figure 6. RON vs. Supplies, VDD = 12 V ± 10%
Rev. A | Page 11 of 28
5
6
ADG2128
80
18
VDD = 8V
VSS = 0V
IDS = 10mA
TA = +125°C
60
TA = +85°C
50
RON (Ω)
Y CHANNELS, VBIAS = 7V
14
LEAKAGE CURRENTS (nA)
70
VDD = 12V
VSS = 0V
16
40
TA = +25°C
30
TA = –40°C
20
X CHANNELS, VBIAS = 7V
12
10
8
Y CHANNELS, VBIAS = 1V
6
4
05464-013
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
05464-011
2
10
0
–2
4.0
0
20
40
SOURCE VOLTAGE (V)
Figure 10. RON vs. Temperature, VDD = 8 V
16
9
LEAKAGE CURRENTS (nA)
LEAKAGE CURRENTS (nA)
X CHANNELS,
VBIAS = +4V
6
120
X, Y CHANNELS;
VBIAS = 7V ON X CHANNEL;
1V ON Y CHANNEL
7
12
8
100
VDD = 12V
VSS = 0V
8
10
80
Figure 13. On Leakage vs. Temperature, 12 V Single Supply
VDD = +5V
VSS = –5V
14
60
TEMPERATURE (°C)
Y CHANNELS,
VBIAS = –2V
6
5
4
3
X, Y CHANNELS;
VBIAS = 1V ON X CHANNEL;
7V ON Y CHANNEL
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4
2
05464-014
0
0
20
40
60
80
100
0
–1
120
0
20
40
TEMPERATURE (°C)
60
80
100
120
TEMPERATURE (°C)
Figure 11. On Leakage vs. Temperature, Dual ±5 V Supplies
12
05464-012
1
2
Figure 14. Off Leakage vs. Temperature, 12 V Single Supply
0
VDD = 5V
VSS = –5V
–0.5
10
CHARGE INJECTION (pC)
X, Y CHANNELS;
VBIAS = +4V ON X CHANNEL;
–2V ON Y CHANNEL
6
4
X, Y CHANNELS;
VBIAS = –2V ON X CHANNEL;
+4V ON Y CHANNEL
2
–1.5
–2.0
–2.5
–3.0
–3.5
VDD = +5V, VSS = –5V
–4.0
–2
0
20
40
60
80
100
VDD = +12V, VSS = 0V
05464-030
0
05464-015
LEAKAGE CURRENTS (nA)
–1.0
8
–4.5
–5.0
–5
120
TEMPERATURE (°C)
–3
–1
1
3
5
7
9
SUPPLY VOLTAGE (V)
Figure 12. Off Leakage vs. Temperature, Dual ±5 V Supplies
Figure 15. Charge Injection vs. Supply Voltage
Rev. A | Page 12 of 28
11
ADG2128
0
240
–1
220
TOFF
INSERTION LOSS (dB)
VDD = 5V, VSS = 0V
180
TON
160
VDD = 12V, VSS = 0V
140
–2
–3
–4
–5
–6
–20
0
20
40
60
80
100
–8
10
120
VDD = +5V
VSS = –5V
TA = 25°C
05464-022
100
–40
–7
05464-029
120
1k
Figure 16. TON/TOFF Times vs. Temperature
–10
–20
INSERTION LOSS (dB)
–4
–5
–6
–40
–50
–60
–70
–80
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–90
VDD = +5V
VSS = –5V
TA = 25°C
1k
100k
10M
1G
–100
–110
10
10G
1k
10M
1G
Figure 20. Off Isolation vs. Frequency
–1
–20
–2
INSERTION LOSS (dB)
–3
–4
–5
–6
VDD = +5V TO +12V
VSS = –5V TO 0V
TA = 25°C
–40
ADJACENT
CHANNELS
–60
–80
NON-ADJACENT
CHANNELS
1k
100k
10M
1G
–120
10
10G
FREQUENCY (Hz)
05464-024
–100
VDD = 12V
VSS = 0V
TA = 25°C
05464-021
INSERTION LOSS (dB)
100k
FREQUENCY (Hz)
Figure 17. Individual Inputs to Individual Outputs Bandwidth,
Dual ±5 V Supply
–8
10
10G
VDD = +5V TO +12V
VSS = –5V TO 0V
TA = 25°C
FREQUENCY (Hz)
–7
1G
–30
05464-020
INSERTION LOSS (dB)
–3
–8
10
10M
Figure 19. One Input to Eight Outputs Bandwidth, 5 V Dual Supply
–2
–7
100k
FREQUENCY (Hz)
TEMPERATURE (°C)
05464-023
TON/TOFF (ns)
200
1k
100k
10M
FREQUENCY (Hz)
Figure 18. Individual Inputs to Individual Outputs Bandwidth,
12 V Single Supply
Figure 21. Crosstalk vs. Frequency
Rev. A | Page 13 of 28
1G
ADG2128
0.35
0
VDD = +5V
VSS = –5V
0.30
VDD = 5V/12V
VSS = –5V/0V
TA = 25°C
–20 0.2V p-p RIPPLE
VL = 5V
SWITCH ON,
WITHOUT DECOUPLING
0.25
ACPSRR (dB)
0.15
–60
–80
0.10
WITH DECOUPLING
VL = 3V
–100
05464-016
0.05
0
SWITCH OFF,
WITHOUT DECOUPLING
0
0.5
1.0
1.5
2.0
2.5
–120
100
3.0
FREQUENCY (MHz)
05464-028
IL (mA)
–40
0.20
1k
10k
100k
1M
Figure 24. ACPSRR
Figure 22. Digital Current (IL) vs. Frequency
1.8
1.6
1.4
VL = 5V
IL (mA)
1.2
1.0
0.8
0.6
0.4
VL = 3V
0
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05464-019
0.2
0
1
2
3
10M
FREQUENCY (Hz)
4
5
6
VLOGIC (V)
Figure 23. Digital Current (IL) vs. VLOGIC for Varying Digital Supply Voltage
Rev. A | Page 14 of 28
100M
1G
ADG2128
TEST CIRCUITS
The test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix.
IDS
V1
Y
IOFF
A
VX
VY
Figure 25. On Resistance
X
NC
VDD
VSS
VDD
VSS
X
A
VY
Figure 26. Off Leakage
0.1µF
ION
Y
Figure 27. On Leakage
0.1µF
50%
9TH DATA BIT
VOUT
Y
RL
300Ω
VX
CL
35pF
90%
VOUT
tOFF AND tON
GND
05464-034
RON = V1/IDS
X
Figure 28. Switching Times, tON, tOFF
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RX
VDD
VSS
VDD
VSS
X
0.1 µF
SW OFF
SW ON
Y
VOUT
DATA BIT
CL
1nF
VX
VOUT
GND
ΔVOUT
QINJ = CL × ΔVOUT
05464-035
0.1 µF
Figure 29. Charge Injection
VDD
VSS
VDD
NETWORK
ANALYZER
VSS
X
VSS
0.1µF
0.1µF
0.1µF
50Ω
VDD
NETWORK
ANALYZER
VSS
X
50Ω
50Ω
VX
VX
Y
Y
RL
50Ω
GND
OFF ISOLATION = 20 log
VOUT
VS
VOUT
V
RL
50Ω
GND
05464-036
V
INSERTION LOSS = 20 log
Figure 30. Off Isolation
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 31. Bandwidth
Rev. A | Page 15 of 28
VOUT
05464-037
VDD
0.1µF
05464-033
A
05464-032
VS
IOFF
Y
05464-031
X
ADG2128
VDD
VSS
0.1µF
NETWORK
ANALYZER
0.1µF
VDD
VOUT
RL
50Ω
VSS
Y1
X1
X2
Y2
R
50Ω
50Ω
DATA
BIT
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
05464-038
VX
R
50Ω
Figure 32. Channel-to-Channel Crosstalk
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Rev. A | Page 16 of 28
ADG2128
TERMINOLOGY
On Resistance (RON)
The series on-channel resistance measured between the
X input/output and the Y input/output.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitudes plus noise of a signal to
the fundamental.
On Resistance Match (ΔRON)
The channel-to-channel matching of on resistance when
channels are operated under identical conditions.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Resistance Flatness (RFLAT(ON))
The variation of on resistance over the specified range produced
by the specified analog input voltage change with a constant
load current.
Channel Off Leakage (IOFF)
The sum of leakage currents into or out of an off channel input.
Channel On Leakage (ION)
The current loss/gain through an on-channel resistance,
creating a voltage offset across the device.
Input Leakage Current (IIN)
The current flowing into a digital input when a specified low
level or high level voltage is applied to that input.
Input Off Capacitance (COFF)
The capacitance between an analog input and ground when the
switch channel is off.
Off Isolation
The measure of unwanted signal coupling through an off switch.
Crosstalk
The measure of unwanted signal that is coupled through from
one channel to another as a result of parasitic capacitance.
Differential Gain
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and is expressed as a percentage of the
largest chrominance amplitude.
Differential Phase
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or positive value and is
expressed in degrees of subcarrier phase.
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Input/Output On Capacitance (CON)
The capacitance between the inputs or outputs and ground
when the switch channel is on.
Charge Injection
The measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
Input High Voltage (VINH)
The minimum input voltage for Logic 1.
Digital Input Capacitance (CIN)
The capacitance between a digital input and ground.
Output On Switching Time (tON)
The time required for the switch channel to close. The time is
measured from 50% of the logic input change to the time the
output reaches 10% of the final value.
Output Off Switching Time (tOFF)
The time required for the switch to open. This time is measured
from 50% of the logic input change to the time the output
reaches 90% of the switch off condition.
Input Low Voltage (VINL)
The maximum input voltage for Logic 0.
Output Low Voltage (VOL)
The minimum input voltage for Logic 1.
Input Low Voltage (VINL)
The maximum output voltage for Logic 0.
IDD
Positive supply current.
ISS
Negative supply current.
Rev. A | Page 17 of 28
ADG2128
THEORY OF OPERATION
The ADG2128 is an analog cross point switch with an array size
of 8 × 12. The 12 rows are referred to as the X input/output lines,
while the eight columns are referred to as the Y input/output
lines. The device is fully flexible in that it connects any X line or
number of X lines with any Y line when turned on. Similarly, it
connects any X line with any number of Y lines when turned on.
LOAD SWITCH (LDSW)
Control of the ADG2128 is carried out via an I2C interface. The
device can be operated from single supplies of up to 13.2 V or
from dual ±5 V supplies. The ADG2128 has many attractive
features, such as the ability to reset all the switches, the ability to
update many switches at the same time, and the option of
reading back the status of any switch. All of these features are
described in more detail here in the Theory of Operation
section.
Transparent Mode
RESET/POWER-ON RESET
The ADG2128 offers the ability to reset all of the 96 switches to
the off state. This is done through the RESET pin. When the
RESET pin is low, all switches are open (off), and appropriate
registers are cleared. Note that the ADG2128 also has a poweron reset block. This ensures that all switches are in the off
condition on power-up of the device. In addition, all internal
registers are filled with 0s and remain so until a valid write to
the ADG2128 takes place.
LDSW is an active high command that allows a number of
switches to be simultaneously updated. This is useful in
applications where it is important to have synchronous
transmission of signals. There are two LDSW modes: the
transparent mode and the latched mode.
In this mode, the switch position changes after the new word
is written in. LDSW is set to 1.
Latched Mode
In this mode, the switch positions are not updated at the same
time that the input registers are written to. This is achieved by
setting LDSW to 0 for each word (apart from the last word)
written to the device. Then, setting LDSW to 1 for the last word
allows all of the switches in that sequence to be simultaneously
updated.
READBACK
Readback of the switch array conditions is also offered when in
standard mode and fast mode. Readback enables the user to
check the status of the switches of the ADG2128. This is very
useful when debugging a system.
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Rev. A | Page 18 of 28
ADG2128
SERIAL INTERFACE
The ADG2128 is controlled via an I2C-compatible serial bus.
The parts are connected to this bus as a slave device (no clock
is generated by the switch).
2.
The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low
during the ninth clock pulse, known as the acknowledge
bit. At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to or
read from its serial register. If the R/W bit is 1 (high), the
master reads from the slave device. If the R/W bit is 0
(low), the master writes to the slave device.
3.
Data is transmitted over the serial bus in sequences of
nine clock pulses: eight data bits followed by an acknowledge bit from the receiver of the data. Transitions on the
SDA line must occur during the low period of the clock
signal, SCL, and remain stable during the high period of
SCL, because a low-to-high transition when the clock is
high can be interpreted as a stop signal.
4.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition
is defined as a low-to-high transition on the SDA line
while SCL is high. In write mode, the master pulls the SDA
line high during the 10th clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse and then high during the 10th clock pulse
to establish a stop condition.
HIGH SPEED I2C INTERFACE
In addition to standard and full speed I2C, the ADG2188 also
supports the high speed (3.4 MHz) I2C interface. Only the -HS
models provide this added performance. See the Ordering
Guide for details.
SERIAL BUS ADDRESS
The ADG2128 has a 7-bit slave address. The four MSBs are
hard coded to 1110, and the three LSBs are determined by the
state of Pin A0, Pin A1, and Pin A2. By offering the facility to
hardware configure Pin A0, Pin A1, and Pin A2, up to eight
of these devices can be connected to a single serial bus.
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, defined as when a high-to-low transition on the
SDA line occurs while SCL is high. This indicates that an
address/data stream follows. All slave peripherals connected
to the serial bus respond to the start condition and shift in
the next eight bits, consisting of a 7-bit address (MSB first)
plus an R/W bit that determines the direction of the data
transfer, that is, whether data is written to or read from the
slave device.
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Refer to Figure 33 and Figure 34 for a graphical explanation
of the serial data transfer protocol.
Rev. A | Page 19 of 28
ADG2128
WRITING TO THE ADG2128
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial
clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
1
1
1
0
A2
A1
A0
R/W
DB8 (LSB)
DB15 (MSB)
DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0
DEVICE ADDRESS
DB0 (LSB)
DB7 (MSB)
X
DATA BITS
X
X
X
X
X
X
LDSW
DATA BITS
05464-004
DB16 (LSB)
DB23 (MSB)
Figure 33. Data-Words
Table 6. Input Shift Register Bit Function Descriptions
Bit
DB23 to DB17
Mnemonic
1110xxx
DB16
R/W
DB15
Data
DB14 to DB11
DB10 to DB8
DB7 to DB1
DB0
AX3 to AX0
AY2 to AY0
X
LDSW
Description
The MSBs of the ADG2128 are set to 1110. The LSBs of the address byte are set by the state
of the three address pins, Pin A0, Pin A1, and Pin A2.
Controls whether the ADG2128 slave device is read from or written to.
If R/W = 1, the ADG2128 is being read from.
If R/W = 0, the ADG2128 is being written to.
Controls whether the switch is to be open (off ) or closed (on).
If Data = 0, the switch is open/off.
If Data = 1, the switch is closed/on.
Controls I/Os X0 to X11. See Table 7 for the decode truth table.
Controls I/Os Y0 to Y7. See Table 7 for the decode truth table.
Don’t care.
This bit is useful when a number of switches need to be simultaneously updated.
If LDSW = 1, the switch position changes after the new word is read.
If LDSW = 0, the input data is latched, but the switch position is not changed.
www.BDTIC.com/ADI
As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines.
Table 7 shows the truth table for these bits. Note the full coding sequence is written out for Channel Y0, and Channel Y1 to Channel Y7
follow a similar pattern. Note also that the RESET pin must be high when writing to the device.
Table 7. Address Decode Truth Table
DB15
DATA
1
0
1
0
1
0
1
0
1
0
1
0
X
X
1
0
1
0
1
0
DB14
AX3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
DB13
AX2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
DB12
AX1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
DB11
AX0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
DB10
AY2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. A | Page 20 of 28
DB9
AY1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB8
AY0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Switch Configuration
X0 to Y0 (on)
X0 to Y0 (off )
X1 to Y0 (on)
X1 to Y0 (off )
X2 to Y0 (on)
X2 to Y0 (off )
X3 to Y0 (on)
X3 to Y0 (off )
X4 to Y0 (on)
X4 to Y0 (off )
X5 to Y0 (on)
X5 to Y0 (off )
Reserved
Reserved
X6 to Y0 (on)
X6 to Y0 (off )
X7 to Y0 (on)
X7 to Y0 (off )
X8 to Y0 (on)
X8 to Y0 (off )
ADG2128
DB15
DATA
1
0
1
0
1
0
X
X
1
0
..
1
1
0
..
1
1
0
..
1
1
0
..
1
1
0
..
1
1
0
..
1
1
0
..
1
DB14
AX3
1
1
1
1
1
1
1
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
DB13
AX2
0
0
1
1
1
1
1
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
DB12
AX1
1
1
0
0
0
0
1
1
0
0
0
0
0
..
0
0
0
..
0
0
0
..
0
0
0
..
0
0
0
..
0
0
0
..
0
DB11
AX0
1
1
0
0
1
1
0
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
0
0
..
1
DB10
AY2
0
0
0
0
0
0
0
0
0
0
..
0
0
0
..
0
0
0
..
0
1
1
..
1
1
1
..
1
1
1
..
1
1
1
..
1
DB9
AY1
0
0
0
0
0
0
0
0
0
0
..
0
1
1
..
1
1
1
..
1
0
0
..
0
0
0
..
0
1
1
..
1
1
1
..
1
DB8
AY0
0
0
0
0
0
0
0
0
1
1
..
1
0
0
..
0
1
1
..
1
0
0
..
0
1
1
..
1
0
0
..
0
1
1
..
1
Switch Configuration
X9 to Y0 (on)
X9 to Y0 (off )
X10 to Y0 (on)
X10 to Y0 (off )
X11 to Y0 (on)
X11 to Y0 (off )
Reserved
Reserved
X0 to Y1 (on)
X0 to Y1 (off )
X11 to Y1 (on)
X0 to Y2 (on)
X0 to Y2 (off )
X11 to Y2 (on)
X0 to Y3 (on)
X0 to Y3 (off )
X11 to Y3 (on)
X0 to Y4 (on)
X0 to Y4 (off )
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Rev. A | Page 21 of 28
X11 to Y4 (on)
X0 to Y5 (on)
X0 to Y5 (off )
X11 to Y5 (on)
X0 to Y6 (on)
X0 to Y6 (off )
X11 to Y6 (on)
X0 to Y7 (on)
X0 to Y7 (off )
X11 to Y7 (on)
ADG2128
WRITE OPERATION
When writing to the ADG2128, the user must begin with an
address byte and R/W bit, after which the switch acknowledges
that it is prepared to receive data by pulling SDA low. This
address byte is followed by the two 8-bit words. The write
operations for the switch array are shown in Figure 34. Note
that it is only the condition of the switch corresponding to the
bits in the data bytes that changes state. All other switches retain
their previous condition.
2.
Enter the readback address for the X line of interest,
the addresses of which are shown in Table 8. Note that
the ADG2128 is expecting a 2-byte write; therefore, be
sure to enter another byte of don’t cares. (see Figure 35).
c.
The ADG2128 then places the status of those eight
switches in a register that can be read back.
The second step involves reading back from the register
that holds the status of the eight switches associated with
your X line of choice.
READ OPERATION
Readback on the ADG2128 has been designed to work as a tool
for debug and can be used to output the status of any of the 96
switches of the device. The readback function is a 2-step
sequence that works as follows:
a.
As before, enter the I2C address of the ADG2128. This
time, set the R/W bit to 1 to indicate that you would
like to read back from the device.
b.
As with a write to the device, the ADG2128 outputs a
2-byte sequence during readback. Therefore, the first
eight bits of data out that are read back are all 0s. The
next eight bits of data that come back are the status of
the eight Y lines attached to that particular X line. If
the bit is a 1, then the switch is closed (on); similarly,
if it is a 0, the switch is open (off).
Select the relevant X line that you wish to read back from.
Note that there are eight switches connecting that X line to
the eight Y lines. The next step involves writing to the
ADG2128 to tell the part that you would like to know the
status of those eight switches.
a. Enter the I2C address of the ADG2128, and set the
R/W bit to 0 to indicate that you are writing to the
device.
The entire read sequence is shown in Figure 35.
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SCL
A2
SDA
START
COND
BY
MASTER
A1
A0
DATA
R/W
AX3
ACK
BY
SWITCH
ADDRESS BYTE
AX2
AX1
AX0
AY2
AY1
AY0
x
x
x
ACK
BY
SWITCH
DATA BYTE
x
x
x
DATA BYTE
x
LDSW
ACK
BY
SWITCH
Figure 34. Write Operation
Table 8. Readback Addresses for Each X Line
X Line
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
RB7
0
0
0
0
0
0
0
0
0
0
0
0
RB6
0
0
1
1
0
0
1
1
0
0
1
1
RB5
1
1
1
1
1
1
1
1
1
1
1
1
RB4
1
1
1
1
1
1
1
1
1
1
1
1
Rev. A | Page 22 of 28
RB3
0
1
0
1
0
1
0
1
0
1
0
1
RB2
1
1
1
1
1
1
1
1
1
1
1
1
RB1
0
0
0
0
0
0
0
0
1
1
1
1
RB0
0
0
0
0
1
1
1
1
0
0
0
0
STOP
COND
BY
MASTER
05464-005
1.
b.
ADG2128
SCL
A2
SDA
START
COND
BY
MASTER
A1
A0
RB7
R/W
ACK
BY
SWITCH
ADDRESS BYTE
RB6
RB5
RB4
RB3
RB2
RB1
DATA BYTE
RB0
x
x
x
ACK
BY
SWITCH
x
x
x
x
x
NO ACK
BY
SWITCH
DATA BYTE
STOP
COND
BY
MASTER
SCL
START
COND
BY
MASTER
ADDRESS BYTE
A1
A0
R/W
ACK
BY
SWITCH
Y7
DUMMY READBACK BYTE
ACK
BY
MASTER
Y6
Y5
Y4
Y2
READBACK BYTE
Figure 35. Read Operation
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Rev. A | Page 23 of 28
Y3
Y1
Y0
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
05464-006
A2
SDA
ADG2128
EVALUATION BOARD
The ADG2128 evaluation board allows designers to evaluate the
high performance ADG2128 8 × 12 switch array with minimum
effort.
The evaluation kit includes a populated, tested ADG2128
printed circuit board. The evaluation board interfaces to the
USB port of a PC, or it can be used as a standalone evaluation
board. Software is available with the evaluation board that
allows the user to easily program the ADG2128 through the USB
port. Schematics of the evaluation board are shown in Figure 36
and Figure 37. The software runs on any PC that has Microsoft®
Windows® 2000 or Windows XP installed.
USING THE ADG2128 EVALUATION BOARD
The ADG2128 evaluation kit is a test system designed to
simplify the evaluation of the ADG2128. Each input/output
of the part comes with a socket specifically chosen for easy
audio/video evaluation. An application note is also available
with the evaluation board and gives full information on
operating the evaluation board.
POWER SUPPLY
The ADG2128 evaluation board can be operated with both
single and dual supplies. VDD and VSS are supplied externally by
the user. The VL supply can be applied externally, or the USB
port can be used to power the digital circuitry.
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Rev. A | Page 24 of 28
ADG2128
SCHEMATICS
05464-039
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Figure 36. EVAL-ADG2128EB Schematic, USB Controller Section
Rev. A | Page 25 of 28
ADG2128
05464-040
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Figure 37. EVAL-ADG2128EB Schematic, Chip Section
Rev. A | Page 26 of 28
ADG2128
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm x 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG2128BCPZ-REEL 1
ADG2128BCPZ-REEL71
ADG2128BCPZ-HS-RL71
ADG2128YCPZ-REEL1
ADG2128YCPZ-REEL71
ADG2128YCPZ-HS-RL71
EVAL-ADG2128EB
1
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Temperature
Range
−40°C to +85°C
−40°C to +85°C
–40°C to +85°C
−40°C to +125°C
−40°C to +125°C
–40°C to +125°C
I2C Speed
100 kHz, 400 kHz
100 kHz, 400 kHz
100 kHz, 400 kHz, 3.4 MHz
100 kHz, 400 kHz
100 kHz, 400 kHz
100 kHz, 400 kHz, 3.4 MHz
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = Pb-free part.
Rev. A | Page 27 of 28
Package
Option
CP-32-3
CP-32-3
CP-32-3
CP-32-3
CP-32-3
CP-32-3
ADG2128
NOTES
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Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05464-0-5/06(0)
Rev. A | Page 28 of 28