500 MHz to 1700 MHz Balanced Mixer, ADL5367

500 MHz to 1700 MHz Balanced Mixer,
LO Buffer and RF Balun
ADL5367
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 8.3 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 34 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
VCMI
IFOP
IFON
PWDN
COMM
20
19
18
17
16
ADL5367
VPMX 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3
13
VGS1
COMM 4
12
VGS0
COMM 5
11
LOI1
BIAS
GENERATOR
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
6
7
8
9
10
VLO3
LGM3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
The ADL5367 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5367 incorporates
an RF balun, allowing optimal performance over a 500 MHz to
1700 MHz RF input frequency range. Performance is optimized for
RF frequencies from 500 MHz to 1200 MHz using a high-side LO
and for RF frequencies from 900 MHz to 1700 MHz using a
low-side LO. The balanced passive mixer arrangement provides
good LO-to-RF leakage, typically better than −35 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where inband blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
loss of 7.7 dB and can be used with a wide range of output
impedances.
08083-001
APPLICATIONS
The ADL5367 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5367 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.
The ADL5367 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer +
IF Amp
Dual Mixer +
IF Amp
500 to 1700
1200 to 2500
ADL5367
ADL5365
ADL5357
ADL5355
ADL5358
ADL5356
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
www.BDTIC.com/ADI
ADL5367
TABLE OF CONTENTS
Features .............................................................................................. 1 Upconversion .............................................................................. 15 Applications ....................................................................................... 1 Spur Tables .................................................................................. 16 General Description ......................................................................... 1 Circuit Description......................................................................... 17 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 17 Revision History ............................................................................... 2 LO Subsystem ............................................................................. 17 Specifications..................................................................................... 3 Applications Information .............................................................. 19 5 V Performance ........................................................................... 4 Basic Connections ...................................................................... 19 3.3 V Performance ........................................................................ 4 IF Port .......................................................................................... 19 Absolute Maximum Ratings............................................................ 5 Bias Resistor Selection ............................................................... 19 ESD Caution .................................................................................. 5 Mixer VGS Control DAC .......................................................... 19 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ............................................................................ 20 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 23 5 V Performance ........................................................................... 7 Ordering Guide .......................................................................... 23 3.3 V Performance ...................................................................... 14 REVISION HISTORY
10/09—Revision 0: Initial Version
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Rev. 0 | Page 2 of 24
ADL5367
SPECIFICATIONS
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
RF INPUT INTERFACE
Return Loss
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage 1
LO INTERFACE
LO Power
Return Loss
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE 2
PWDN Threshold
Logic 0 Level
Logic 1 Level
PWDN Response Time
PWDN Input Bias Current
1
2
Conditions
Min
Tunable to >20 dB over a limited bandwidth
Typ
Unit
1700
dB
Ω
MHz
450
5.5
Ω||pF
MHz
V
14
50
500
Differential impedance, f = 200 MHz
Externally generated
Max
34||1.9
30
3.3
−6
5.0
0
12.6
50
730
+10
1670
1.0
0.4
1.4
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
Device disabled
160
220
0.0
70
Apply the supply voltage from the external circuit through the choke inductors.
PWDN function is intended for use with VS ≤ 3.6 V only.
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Rev. 0 | Page 3 of 24
dBm
dB
Ω
MHz
V
V
V
ns
ns
μA
μA
ADL5367
5 V PERFORMANCE
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Power Conversion Loss
Voltage Conversion Loss
SSB Noise Figure
SSB Noise Figure Under Blocking
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (IP1dB)1
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
IF/3 Spurious
POWER SUPPLY
Positive Supply Voltage
Total Quiescent Current
1
Conditions
Min
Typ
Max
Unit
Including 1:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 50 Ω differential
6.5
7.7
1.4
8.3
21
8.5
dB
dB
dB
dB
28
34
dBm
80
dBm
25
−15
−40
−47
−75
−72
dBm
dBm
dBm
dBc
dBc
dBc
5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered
fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz,
each RF tone at 0 dBm
fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz,
each RF tone at 0 dBm
Exceeding 20 dBm RF power results in damage to the device
Unfiltered IF output
0 dBm input power
0 dBm input power
4.5
5
97
VS = 5 V
5.5
V
mA
Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
Power Conversion Loss
Voltage Conversion Loss
SSB Noise Figure
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
POWER INTERFACE
Supply Voltage
Quiescent Current
Power-Down Current
Conditions
Min
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
fRF1 = 1949.5 MHz, fRF2 = 1950.5 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1750 MHz,
each RF tone at −10 dBm
3.0
Resistor programmable
Device disabled
Typ
Unit
7.3
1
8.1
28.5
dB
dB
dB
dBm
75
dBm
3.3
56
150
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Rev. 0 | Page 4 of 24
Max
3.6
V
mA
μA
ADL5367
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage, VS
RF Input Level
LO Input Level
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
Rating
5.5 V
20 dBm
13 dBm
6.0 V
5.5 V
1.2 W
25°C/W
150°C
−40°C to +85°C
−65°C to +150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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Rev. 0 | Page 5 of 24
ADL5367
20
19
18
17
16
VCMI
IFOP
IFON
PWDN
COMM
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
PIN 1
INDICATOR
ADL5367
TOP VIEW
(Not to Scale)
15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
08083-002
VLO3 6
LGM3 7
VLO2 8
LOSW 9
NC 10
VPMX
RFIN
RFCT
COMM
COMM
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4, 5, 16
6, 8
7
9
10
11, 15
12, 13
14
17
18, 19
20
Mnemonic
VPMX
RFIN
RFCT
COMM
VLO3, VLO2
LGM3
LOSW
NC
LOI1, LOI2
VGS0, VGS1
VPSW
PWDN
IFON, IFOP
VCMI
EPAD (EP)
Description
Positive Supply Voltage for IF Amplifier.
RF Input. This pin must be ac-coupled.
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
Positive Supply Voltages for LO Amplifier.
LO Amplifier Bias Control.
LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V.
No Connect.
LO Inputs. This pin must be ac-coupled.
Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
Positive Supply Voltage for LO Switch.
Power Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode.
Differential IF Outputs.
No Connect. This pin can be grounded.
Exposed pad must be soldered to ground.
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Rev. 0 | Page 6 of 24
ADL5367
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
100
105
90
TA = +25°C
95
TA = +85°C
90
85
70
TA = +85°C
60
TA = +25°C
50
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
40
700
08083-017
80
700
80
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
08083-023
TA = –40°C
100
INPUT IP2 (dBm)
SUPPLY CURRENT (mA)
TA = –40°C
Figure 6. Input IP2 vs. RF Frequency
12
10.0
9.5
11
8.5
TA = +25°C
SSB NOISE FIGURE (dB)
CONVERSION LOSS (dB)
9.0
TA = +85°C
8.0
7.5
7.0
TA = –40°C
6.5
10
TA = +85ºC
9
TA = +25ºC
8
TA = –40ºC
7
6.0
6
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 4. Power Conversion Loss vs. RF Frequency
5
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 7. SSB Noise Figure vs. RF Frequency
40
38
TA = +25°C
34
32
TA = –40°C
30
TA = +85°C
28
26
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
08083-028
INPUT IP3 (dBm)
36
Figure 5. Input IP3 vs. RF Frequency
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Rev. 0 | Page 7 of 24
08083-011
5.0
700
08083-035
5.5
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
86
84
VPOS = 5.25V
82
VPOS = 5.25V
100
INPUT IP2 (dBm)
SUPPLY CURRENT (mA)
105
VPOS = 5V
95
90
VPOS = 4.75V
80
78
VPOS = 5V
VPOS = 4.75V
76
74
85
–20
0
20
40
60
80
TEMPERATURE (°C)
70
–40
08083-019
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
08083-025
72
Figure 11. Input IP2 vs. Temperature
12
10.0
VPOS = 4.75V
VPOS = 5V
VPOS = 5.25V
9.5
11
SSB NOISE FIGURE (dB)
CONVERSION LOSS (dB)
9.0
8.5
8.0
7.5
7.0
6.5
10
VPOS = 5.25V
9
VPOS = 5V
8
VPOS = 4.75V
7
6.0
6
–20
0
20
40
60
80
TEMPERATURE (°C)
5
–40
08083-038
5.0
–40
–20
0
20
40
Figure 9. Power Conversion Loss vs. Temperature
Figure 12. SSB Noise Figure vs. Temperature
40
38
VPOS = 5.25V
34
VPOS = 5V
VPOS = 4.75V
32
30
28
26
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
08083-030
INPUT IP3 (dBm)
36
60
TEMPERATURE (ºC)
Figure 10. Input IP3 vs. Temperature
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Rev. 0 | Page 8 of 24
80
08083-012
5.5
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
110
85
TA = +25°C
80
TA = –40°C
75
100
INPUT IP2 (dBm)
TA = +25°C
95
TA = +85°C
90
70
65
TA = +85°C
60
85
55
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
50
30
08083-016
80
30
TA = –40°C
80
130
180
230
280
330
380
430
380
430
IF FREQUENCY (MHz)
Figure 13. Supply Current vs. IF Frequency
08083-021
SUPPLY CURRENT (mA)
105
Figure 16. Input IP2 vs. IF Frequency
10.0
12
9.5
11
SSB NOISE FIGURE (dB)
CONVERSION LOSS (dB)
9.0
TA = +85°C
8.5
TA = +25°C
8.0
7.5
TA = –40°C
7.0
6.5
10
9
8
7
6.0
6
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
5
30
08083-033
5.0
30
80
130
180
230
280
Figure 17. SSB Noise Figure vs. IF Frequency
Figure 14. Power Conversion Loss vs. IF Frequency
40
38
TA = –40°C
34
TA = +25°C
32
30
TA = +85°C
26
30
80
130
180
230
280
330
IF FREQUENCY (MHz)
380
430
08083-026
INPUT IP3 (dBm)
36
28
330
IF FREQUENCY (MHz)
Figure 15. Input IP3 vs. IF Frequency
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Rev. 0 | Page 9 of 24
08083-010
5.5
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
10.0
–40
9.5
TA = +85°C
TA = +25°C
8.0
7.5
–70
TA = +85°C
–2
0
2
4
6
8
10
–100
700
08083-034
–4
LO POWER (dBm)
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 18. Power Conversion Loss vs. LO Power
Figure 21. IF/2 Spurious vs. RF Frequency
40
–40
–45
38
TA = –40°C
–50
TA = +25°C
IF/3 SPURIOUS (dBc)
INPUT IP3 (dBm)
TA = +25°C
–90
6.5
36
TA = –40°C
–80
TA = –40°C
7.0
6.0
–6
–60
08083-020
8.5
IF/2 SPURIOUS (dBc)
CONVERSION LOSS (dB)
–50
9.0
34
32
TA = +85°C
30
–55
–60
TA = +85°C
–65
TA = –40°C
–70
–75
TA = +25°C
28
–2
0
2
4
6
8
10
LO POWER (dBm)
Figure 19. Input IP3 vs. LO Power
–85
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 22. IF/3 Spurious vs. RF Frequency
90
TA = +25°C
85
TA = –40°C
75
TA = +85°C
70
65
60
55
50
–6
–4
–2
0
2
4
6
LO POWER (dBm)
8
10
08083-022
INPUT IP2 (dBm)
80
Figure 20. Input IP2 vs. LO Power
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Rev. 0 | Page 10 of 24
08083-040
–4
08083-027
26
–6
–80
ADL5367
100
RESISTANCE (Ω)
PERCENT (%)
80
60
40
36.5
3.6
36.0
3.4
35.5
3.2
35.0
3.0
34.5
2.8
34.0
2.6
33.5
2.4
33.0
2.2
32.5
2.0
32.0
1.8
31.5
1.6
31.0
1.4
CAPACITANCE (pF)
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
20
7.4
7.6
7.8
CONVERSION LOSS (dB)
8.0
8.2
1.2
30.5
30
08083-068
0
7.2
80
180
230
280
330
380
430
IF FREQUENCY (MHz)
Figure 23. Conversion Loss Distribution
Figure 26. IF Port Return Loss
100
0
80
5
RF RETURN LOSS (dB)
PERCENT (%)
130
08083-069
MEAN: 7.7
STANDARD DEVIATION: 0.18
60
40
20
10
15
20
35
INPUT IP3 (dBm)
37
39
25
700
750
2
80
4
LO RETURN LOSS (dB)
90
70
60
50
40
30
20
8.4
8.6
1000 1050 1100 1150 1200
8
10
12
SELECTED
14
UNSELECTED
18
MEAN: 8.3
STANDARD DEVIATION: 0.05
8.2
950
6
16
8.8
NOISE FIGURE (dB)
9.0
08083-063
PERCENTAGE (%)
0
8.0
900
Figure 27. RF Port Return Loss, Fixed IF
100
0
7.8
850
RF FREQUENCY (MHz)
Figure 24. Input IP3 Distribution
10
800
20
900
950
1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQUENCY (MHz)
Figure 28. LO Return Loss, Selected and Unselected
Figure 25. SSB Noise Figure Distribution
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Rev. 0 | Page 11 of 24
08083-007
33
08083-067
31
08083-013
MEAN: 34.67
STANDARD DEVIATION: 0.19
0
ADL5367
70
–20
65
–25
LO-TO-RF LEAKAGE (dBm)
LO SWITCH ISOLATION (dB)
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
TA = +25°C
60
TA = –40°C
55
TA = +85°C
50
–30
–35
TA = +85°C
TA = –40°C
–40
45
–45
40
700
–50
900
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 32. LO-to-RF Leakage vs. LO Frequency
–40
0
TA = +85°C
–5
–10
TA = +25°C
2LO LEAKAGE (dBm)
–46
–48
–50
–52
TA = –40°C
–54
–15
–25
–30
–35
–40
–58
–45
950
1000 1050 1100 1150 1200 1250 1300 1350 1400
RF FREQUENCY (MHz)
–50
900
950
1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQUENCY (MHz)
0
0
–10
3LO LEAKAGE (dBm)
–5
TA = –40°C
TA = +25°C
–15
TA = +85°C
–20
–25
–20
3LO TO IF
–30
–40
–50
3LO TO RF
950
1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQUENCY (MHz)
Figure 31. LO-to-IF Leakage vs. LO Frequency
–70
900
950
1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREUQENCY (MHz)
Figure 34. 3LO Leakage vs. LO Frequency
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Rev. 0 | Page 12 of 24
08083-015
–60
08083-031
LO-TO-IF LEAKAGE (dBm)
2LO TO IF
Figure 33. 2LO Leakage vs. LO Frequency
Figure 30. RF-to-IF Isolation vs. RF Frequency
–30
900
2LO TO RF
–20
–56
08083-039
RF-TO-IF ISOLATION (dBc)
–44
08083-014
–42
–10
1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQUENCY (MHz)
Figure 29. LO Switch Isolation vs. RF Frequency
–60
900
950
08083-032
750
08083-059
TA = +25°C
ADL5367
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
10
15
9
30
14
12
6
11
5
10
NOISE FIGURE
4
9
3
8
VGS = 0,
VGS = 0,
VGS = 1,
VGS = 1,
1
0
700
750
10
5
6
850
900
950
5
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
0
–30
–25
–20
–15
–10
–5
0
5
BLOCKER POWER (dBm)
10
Figure 38. SSB Noise Figure vs.10 MHz Offset Blocker Level
Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
140
40
VGS = 0,
VGS = 0,
VGS = 1,
VGS = 1,
38
0
1
0
1
120
SUPPLY CURRENT (mA)
36
34
INPUT IP3 (dBm)
15
7
0
1
0
1
800
20
08083-003
2
NOISE FIGURE (dB)
7
25
SSB NOISE FIGURE (dB)
13
08083-058
CONVERSION LOSS (dB)
CONVERSION LOSS
8
32
30
28
26
100
80
60
40
24
20
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
0
600
08083-062
20
700
1200
1400
40
INPUT IP3
11
35
10
25
NOISE FIGURE
20
CONVERSION LOSS
7
15
6
10
5
5
0
800
1000
1200
1400
1600
1800
BIAS RESISTOR VALUE (Ω)
08083-009
9
INPUT IP3 (dBm)
30
8
1600
1800
Figure 39. LO Supply Current vs. LO Bias Resistor Value
12
CONVERSION LOSS (dB) AND
SSB NOISE FIGURE (dBm)
1000
BIAS RESISTOR VALUE (Ω)
Figure 36. Input IP3 vs. RF Frequency
4
600
800
Figure 37. Power Conversion Loss, SSB Noise Figure, and
Input IP3 vs. LO Bias Resistor Value
www.BDTIC.com/ADI
Rev. 0 | Page 13 of 24
08083-008
22
ADL5367
3.3 V PERFORMANCE
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
85
64
80
TA = –40°C
75
60
TA = –40°C
TA = +25°C
58
INPUT IP2 (dBm)
SUPPLY CURRENT (mA)
62
56
TA = +85°C
70
TA = +25°C
65
TA = +85°C
60
55
54
50
52
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
40
700
08083-018
50
700
850
900
950
1000 1050 1100 1150 1200
Figure 43. Input IP2 vs. RF Frequency at 3.3 V
10.0
10.0
9.5
9.5
9.0
9.0
NOISE FIGURE (dB)
8.5
TA = +85°C
TA = +25°C
7.5
7.0
6.5
TA = +85°C
8.5
TA = +25°C
8.0
7.5
TA = –40°C
7.0
6.5
6.0
6.0
5.5
5.5
5.0
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 41. Power Conversion Loss vs. RF Frequency at 3.3 V
5.0
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 44. SSB Noise Figure vs. RF Frequency at 3.3 V
34
32
TA = –40°C
28
TA = +85°C
26
TA = +25°C
24
22
20
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
08083-029
INPUT IP3 (dBm)
30
Figure 42. Input IP3 vs. RF Frequency at 3.3 V
www.BDTIC.com/ADI
Rev. 0 | Page 14 of 24
08083-064
TA = –40°C
08083-036
CONVERSION LOSS (dB)
800
RF FREQUENCY (MHz)
Figure 40. Supply Current vs. RF Frequency at 3.3 V
8.0
750
08083-024
45
ADL5367
UPCONVERSION
10.0
9.5
9.5
9.0
9.0
8.5
8.0
TA = +85°C
7.5
7.0
TA = –40°C
TA = +25°C
6.5
8.0
6.5
5.5
5.5
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 45. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
5.0
700
TA = –40°C
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 47. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion
34
34
TA = –40°C
TA = +25°C
32
32
TA = +85°C
30
INPUT IP3 (dBm)
30
28
26
24
TA = –40°C
28
TA = +85°C
26
TA = +25°C
24
22
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 46. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
20
700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 48. Input IP3 vs. RF Frequency at 3.3 V, Upconversion
www.BDTIC.com/ADI
Rev. 0 | Page 15 of 24
08083-061
22
08083-060
20
700
TA = +25°C
7.0
6.0
750
TA = +85°C
7.5
6.0
5.0
700
INPUT IP3 (dBm)
8.5
08083-066
CONVERSION LOSS (dB)
10.0
08083-065
CONVERSION LOSS (dB)
TA = 25°C, fIF = 153 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.
ADL5367
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, IS = 97 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and
ZO = 50 Ω, unless otherwise noted.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−39.7
−84.6
<−100
<−100
<−100
<−100
1
−7.8
0.0
−68.8
−78.6
<−100
<−100
<−100
<−100
2
−24.6
−45.0
−77.4
−95.5
<−100
<−100
<−100
<−100
<−100
<−100
3
−35.7
−27.5
−72.8
−75.9
<−100
<−100
<−100
<−100
<−100
<−100
<−100
4
−53.0
−53.0
−80.2
−97.9
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
5
−47.4
−54.4
−80.9
−91.7
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
6
−71.8
−87.8
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
7
8
9
10
11
12
13
14
−96.8
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
3.3 V Performance
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 =
0 V, and ZO = 50 Ω, unless otherwise noted.
M
0
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
−40.5
−78.6
−93.9
<−100
<−100
<−100
1
−12.6
0.0
−59.5
−66.3
<−100
<−100
<−100
<−100
2
−28.8
−42.7
−64.8
−90.1
−95.6
<−100
<−100
<−100
<−100
<−100
3
−40.6
−27.1
−68.0
−63.0
−95.5
<−100
<−100
<−100
<−100
<−100
<−100
4
−43.0
−53.2
−65.9
−90.5
−97.0
<−100
<−100
<−100
<−100
<−100
<−100
<−100
5
−59.6
−50.7
−73.0
−77.8
<−100
−98.9
<−100
<−100
<−100
<−100
<−100
<−100
<−100
6
−71.8
−75.4
−96.4
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
7
8
9
10
11
12
13
14
−89.4
−95.6
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
www.BDTIC.com/ADI
Rev. 0 | Page 16 of 24
ADL5367
CIRCUIT DESCRIPTION
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
The ADL5367 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
A block diagram of the device is shown in Figure 49.
VCMI
IFOP
IFON
PWDN
COMM
20
19
18
17
16
ADL5367
VPMX 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3
13
VGS1
COMM 4
12
VGS0
COMM 5
11
LOI1
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
The IP3 performance can be optimized by adjusting the supply
current with an external resistor. Figure 37 and Figure 39
illustrate how various bias resistors affect the performance with a
5 V supply. Additionally, dc current can be saved by increasing
the resistor. It is permissible to reduce the dc supply voltage to
as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors and excessive dc power
dissipation may result.)
LO SUBSYSTEM
6
7
8
9
10
VLO3
LGM3
VLO2
LOSW
NC
NC = NO CONNECT
08083-051
BIAS
GENERATOR
Figure 49. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 500 MHz to 1700 MHz.
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or low-side injection
for RF signals in the 900 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion loss is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.
The ADL5367 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
www.BDTIC.com/ADI
Rev. 0 | Page 17 of 24
ADL5367
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5367 has a power-down mode that permits the dc
current to drop to <200 μA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
www.BDTIC.com/ADI
Rev. 0 | Page 18 of 24
ADL5367
APPLICATIONS INFORMATION
BASIC CONNECTIONS
BIAS RESISTOR SELECTION
The ADL5367 mixer is designed to upconvert or downconvert
between radio frequencies (RF) from 500 MHz to 1700 MHz and
intermediate frequencies (IF) from dc to 450 MHz. Figure 50
depicts the basic connections of the mixer. It is recommended
to ac-couple the RF and LO input ports to prevent non-zero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN capacitor value of 8 pF is recommended to provide the
optimized RF input return loss for the desired frequency band.
An external resistor, RBIAS LO, is used to adjust the bias current of the
integrated amplifiers at the LO terminals. It is necessary to have
a sufficient amount of current to bias the internal LO amplifier
to optimize dc current vs. optimum IIP3 performance. Figure 37
and Figure 39 provide the reference for the bias resistor selection
when lower power consumption is considered at the expense of
conversion gain and IP3 performance.
For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP),
must be driven differentially or using a 1:1 ratio transformer for
single ended operation. An 8 pF capacitor is recommended for
the RF output, Pin 2 (RFIN).
The ADL5367 features two logic control pins, Pin 12 (VGS0)
and Pin 13 (VGS1), that allow programmability for internal
gate-to-source voltages for optimizing mixer performance over
desired frequency bands. The evaluation board defaults both
VGS0 and VGS1 to ground. Power conversion loss, NF, and
IIP3 can be optimized, as shown in Figure 35 and Figure 36.
MIXER VGS CONTROL DAC
IF PORT
The real part of the output impedance is approximately 50 Ω,
as seen in Figure 26, which matches many commonly used SAW
filters without the need for a transformer. This results in a voltage
conversion loss that is approximately the same as the power
conversion loss, as shown in Table 3.
IF1_OUT
R1
0Ω
T1
C25
560pF
+5V
20
C24
560pF
19
10kΩ
18
17
16
10pF
4.7µF
ADL5367
+5V
22pF
1
15
2
14
LO2_IN
8pF
RF-IN
+5V
10pF
3
0.01µF
13
10pF
BIAS
GENERATOR
4
12
5
11
22pF
6
7
8
9
RBIAS LO
LO1_IN
10
10kΩ
10pF
10pF
Figure 50. Typical Application Circuit
www.BDTIC.com/ADI
Rev. 0 | Page 19 of 24
08082-052
+5V
ADL5367
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 51. The evaluation board is fabricated using Rogers®
RO3003 material. Table 7 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 52 to Figure 55.
IF1_OUT
R1
0Ω
T1
C24
560pF
C25
560pF
PWR_UP
R14
0Ω
C2
10µF
C21
10pF
VPMX
C1
8pF
C5
0.01µF
C4
10pF
LO2_IN
LOI2
RFIN
RF-IN
C12
22pF
COMM
PWDN
IFON
IFOP
L3
0Ω
VCMI
VPOS
R21
10kΩ
C20
10pF
VPSW
ADL5367
RFCT
C22
1nF
VGS1
COMM
VGS0
COMM
LOI1
VPOS
R22
10kΩ
R23
15kΩ
VGS1
LO1_IN
NC
LOSW
VLO2
LGM3
VLO3
VGS0
C10
22pF
LOSEL
VPOS
R9
1.1kΩ
VPOS
R4
10kΩ
C8
10pF
Figure 51. Evaluation Board Schematic
www.BDTIC.com/ADI
Rev. 0 | Page 20 of 24
08082-053
C6
10pF
ADL5367
Table 7. Evaluation Board Configuration
Components
C2, C6, C8,
C20, C21
C1, C4, C5
T1, R1, C24, C25
C10, C12, R4
R21
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Description
Power Supply Decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
IF Output Interface. T1 is a 1:1 impedance transformer used to provide
a single-ended IF output interface. Remove R1 for balanced output
operation. C24 and C25 are used to block the dc bias at the IF ports.
LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is
enabled when the LOSEL test point is logic low. LO2_IN is enabled
when LOSEL is pulled to logic high.
PWDN Interface. R21 pulls the PWDN logic low and enables the device.
The PWR_UP test point allows the PWDN interface to be exercised
using the an external logic generator. Grounding the PWDN pin for
nominal operation is allowed. Using the PWDN pin when supply
voltages exceed 3.3 V is not allowed.
Bias Control. R22 and R23 form a voltage divider to provide 3 V for
logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal operation.
R9 sets the bias point for the internal LO buffers. R14 sets the bias point
for the internal IF amplifier.
Default Conditions
C2 = 10 μF (Size 0603),
C6, C8, C20, C21 = 10 pF (Size 0402)
C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402),
C5 = 0.01 μF (Size 0402)
T1 = TC1-1-13M+ (Mini-Circuits),
R1 = 0 Ω (Size 0402),
C24, C25 = 560 pF (Size 0402)
C10, C12 = 22 pF (Size 0402),
R4 = 10 kΩ (Size 0402)
R21 = 10 kΩ (Size 0402)
C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603),
R9 = 1.1 kΩ (Size 0402), R14 = 0 Ω (Size 0402),
R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402),
VGS0 = VGS1 = 3-pin shunt
www.BDTIC.com/ADI
Rev. 0 | Page 21 of 24
08083-054
08083-056
ADL5367
Figure 54. Evaluation Board Power Plane, Internal Layer 2
Figure 53. Evaluation Board Ground Plane, Internal Layer 1
08083-057
08083-055
Figure 52. Evaluation Board Top Layer
Figure 55. Evaluation Board Bottom Layer
www.BDTIC.com/ADI
Rev. 0 | Page 22 of 24
ADL5367
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
15
PIN 1
INDICATOR
20
16
1
PIN 1
INDICATOR
4.75
BSC SQ
0.65
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
(BOTTOM VIEW)
5
10
0.90
0.85
0.80
12° MAX
SEATING
PLANE
0.70
0.65
0.60
0.35
0.28
0.23
0.75
0.60
0.50
0.05 MAX
0.01 NOM
COPLANARITY
0.05
0.20 REF
2.60 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
042209-B
TOP VIEW
6
11
Figure 56. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5367ACPZ-R7 1
ADL5367-EVALZ1
1
Temperature Range
−40°C to +85°C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
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Rev. 0 | Page 23 of 24
Package
Option
CP-20-5
Ordering
Quantity
1,500
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