High Voltage Latch-Up Proof, Dual SPDT Switches ADG5436

High Voltage Latch-Up Proof,
Dual SPDT Switches
ADG5436
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
8 kV HBM ESD rating
Low on resistance (<10 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
ADG5436
S1A
D1
S1B
IN1
IN2
S2A
APPLICATIONS
D2
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
09204-001
S2B
Figure 1. TSSOP Package
ADG5436
S1A
S2A
D2
D1
S2B
S1B
IN1
IN2
EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
09204-002
LOGIC
Figure 2. LFCSP Package
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5436 is a monolithic CMOS device containing two
independently selectable single-pole/single-throw (SPDT)
switches. An EN input on the LFCSP package enables or
disables the device. When disabled, all channels switch off. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
2. Low RON.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5436 can be operated from dual
supplies up to ±22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5436 can be operated from a
single-rail power supply up to 40 V.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
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TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
Applications ....................................................................................... 1
ESD Caution...................................................................................8
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ............................9
General Description ......................................................................... 1
Truth Table For Switches ..............................................................9
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits..................................................................................... 14
Specifications..................................................................................... 3
Terminology .................................................................................... 16
±15 V Dual Supply ....................................................................... 3
Trench Isolation .............................................................................. 17
±20 V Dual Supply ....................................................................... 4
Applications Information .............................................................. 18
12 V Single Supply ........................................................................ 5
Outline Dimensions ....................................................................... 19
36 V Single Supply ........................................................................ 6
Ordering Guide .......................................................................... 19
Continuous Current per Channel, Sx or Dx ............................. 7
REVISION HISTORY
6/11—Rev. 0 to Rev. A
Added ISS −40°C to +125°C Parameter .......................................... 5
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/10—Revision 0: Initial Version
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SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
25°C
9.8
11
0.35
0.7
1.2
1.6
±0.05
±0.25
±0.1
±0.4
±0.1
±0.4
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −10 mA; see Figure 25
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V , IS = −10 mA
14
16
0.9
1.1
2
2.2
±0.75
±3.5
±2
±12
±2
±12
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 28
VS = ±10 V, VD =  10 V; see Figure 28
VS = VD = ±10 V; see Figure 24
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
5
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD
170
235
173
230
124
160
55
Charge Injection, QINJ
200
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−78
dB typ
Channel-to-Channel Crosstalk
−58
dB typ
Total Harmonic Distortion + Noise
0.009
% typ
−3 dB Bandwidth
Insertion Loss
102
−0.7
MHz typ
dB typ
CS (Off )
CD (Off )
CD (On), CS (On)
18
62
83
pF typ
pF typ
pF typ
tON
tOFF
285
316
280
351
193
218
18
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
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Parameter
POWER REQUIREMENTS
IDD
25°C
−40°C to +85°C
45
55
0.001
ISS
−40°C to +125°C
70
1
VDD/VSS
1
±9/±22
Unit
µA typ
µA max
µA typ
µA max
V min/V max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
9
10
0.35
0.7
1.5
1.8
±0.05
±0.25
±0.1
±0.4
±0.1
±0.4
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±15 V, IS = −10 mA; see Figure 25
VDD = +18 V, VSS = −18 V
VS = ±15 V , IS = −10 mA
13
15
0.9
1.1
2.2
2.5
±0.75
±3.5
±2
±12
±2
±12
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
5
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD
158
217
164
213
110
152
50
Charge Injection, QINJ
250
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
−78
dB typ
Channel-to-Channel Crosstalk
−58
dB typ
Total Harmonic Distortion + Noise
0.007
% typ
−3 dB Bandwidth
100
MHz typ
tON
tOFF
260
293
256
287
173
194
15
VS = ±15 V, IS = −10 mA
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see Figure 28
VS = ±15 V, VD =  15 V; see Figure 28
VS = VD = ±15 V; see Figure 24
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 30
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ADG5436
Parameter
Insertion Loss
25°C
−0.6
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
18
63
82
ISS
−40°C to +85°C
−40°C to +125°C
pF typ
pF typ
pF typ
50
70
0.001
±9/±22
μA typ
μA max
μA typ
μA max
V min/V max
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
110
1
VDD/VSS
1
Unit
dB typ
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
19
27
31
Ω max
Ω typ
0.8
4.4
5.5
1
1.2
VS = 0 V to 10 V, IS = −10 mA
6.5
7.5
Ω max
Ω typ
Ω max
nA typ
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 28
±0.05
±0.25
±0.1
±0.75
Drain Off Leakage, ID (Off )
±0.4
±0.1
±0.4
±2
±12
±2
±12
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±3.5
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
5
Break-Before-Make Time Delay, tD
250
346
250
358
135
178
125
Charge Injection, QINJ
80
tON
tOFF
VS = 0 V to 10 V, IS = −10 mA; see
Figure 25
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
22
0.4
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
437
501
445
512
212
237
50
nA max
nA typ
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 28
nA max
nA typ
nA max
VS = VD = 1 V/10 V; see Figure 24
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 32
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 34
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Rev. A | Page 5 of 20
ADG5436
Parameter
Off Isolation
25°C
−78
−40°C to +85°C
Unit
dB typ
Channel-to-Channel Crosstalk
−58
dB typ
Total Harmonic Distortion + Noise
0.075
% typ
−3 dB Bandwidth
Insertion Loss
106
−1.3
MHz typ
dB typ
22
67
85
pF typ
pF typ
pF typ
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
40
50
9/40
μA typ
μA max
V min/V max
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
65
VDD
1
−40°C to +125°C
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C
−40°C to +85°C
10.6
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
15
17
Ω max
Ω typ
0.7
2.7
3.2
0.9
1.1
VS = 0 V to 30 V, IS = −10 mA
3.8
4.5
Ω max
Ω typ
Ω max
nA typ
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 28
±0.05
±0.25
±0.1
±0.75
Drain Off Leakage, ID (Off )
±0.4
±0.1
±0.4
±2
±12
±2
±12
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±3.5
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
tON
VS = 0 V to 30 V, IS = −10 mA;
see Figure 25
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −10 mA
12
0.35
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
5
174
246
180
247
270
303
270
301
nA max
nA typ
VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 28
nA max
nA typ
nA max
VS = VD = 1 V/30 V; see Figure 24
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
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Rev. A | Page 6 of 20
Parameter
tOFF
Break-Before-Make Time Delay, tD
25°C
127
179
55
−40°C to +85°C
−40°C to +125°C
Charge Injection, QINJ
250
Unit
ns typ
ns max
ns typ
ns min
pC typ
193
215
Off Isolation
−78
dB typ
Channel-to-Channel Crosstalk
−58
dB typ
Total Harmonic Distortion + Noise
0.03
% typ
−3 dB Bandwidth
Insertion Loss
98
−0.8
MHz typ
dB typ
19
40
78
pF typ
pF typ
pF typ
18
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
80
100
VDD
1
µA typ
µA max
V min/V max
130
9/40
Test Conditions/Comments
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 32
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 1 kΩ, 18 V p-p, f = 20 Hz to
20 kHz; see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
122
217
77
116
44
53
mA maximum
mA maximum
130
229
80
121
45
54
mA maximum
mA maximum
84
150
56
90
36
48
mA maximum
mA maximum
110
196
70
109
42
52
mA maximum
mA maximum
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ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer
Board)
16-Lead LFCSP
Reflow Soldering Peak
Temperature, Pb Free
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
375 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
30.4°C/W
260(+0/−5)°C
1
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Current should be limited to the maximum ratings given.
2
See Table 5.
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VDD
TOP VIEW
VSS 5 (Not to Scale) 12 S2B
S1B 2
VSS 3
D2
NC 7
10
S2A
NC 8
9
IN2
NC = NO CONNECT
GND 4
ADG5436
TOP VIEW
(Not to Scale)
NC 5
11
09204-003
GND 6
PIN 1
INDICATOR
D1 1
13
12 EN
11 VDD
10 S2B
9 D2
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
09204-004
ADG5436
14 NC
NC
S1B 4
13 NC
14
NC 7
NC
D1 3
S2A 8
NC
15
16 S1A
16
IN2 6
IN1 1
S1A 2
15 IN1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. LFCSP Pin Configuration
Figure 3. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
3
1
4
2
5
3
6
4
7, 8, 14 to 16 5, 7, 13, 14
9
6
10
8
11
9
12
10
13
11
N/A
12
EP
Mnemonic
IN1
S1A
D1
S1B
VSS
GND
NC
IN2
S2A
D2
S2B
VDD
EN
Exposed Pad
Function
Logic Control Input 1.
Source Terminal 1A. This pin can be an input or output.
Drain Terminal 1. This pin can be an input or output.
Source Terminal 1B. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
No Connect.
Logic Control Input 2.
Source Terminal 2A. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Source Terminal 2B. This pin can be an input or output.
Most Positive Power Supply Potential.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, INx logic inputs determine the on switches.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
TRUTH TABLE FOR SWITCHES
Table 8. ADG5436 TSSOP Truth Table
INx
0
1
SxA
Off
On
SxB
On
Off
Table 9. ADG5436 LFCSP Truth Table
EN
0
1
1
INx
X
0
1
SxA
Off
Off
On
SxB
Off
On
Off
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TYPICAL PERFORMANCE CHARACTERISTICS
16
12
VDD = +10V
VDD = +9V VSS = –10V
VSS = –9V
TA = 25°C
14
10
ON RESISTANCE (Ω)
VDD = +11V
VSS = –11V
12
ON RESISTANCE (Ω)
TA = 25°C
10
8
= +13.5V
VDD10
VSS = –13.5V
6
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
VDD = 36V
VSS = 0V
VDD = 32.4V
VSS = 0V
8
6
VDD = 39.6V
VSS = 0V
4
4
2
–10
–5
0
10
5
15
20
VS, VD (V)
0
0
5
10
15
20
25
30
35
40
45
09204-042
–15
09204-134
0
–20
15
09204-140
2
VS, VD (V)
Figure 8. On Resistance vs. VS, VD (Single Supply)
Figure 5. On Resistance vs. VS, VD (Dual Supply)
18
12
VDD = +18V
VSS = –18V
10
16
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
14
8
VDD = +20V
VSS = –20V
6
VDD = +22V
VSS = –22V
4
TA = +125°C
12
TA = +85°C
10
TA = +25°C
8
TA = –40°C
6
4
2
2
TA = 25°C
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
0
–15
09204-135
0
–25
–10
–5
0
5
10
VS, VD (V)
Figure 9. On Resistance vs. VD or VS for Different Temperatures, ±15 V Dual Supply
Figure 6. On Resistance vs. VS, VD (Dual Supply) Included
16
25
VDD = +10V
VSS = 0V
VDD = 10.8V
VSS = 0V
VDD = +9V
VSS = 0V
20
14
12
ON RESISTANCE (Ω)
TA = 25°C
15
10
VDD = 11V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
TA = +125°C
10
TA = +85°C
8
TA = +25°C
6
TA = –40°C
4
5
0
0
2
4
6
8
10
12
VS, VD (V)
Figure 7. On Resistance vs. VS, VD (Single Supply)
14
VDD = +20V
VSS = –20V
0
–20
–15
–10
–5
0
5
VS, VD (V)
10
15
20
09204-141
2
09204-041
ON RESISTANCE (Ω)
VDD = +15V
VSS = –15V
Figure 10. On Resistance vs. VD or VS for Different Temperatures, ±20 V Dual Supply
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ADG5436
0.8
LEAKAGE CURRENT (nA)
TA = +125°C
20
TA = +85°C
15
TA = +25°C
TA = –40°C
10
5
ID (OFF) – +
0.4
IS (OFF) + –
0.2
0
ID, IS (ON) – –
–0.2
IS (OFF) – +
ID (OFF) + –
–0.4
2
4
6
8
10
12
–0.6
09204-142
0
VS, VD (V)
0
0.6
TA = +85°C
8
TA = +25°C
6
TA = –40°C
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
10
4
2
15
20
25
30
35
40
VS, VD (V)
0
0
0.6
LEAKAGE CURRENT (nA)
IS (OFF) + –
0.2
0
–0.2
ID, IS (ON) – –
ID (OFF) + –
IS (OFF) – +
–0.4
IS (OFF) – +
50
75
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
ID, IS (ON) + +
ID (OFF) – +
25
ID (OFF) + –
100
125
Figure 15. Leakage Currents vs. Temperature, 12 V Single Supply
ID, IS (ON) + +
ID (OFF) – +
0.4
IS (OFF) + –
0.2
0
–0.2
ID, IS (ON) – –
IS (OFF) – +
–0.4
ID (OFF) + –
–0.6
0
25
50
75
100
125
TEMPERATURE (°C)
09204-047
LEAKAGE CURRENT (nA)
IS (OFF) + –
0.8
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0.4
ID (OFF) – +
TEMPERATURE (°C)
Figure 12. On Resistance vs. VS (VD) for Different Temperatures, 36 V Single Supply
0.6
125
ID, IS (ON) + +
0.2
–0.2
09204-143
10
5
100
0.4
ID, IS (ON) – –
VDD = 36V
VSS = 0V
0
75
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
14
TA = +125°C
50
Figure 14. Leakage Currents vs. Temperature, ±20 V Single Supply
16
12
25
TEMPERATURE (°C)
Figure 11. On Resistance vs. VD or VS for Different Temperatures, 12 V Single Supply
0
ID, IS (ON) + +
–0.6
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 16. Leakage Currents vs. Temperature, 36 V Single Supply
Figure 13. Leakage Currents vs. Temperature, ±15 V Dual Supply
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Rev. A | Page 11 of 20
09204-049
ON RESISTANCE (Ω)
25
0
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
0.6
09204-048
VDD = 12V
VSS = 0V
09204-046
30
0
–10
–20
–20
–30
–30
ACPSRR (dB)
TA = 25°C
–10 VDD = +15V
VSS = –15V
–60
–40
–70
–80
–80
–90
–90
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
DECOUPLING
CAPACITORS
–60
–70
–100
1k
NO DECOUPLING
CAPACITORS
–50
–100
1k
1M
10M
20k
Figure 20. ACPSRR vs. Frequency
0.10
TA = 25°C
VDD = +15V
VSS = –15V
LOAD = 1kΩ
TA = 25°C
0.09
–20
0.08
–30
0.07
THD + N (%)
CROSSTALK (dB)
–10
100k
FREQUENCY (Hz)
Figure 17. Off Isolation vs. Frequency
0
10k
09204-038
–50
TA = 25°C
VDD = +15V
VSS = –15V
09204-039
–40
09204-044
OFF ISOLATION (dB)
0
–40
–50
–60
VDD = 12V, VSS = 0V, VS = 6V p-p
0.06
0.05
0.04
VDD = 36V, VSS = 0V, VS = 18V p-p
–70
0.03
–80
0.02
–90
0.01
VDD = 15V, VSS = 15V, VS = 15V p-p
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
09204-040
VDD = 20V, VSS = 20V, VS = 20V p-p
0
5k
10k
15k
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
Figure 21. THD + N vs. Frequency
0
450
TA = 25°C
VDD = +15V
VSS = –15V
TA = 25°C
–0.5
–1.0
350
VDD = +36V
VSS = 0V
250
VDD = +15V
VSS = –15V
200
INSERTION LOSS (dB)
300
VDD = +20V
VSS = –20V
150
100
50
0
–20
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
VDD = +12V
VSS = 0V
–10
0
10
20
30
VS (V)
Figure 19. Charge Injection vs. Source Voltage
40
09204-034
CHARGE INJECTION (pC)
400
–5.0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 22. Bandwidth
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100M
1G
09204-037
–100
10k
400
350
300
VDD = 12V
VSS = 0V
VDD = 36V
VSS = 0V
200
VDD = +20V
VSS = –20V
150
VDD = +15V
VSS = –15V
100
50
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
09204-035
TIME (ns)
250
Figure 23. tTRANSITION Time vs. Temperature
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ADG5436
TEST CIRCUITS
ID (ON)
IS (OFF)
A
A
VD
NC = NO CONNECT
SxA/SxB
Dx
ID (OFF)
VS
A
VD
Figure 24. On Leakage
09204-024
Dx
09204-025
SxA/SxB
NC
Figure 28. Off Leakage
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VDD
VSS
RS
SxA/SxB
V
VS
V p-p
Dx
Dx
VIN
RL
1kΩ
GND
Figure 25. On Resistance
VDD
Figure 29. THD + Noise
VSS
0.1µF
0.1µF
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VOUT
VDD
SxA
VSS
VDD
RL
50Ω
SxB
Dx
INx
RL
50Ω
NETWORK
ANALYZER
VSS
SxA
NC
SxB
50Ω
VS
VIN
GND
RL
50Ω
GND
VOUT
VS
09204-032
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
INSERTION LOSS = 20 log
VDD
VSS
0.1µF
VDD
INx
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 30. Bandwidth
Figure 26. Channel-to-Channel Crosstalk
0.1µF
NETWORK
ANALYZER
VSS
SxA
NC
SxB
50Ω
50Ω
VS
Dx
RL
50Ω
GND
VOUT
VS
VOUT
09204-030
VIN
OFF ISOLATION = 20 log
50Ω
Dx
INx
VS
VOUT
09204-033
VS
09204-023
IDS
Figure 27. Off Isolation
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Rev. A | Page 14 of 20
VOUT
09204-031
SxA/SxB
INx
ADG5436
VDD
VSS
VIN
50%
50%
VIN
50%
50%
VSS
VDD
SxB
VS
0.1µF
Dx
SxA
VOUT
RL
300Ω
INx
CL
35pF
GND
VIN
90%
90%
VOUT
tON
tOFF
09204-026
0.1µF
Figure 31. Switching Times
0.1µF
VDD
VSS
VDD
VSS
SxB
VS
0.1µF
VIN
Dx
VOUT
SxA
RL
300Ω
INx
VOUT
CL
35pF
80%
tD
tD
09204-027
GND
VIN
Figure 32. Break-Before-Make Time Delay tD
3V
ENABLE
DRIVE (VIN)
50%
50%
VDD
VSS
VDD
VSS
INx
SxA
VS
SxB
0V
tON (EN)
tOFF (EN)
0.9VOUT
OUTPUT
0.9VOUT
Dx
EN
OUTPUT
VIN
50Ω
300Ω
35pF
09204-028
GND
Figure 33. Enable Delay, tON (EN), tOFF (EN)
VS
VDD
VSS
VDD
VSS
VIN (NORMALLY
CLOSED SWITCH)
SxB
Dx
SxA
INx
VIN
0.1µF
GND
ON
OFF
NC
VOUT
CL
1nF
VIN (NORMALLY
OPEN SWITCH)
VOUT
∆VOUT
QINJ = CL × ∆VOUT
Figure 34. Charge Injection
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Rev. A | Page 15 of 20
09204-029
0.1µF
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN is the digital input capacitance.
ISS
ISS represents the negative supply current.
tON
tON represents the delay between applying the digital control
input and the output switching on.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
RON
RON represents the ohmic resistance between Terminal D and
Terminal S.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the part to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
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TRENCH ISOLATION
NMOS
PMOS
P-WELL
N-WELL
In the ADG5436, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 35. Trench Isolation
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09204-045
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace and other harsh environments that are prone to latchup, which is an undesirable high current state that can lead to
device failure and persist until the power supply is turned off.
The ADG5436 high voltage switches allow single-supply
operation from 9 V to 40 V and dual supply operation from
±9 V to ±22 V. The ADG5436 (as well as other select devices
within this family) achieves an 8 kV human body model ESD
rating, which provides a robust solution eliminating the need
for separate protect circuitry designs in some applications.
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OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
08-16-2010-C
TOP VIEW
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG5436BRUZ
ADG5436BRUZ-REEL7
ADG5436BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
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Package Option
RU-16
RU-16
CP-16-17
NOTES
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09204-0-6/11(A)
www.BDTIC.com/ADI