Difet OPA627 OPA637 Precision High-Speed

®
OPA627
OPA637
OPA
627
OPA
627
Precision High-Speed
Difet ® OPERATIONAL AMPLIFIERS
FEATURES
APPLICATIONS
● VERY LOW NOISE: 4.5nV/√Hz at 10kHz
● FAST SETTLING TIME:
OPA627—550ns to 0.01%
OPA637—450ns to 0.01%
● PRECISION INSTRUMENTATION
● FAST DATA ACQUISITION
● DAC OUTPUT AMPLIFIER
● OPTOELECTRONICS
● LOW VOS: 100µV max
● LOW DRIFT: 0.8µV/°C max
● LOW IB: 5pA max
● SONAR, ULTRASOUND
● HIGH-IMPEDANCE SENSOR AMPS
● HIGH-PERFORMANCE AUDIO CIRCUITRY
● OPA627: Unity-Gain Stable
● OPA637: Stable in Gain ≥ 5
● ACTIVE FILTERS
High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not possible with previous precision FET op
amps. The OPA627 is unity-gain stable. The OPA637
is stable in gains equal to or greater than five.
DESCRIPTION
The OPA627 and OPA637 Difet operational amplifiers provide a new level of performance in a precision
FET op amp. When compared to the popular OPA111
op amp, the OPA627/637 has lower noise, lower offset
voltage, and much higher speed. It is useful in a broad
range of precision and high speed analog circuitry.
Difet fabrication achieves extremely low input bias
currents without compromising input voltage noise
performance. Low input bias current is maintained
over a wide input common-mode voltage range with
unique cascode circuitry.
The OPA627/637 is fabricated on a high-speed, dielectrically-isolated complementary NPN/PNP process. It
operates over a wide range of power supply voltage—
±4.5V to ±18V. Laser-trimmed Difet input circuitry
provides high accuracy and low-noise performance
comparable with the best bipolar-input op amps.
Trim
1
The OPA627/637 is available in plastic DIP, SOIC
and metal TO-99 packages. Industrial and military
temperature range models are available.
7
+VS
Trim
5
Output
6
+In
3
–In
2
–VS
4
Difet ®, Burr-Brown Corp.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
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©1989 Burr-Brown Corporation
SBOS165
PDS-998H
Printed in U.S.A. March, 1998
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, and VS = ±15V, unless otherwise noted.
OPA627BM, BP, SM
OPA637BM, BP, SM
PARAMETER
CONDITIONS
OFFSET VOLTAGE (1)
Input Offset Voltage
AP, BP, AU Grades
Average Drift
AP, BP, AU Grades
Power Supply Rejection
VS = ±4.5 to ±18V
INPUT BIAS CURRENT (2)
Input Bias Current
Over Specified Temperature
SM Grade
Over Common-Mode Voltage
Input Offset Current
Over Specified Temperature
SM Grade
MIN
TYP
MAX
100
250
0.8
2
106
40
100
0.4
0.8
120
1
5
1
50
VCM = 0V
VCM = 0V
VCM = 0V
VCM = ±10V
VCM = 0V
VCM = 0V
1
0.5
NOISE
Input Voltage Noise
Noise Density: f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Voltage Noise, BW = 0.1Hz to 10Hz
Input Bias Current Noise
Noise Density, f = 100Hz
Current Noise, BW = 0.1Hz to 10Hz
INPUT IMPEDANCE
Differential
Common-Mode
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Specified Temperature
Common-Mode Rejection
OPEN-LOOP GAIN
Open-Loop Voltage Gain
Over Specified Temperature
SM Grade
OPA627AM, AP, AU
OPA637AM, AP, AU
MIN
TYP
MAX
UNITS
250
500
2
100
130
280
1.2
2.5
116
µV
µV
µV/°C
µV/°C
dB
2
10
2
pA
nA
nA
pA
pA
nA
nA
2
1
5
1
50
15
8
5.2
4.5
0.6
40
20
8
6
1.6
20
10
5.6
4.8
0.8
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
1.6
30
2.5
60
2.5
48
fA/√Hz
fAp-p
*
*
Ω || pF
Ω || pF
1013 || 8
1013 || 7
FREQUENCY RESPONSE
Slew Rate: OPA627
OPA637
Settling Time: OPA627 0.01%
0.1%
OPA637 0.01%
0.1%
Gain-Bandwidth Product: OPA627
OPA637
Total Harmonic Distortion + Noise
VCM = ±10.5V
±11
±10.5
106
±11.5
±11
116
*
*
100
*
*
110
V
V
dB
VO = ±10V, RL = 1kΩ
VO = ±10V, RL = 1kΩ
VO = ±10V, RL = 1kΩ
112
106
100
120
117
114
106
100
116
110
dB
dB
dB
40
100
55
135
550
450
450
300
16
80
0.00003
*
*
*
*
*
*
*
*
*
*
*
V/µs
V/µs
ns
ns
ns
ns
MHz
MHz
%
G
G
G
G
G
G
=
=
=
=
=
=
–1, 10V Step
–4, 10V Step
–1, 10V Step
–1, 10V Step
–4, 10V Step
–4, 10V Step
G=1
G = 10
G = +1, f = 1kHz
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Current
±4.5
OUTPUT
Voltage Output
Over Specified Temperature
Current Output
Short-Circuit Current
Output Impedance, Open-Loop
10
2
±11.5
±11
RL = 1kΩ
VO = ±10V
±35
1MHz
TEMPERATURE RANGE
Specification: AP, BP, AM, BM, AU
SM
Storage: AM, BM, SM
AP, BP, AU
θJ-A: AM, BM, SM
AP, BP
AU
±15
±7
±12.3
±11.5
±45
+70/–55
55
–25
–55
–60
–40
200
100
160
±18
±7.5
*
*
*
*
*
*
*
*
*
*
*
*
±100
*
+85
+125
+150
+125
*
*
*
*
*
*
*
*
*
V
V
mA
V
mA
mA
Ω
°C
°C
°C
°C
°C/W
°C/W
°C/W
* Specifications same as “B” grade.
NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25°C. See Typical Performance Curves for warmed-up performance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
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OPA627, 637
2
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Top View
Supply Voltage .................................................................................. ±18V
Input Voltage Range .............................................. +VS + 2V to –VS – 2V
Differential Input Range ....................................................... Total VS + 4V
Power Dissipation ........................................................................ 1000mW
Operating Temperature
M Package .................................................................. –55°C to +125°C
P, U Package ............................................................. –40°C to +125°C
Storage Temperature
M Package .................................................................. –65°C to +150°C
P, U Package ............................................................. –40°C to +125°C
Junction Temperature
M Package .................................................................................. +175°C
P, U Package ............................................................................. +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
SOlC (soldering, 3s) ................................................................... +260°C
DIP/SOIC
Offset Trim
1
8
No Internal Connection
–In
2
7
+VS
+In
3
6
Output
–VS
4
5
Offset Trim
NOTE: (1) Stresses above these ratings may cause permanent damage.
Top View
TO-99
No Internal Connection
PACKAGE/ORDERING INFORMATION
8
+VS
Offset Trim
1
–In
7
2
6
3
+In
Output
5
4
Offset Trim
–VS
Case connected to –VS.
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
TEMPERATURE
RANGE
OPA627AP
OPA627BP
OPA627AU
OPA627AM
OPA627BM
OPA627SM
Plastic DIP
Plastic DIP
SOIC
TO-99 Metal
TO-99 Metal
TO-99 Metal
006
006
182
001
001
001
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
OPA637AP
OPA637BP
OPA637AU
OPA637AM
OPA637BM
OPA637SM
Plastic DIP
Plastic DIP
SOIC
TO-99 Metal
TO-99 Metal
TO-99 Metal
006
006
182
001
001
001
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
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3
OPA627, 637
®
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.
TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH
INPUT VOLTAGE NOISE SPECTRAL DENSITY
100
Input Voltage Noise (µV)
100
10
10
1
0.1
RMS
0.01
1
1
10
100
1k
10k
100k
1M
1
10M
10
100
VOLTAGE NOISE vs SOURCE RESISTANCE
10k
100k
1M
10M
OPEN-LOOP GAIN vs FREQUENCY
1k
140
–
120
+
Voltage Gain (dB)
Voltage Noise (nV/ √ Hz)
1k
Bandwidth (Hz)
Frequency (Hz)
RS
100
Comparison with
OPA27 Bipolar Op
Amp + Resistor
OPA627 + Resistor
10
OPA637
100
80
60
40
OPA627
20
Spot Noise
at 10kHz
Resistor Noise Only
0
–20
1
1k
100
10k
100k
1M
10M
100M
1
Source Resistance ( Ω)
OPA627 GAIN/PHASE vs FREQUENCY
–10
10
1
100k
1M
100M
20
–120
–150
Gain (dB)
–120
Phase
Phase
Gain
10
–180
0
–210
100
–10
–210
1
10
Frequency (MHz)
4
–150
–180
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OPA627, 637
10M
–90
Frequency (MHz)
®
10k
30
Gain
0
1k
–90
Phase (Degrees)
75° Phase
Margin
100
OPA637 GAIN/PHASE vs FREQUENCY
20
10
10
Frequency (Hz)
30
Gain (dB)
p-p
Noise Bandwidth:
0.1Hz to indicated
frequency.
100
Phase (Degrees)
Voltage Noise (nV/ √ Hz)
1k
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
OPEN-LOOP GAIN vs TEMPERATURE
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
125
Output Resistance (Ω)
100
Voltage Gain (dB)
120
115
110
60
40
20
105
–75
0
–50
–25
0
25
50
75
100
2
125
20
2k
20k
200k
Frequency (Hz)
COMMON-MODE REJECTION vs FREQUENCY
COMMON-MODE REJECTION vs
INPUT COMMON MODE VOLTAGE
2M
20M
130
Common-Mode Rejection (dB)
120
OPA637
100
80
OPA627
60
40
20
1
10
100
1k
10k
100k
1M
120
110
100
90
80
–15
0
10M
–10
–5
0
5
10
15
Common-Mode Voltage (V)
Frequency (Hz)
POWER-SUPPLY REJECTION AND COMMON-MODE
REJECTION vs TEMPERATURE
POWER-SUPPLY REJECTION vs FREQUENCY
125
140
120
PSR
CMR and PSR (dB)
Power-Supply Rejection (dB)
200
Temperature (°C)
140
Common-Mode Rejection Ratio (dB)
80
100
–VS PSRR 627
and 637
80
60
+VS PSRR 627
637
40
120
CMR
115
110
20
105
0
1
10
100
1k
10k
100k
1M
–75
10M
Frequency (Hz)
–50
–25
0
25
50
75
100
125
Temperature (°C)
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5
OPA627, 637
®
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
OUTPUT CURRENT LIMIT vs TEMPERATURE
100
8
+IL at VO = 0V
Output Current (mA)
Supply Current (mA)
80
7.5
7
6.5
+IL at VO = +10V
60
40
–IL at VO = 0V
20
–IL at VO = –10V
0
6
–75
–50
–25
0
25
50
75
100
–75
125
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
OPA637 GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
OPA627 GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
160
120
60
24
Slew Rate
16
55
GBW
12
8
–75
–25
0
25
50
75
100
140
80
120
GBW
100
60
80
40
50
–50
100
–50
–75
125
–25
OPA627 TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
G = +1
VI
–
600 Ω
1
VO = ±10V
+
–
100pF
5kΩ
600 Ω
G = +10
VI
0.1
549 Ω
VO = ±10V
5k Ω
600Ω
VI
Measurement BW: 80kHz
G = +10
0.0001
+
–
100pF
549Ω
0.001
75
100
125
G = +50
+
–
100pF
THD+N (%)
THD+N (%)
0.01
VI
50
OPA637 TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
G = +10
VO = ±10V
+
25
Temperature (°C)
Temperature (°C)
0.1
0
VO = ±10V
5k Ω
600Ω
100pF
102 Ω
0.01
G = +50
Measurement BW: 80kHz
0.001
G = +1
0.00001
G = +10
0.0001
20
100
1k
10k
20k
20
Frequency (Hz)
®
100
1k
Frequency (Hz)
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OPA627, 637
6
10k
20k
Slew Rate (V/µs)
Gain-Bandwidth (MHz)
20
Slew Rate (V/µs)
Gain-Bandwidth (MHz)
Slew Rate
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
INPUT BIAS CURRENT
vs POWER SUPPLY VOLTAGE
INPUT BIAS AND OFFSET CURRENT
vs JUNCTION TEMPERATURE
20
10k
100
Input Bias Current (pA)
Input Current (pA)
1k
IB
10
IOS
1
NOTE: Measured fully
warmed-up.
15
TO-99
10
Plastic
DIP, SOIC
5
TO-99 with 0807HS Heat Sink
0
0.1
–50
–25
0
25
50
75
100
125
150
±4
±6
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
±12
±14
±16
±18
INPUT OFFSET VOLTAGE WARM-UP vs TIME
1.2
50
Beyond Linear
Common-Mode Range
1.1
Offset Voltage Change (µV)
Input Bias Current Multiplier
±10
Supply Voltage (±VS)
Junction Temperature (°C)
1
0.9
Beyond Linear
Common-Mode Range
0.8
25
0
–25
–50
–15
–10
–5
0
5
Common-Mode Voltage (V)
10
15
0
1
2
3
4
5
6
Time From Power Turn-On (Min)
SETTLING TIME vs CLOSED-LOOP GAIN
MAX OUTPUT VOLTAGE vs FREQUENCY
100
30
Error Band: ±0.01%
Settling Time (µs)
Output Voltage (Vp-p)
±8
20
OPA637
10
10
OPA627
1
OPA637
OPA627
0.1
0
100k
1M
10M
100M
–1
Frequency (Hz)
–10
–100
–1000
Closed-Loop Gain (V/V)
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7
OPA627, 637
®
TYPICAL PERFORMANCE CURVES
(CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.
SETTLING TIME vs ERROR BAND
1500
–
1000
+
RF
–5V
2kΩ
OPA627
RI 2kΩ
RF 2kΩ
CF 6pF
OPA637
500Ω
2kΩ
4pF
Settling Time (µs)
+5V
RI
Settling Time (ns)
SETTLING TIME vs LOAD CAPACITANCE
3
CF
OPA627
G = –1
500
OPA637
G = –4
Error Band:
±0.01%
2
OPA627
G = –1
1
OPA637
G = –4
0
0.001
0
0.01
0.1
1
10
0
150
Error Band (%)
200
300
400
500
Load Capacitance (pF)
APPLICATIONS INFORMATION
RF < 4RI
The OPA627 is unity-gain stable. The OPA637 may be used
to achieve higher speed and bandwidth in circuits with noise
gain greater than five. Noise gain refers to the closed-loop
gain of a circuit as if the non-inverting op amp input were
being driven. For example, the OPA637 may be used in a
non-inverting amplifier with gain greater than five, or an
inverting amplifier of gain greater than four.
–
+
OPA627
OPA627
–
+
Buffer
Non-Inverting Amp
G<5
RI
RF < 4R
When choosing between the OPA627 or OPA637, it is
important to consider the high frequency noise gain of your
circuit configuration. Circuits with a feedback capacitor
(Figure 1) place the op amp in unity noise-gain at high
frequency. These applications must use the OPA627 for
proper stability. An exception is the circuit in Figure 2,
where a small feedback capacitance is used to compensate
for the input capacitance at the op amp’s inverting input. In
this case, the closed-loop noise gain remains constant with
frequency, so if the closed-loop gain is equal to five or
greater, the OPA637 may be used.
–
+
–
+
OPA627
Bandwidth
Limiting
RI
OPA627
–
+
OPA627
Integrator
Inverting Amp
G < |–4|
–
+
OPA627
Filter
FIGURE 1. Circuits with Noise Gain Less than Five Require
the OPA627 for Proper Stability.
®
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OPA627, 637
8
OFFSET VOLTAGE ADJUSTMENT
The OPA627/637 is laser-trimmed for low offset voltage
and drift, so many circuits will not require external adjustment. Figure 3 shows the optional connection of an external
potentiometer to adjust offset voltage. This adjustment should
not be used to compensate for offsets created elsewhere in a
system (such as in later amplification stages or in an A/D
converter) because this could introduce excessive temperature drift. Generally, the offset drift will change by approximately 4µV/°C for 1mV of change in the offset voltage due
to an offset adjustment (as shown on Figure 3).
amp contributes little additional noise. Below 1kΩ, op amp
noise dominates over the resistor noise, but compares
favorably with precision bipolar op amps.
CIRCUIT LAYOUT
As with any high speed, wide bandwidth circuit, careful
layout will ensure best performance. Make short, direct
interconnections and avoid stray wiring capacitance—especially at the input pins and feedback circuitry.
The case (TO-99 metal package only) is internally connected
to the negative power supply as it is with most common op
amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages
has no internal connection.
C2
Power supply connections should be bypassed with good
high frequency capacitors positioned close to the op amp
pins. In most cases 0.1µF ceramic capacitors are adequate.
The OPA627/637 is capable of high output current (in
excess of 45mA). Applications with low impedance loads or
capacitive loads with fast transient signals demand large
currents from the power supplies. Larger bypass capacitors
such as 1µF solid tantalum capacitors may improve dynamic
performance in these applications.
R2
C1
–
+
R1
OPA637
C1 = CIN + CSTRAY
C2 =
R1 C1
R2
FIGURE 2. Circuits with Noise Gain Equal to or Greater than
Five May Use the OPA637.
+VS
100kΩ
NOISE PERFORMANCE
Some bipolar op amps may provide lower voltage noise
performance, but both voltage noise and bias current noise
contribute to the total noise of a system. The OPA627/637
is unique in providing very low voltage noise and very low
current noise. This provides optimum noise performance
over a wide range of sources, including reactive source
impedances. This can be seen in the performance curve
showing the noise of a source resistor combined with the
noise of an OPA627. Above a 2kΩ source resistance, the op
7
2
3
6
+
4
OPA627/637
±10mV Typical
Trim Range
–VS
FIGURE 3. Optional Offset Voltage Trim Circuit.
Buffer
2
–
6
In
5
–
3
Non-inverting
2
10kΩ to 1MΩ
Potentiometer
(100kΩ preferred)
1
+
Out
In
OPA627
3
–
6
Out
+
OPA627
TO-99 Bottom View
Inverting
In
2
3
OPA627
–
6
4
3
5
Out
+
2
Board Layout for Input Guarding:
Guard top and bottom of board.
Alternate—use Teflon® standoff for sensitive input pins.
6
7
1
Teflon® E.I. du Pont de Nemours & Co.
8 No Internal Connection
To Guard Drive
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FIGURE 4. Connection of Input Guard for Lowest IB.
9
OPA627, 637
®
INPUT BIAS CURRENT
Difet fabrication of the OPA627/637 provides very low
input bias current. Since the gate current of a FET doubles
approximately every 10°C, to achieve lowest input bias
current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current
of the OPA627/637 can lead to higher chip temperature. A
simple press-on heat sink such as the Burr-Brown model
807HS (TO-99 metal package) can reduce chip temperature
by approximately 15°C, lowering the IB to one-third its
warmed-up value. The 807HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS for details.
takes approximately 500ns. When the output is driven into
the positive limit, recovery takes approximately 6µs. Output
recovery of the OPA627 can be improved using the output
clamp circuit shown in Figure 5. Diodes at the inverting
input prevent degradation of input bias current.
+VS
5kΩ
(2)
HP 5082-2811
Temperature rise in the plastic DIP and SOIC packages can
be minimized by soldering the device to the circuit board.
Wide copper traces will also help dissipate heat.
The OPA627/637 may also be operated at reduced power
supply voltage to minimize power dissipation and temperature rise. Using ±5V power supplies reduces power dissipation to one-third of that at ±15V. This reduces the IB of TO99 metal package devices to approximately one-fourth the
value at ±15V.
Diode Bridge
BB: PWS740-3
5kΩ
ZD1 : 10V IN961
1kΩ
RF
VI
–
RI
Leakage currents between printed circuit board traces can
easily exceed the input bias current of the OPA627/637. A
circuit board “guard” pattern (Figure 4) reduces leakage
effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same
potential, leakage current will flow harmlessly to the lowimpedance node. The case (TO-99 metal package only) is
internally connected to –VS.
–VS
VO
+
OPA627
Clamps output
at VO = ±11.5V
FIGURE 5. Clamp Circuit for Improved Overload Recovery.
CAPACITIVE LOADS
As with any high-speed op amp, best dynamic performance
can be achieved by minimizing the capacitive load. Since a
load capacitance presents a decreasing impedance at higher
frequency, a load capacitance which is easily driven by a
slow op amp can cause a high-speed op amp to perform
poorly. See the typical curves showing settling times as a
function of capacitive load. The lower bandwidth of the
OPA627 makes it the better choice for driving large capacitive loads. Figure 6 shows a circuit for driving very large
load capacitance. This circuit’s two-pole response can also
be used to sharply limit system bandwidth. This is often
useful in reducing the noise of systems which do not require
the full bandwidth of the OPA627.
Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and
circuit boards may be removed with cleaning solvents and
deionized water. Each rinsing operation should be followed
by a 30-minute bake at 85°C.
Many FET-input op amps exhibit large changes in input
bias current with changes in input voltage. Input stage
cascode circuitry makes the input bias current of the
OPA627/637 virtually constant with wide common-mode
voltage changes. This is ideal for accurate high inputimpedance buffer applications.
RF
1kΩ
PHASE-REVERSAL PROTECTION
The OPA627/637 has internal phase-reversal protection.
Many FET-input op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This
is most often encountered in non-inverting circuits when the
input is driven below –12V, causing the output to reverse
into the positive rail. The input circuitry of the OPA627/637
does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail.
200pF
CF
–
G = +1
BW ≥ 1MHz
RO
20Ω
+
G = 1+
RF
R1
Optional Gain
Gain > 1
OUTPUT OVERLOAD
When the inputs to the OPA627/637 are overdriven, the
output voltage of the OPA627/637 smoothly limits at approximately 2.5V from the positive and negative power
supplies. If driven to the negative swing limit, recovery
®
ZD1
CL
5nF
OPA627
R1
For Approximate Butterworth Response:
2 RO CL
RF >> RO
CF =
RF
f–3dB =
1
2π √ RF RO CF CL
FIGURE 6. Driving Large Capacitive Loads.
www.BDTIC.com/TI
OPA627, 637
10
INPUT PROTECTION
Sometimes input protection is required on I/V converters of
inverting amplifiers (Figure 7b). Although in normal operation, the voltage at the summing junction will be near zero
(equal to the offset voltage of the amplifier), large input
transients may cause this node to exceed 2V beyond the
power supplies. In this case, the summing junction should
be protected with diode clamps connected to ground. Even
with the low voltage present at the summing junction,
common signal diodes may have excessive leakage current.
Since the reverse voltage on these diodes is clamped, a
diode-connected signal transistor can be used as an inexpensive low leakage diode (Figure 7b).
The inputs of the OPA627/637 are protected for voltages
between +VS + 2V and –VS – 2V. If the input voltage can
exceed these limits, the amplifier should be protected. The
diode clamps shown in Figure 7a will prevent the input
voltage from exceeding one forward diode voltage drop
beyond the power supplies—well within the safe limits. If
the input source can deliver current in excess of the maximum forward current of the protection diodes, use a series
resistor, RS, to limit the current. Be aware that adding
resistance to the input will increase noise. The 4nV/√Hz
theoretical thermal noise of a 1kΩ resistor will add to the
4.5nV/√Hz noise of the OPA627/637 (by the square-root of
the sum of the squares), producing a total noise of 6nV/√Hz.
Resistors below 100Ω add negligible noise.
+VS
Leakage current in the protection diodes can increase the
total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the
1N4148 is approximately 25nA—more than a thousand
times larger than the input bias current of the OPA627/637.
Leakage current of these diodes is typically much lower and
may be adequate in many applications. Light falling on the
junction of the protection diodes can dramatically increase
leakage current, so common glass-packaged diodes should
be shielded from ambient light. Very low leakage can be
achieved by using a diode-connected FET as shown. The
2N4117A is specified at 1pA and its metal case shields the
junction from light.
–
VO
D
+
D
OPA627
D: IN4148 — 25nA Leakage
2N4117A — 1pA Leakage
Siliconix
Optional RS
–VS
=
(a)
IIN
–
VO
D
D
+
OPA627
D: 2N3904
=
(b)
NC
FIGURE 7. Input Protection Circuits.
SMALL SIGNAL RESPONSE
LARGE SIGNAL RESPONSE
(A)
(B)
FPO
When used as a unity-gain buffer, large common-mode input voltage steps
produce transient variations in input-stage currents. This causes the rising
edge to be slower and falling edges to be faster than nominal slew rates
observed in higher-gain circuits.
G=1
–
+
OPA627
FIGURE 8. OPA627 Dynamic Performance, G = +1.
www.BDTIC.com/TI
11
OPA627, 637
®
LARGE SIGNAL RESPONSE
+10
0
VOUT (V)
VOUT (V)
+10
(C)
–10
0
(D)
–10
6pF(1)
NOTE: (1) Optimum value will
depend on circuit board layout and stray capacitance at
the inverting input.
When driven with a very fast input step (left), common-mode
transients cause a slight variation in input stage currents which
will reduce output slew rate. If the input step slew rate is reduced
(right), output slew rate will increase slightly.
2kΩ
G = –1
–
2kΩ
VOUT
+
OPA627
FIGURE 9. OPA627 Dynamic Performance, G = –1.
OPA637
LARGE SIGNAL RESPONSE
OPA637
SMALL SIGNAL RESPONSE
+100
0
VOUT (mV)
VOUT (V)
+10
(E)
0
(F)
FPO
–100
–10
4pF(1)
2kΩ
G=5
–
+
OPA637
VOUT
500Ω
NOTE: (1) Optimum value will depend on circuit
board layout and capacitance at inverting input.
FIGURE 10. OPA637 Dynamic Response, G = 5.
®
www.BDTIC.com/TI
OPA627, 637
12
Error Out
/
RI
2kΩ
CF
HP50822835
RI , R 1
CF
Error Band
(0.01%)
2kΩ
OPA627
OPA637
2kΩ
6pF
±0.5mV
500Ω
4pF
±0.2mV
+15V
RI
High Quality
Pulse Generator
–
51Ω
NOTE: CF is selected for best settling time performance
depending on test fixture layout. Once optimum value is
determined, a fixed capacitor may be used.
±5V
Out
+
–15V
FIGURE 11. Settling Time and Slew Rate Test Circuit.
–In
+
–
Gain = 100
CMRR ≈ 116dB
Bandwidth ≈ 1MHz
OPA637
RF
5kΩ
2
Input Common-Mode
Range = ±5V
RG
101Ω
25kΩ
25kΩ
INA105
Differential
Amplifier
3pF
–
3
–
+In
+
RF
5kΩ
5
Output
6
+
25kΩ
25kΩ
1
OPA637
Differential Voltage Gain = 1 + 2RF /RG
FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100.
–In
+
–
Gain = 1000
CMRR ≈ 116dB
Bandwidth ≈ 400kHz
OPA637
RF
5kΩ
2
Input Common-Mode
Range = ±10V
RG
101Ω
10kΩ
INA106
Differential
Amplifier
3pF
3
–
+In
+
RF
5kΩ
100kΩ
5
–
6
Output
+
10kΩ
100kΩ
1
OPA637
Differential Voltage Gain = (1 + 2RF /RG) • 10
FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000.
This composite amplifier uses the OPA603 current-feedback op amp to
provide extended bandwidth and slew rate at high closed-loop gain. The
feedback loop is closed around the composite amp, preserving the
precision input characteristics of the OPA627/637. Use separate power
supply bypass capacitors for each op amp.
R2
–
A1
VI
+
*Minimize capacitance at this node.
VO
+
–
OPA603
R1
R3
*
RL ≥ 150Ω
for ±10V Out
R4
GAIN
(V/V)
A1
OP AMP
R1
(Ω)
R2
(kΩ)
R3
(Ω)
R4
(kΩ)
–3dB
(MHz)
SLEW RATE
(V/µs)
100
1000
OPA627
OPA637
50.5(1)
49.9
4.99
4.99
20
12
1
1
15
11
700
500
NOTE: (1) Closest 1/2% value.
FIGURE 14. Composite Amplifier for Wide Bandwidth.
www.BDTIC.com/TI
13
OPA627, 637
®
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA627AM
NRND
TO-99
LMC
8
20
Green (RoHS &
no Sb/Br)
AU
Lead/Ball Finish
MSL Peak Temp (3)
N / A for Pkg Type
OPA627AP
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA627APG4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA627AU
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA627AU/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA627AU/2K5E4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA627AUE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA627AUG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA627BM
NRND
TO-99
LMC
8
1
Green (RoHS &
no Sb/Br)
AU
N / A for Pkg Type
OPA627BP
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA627BPG4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA627SM
NRND
TO-99
LMC
8
20
Green (RoHS &
no Sb/Br)
AU
N / A for Pkg Type
OPA637AM
NRND
TO-99
LMC
8
20
Green (RoHS &
no Sb/Br)
AU
N / A for Pkg Type
OPA637AM2
OBSOLETE
TO-99
LMC
8
TBD
Call TI
Call TI
OPA637AP
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA637APG4
ACTIVE
PDIP
P
8
50
TBD
Call TI
Call TI
OPA637AU
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA637AU/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA637AU/2K5E4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
OPA637AUE4
OBSOLETE
SOIC
D
8
OPA637AUG4
ACTIVE
SOIC
D
8
OPA637BM
NRND
TO-99
LMC
8
OPA637BM1
OBSOLETE
TO-99
LMC
8
OPA637BP
ACTIVE
PDIP
P
8
50
OPA637BPG4
ACTIVE
PDIP
P
8
OPA637SM
NRND
TO-99
LMC
8
TBD
Call TI
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
20
Green (RoHS &
no Sb/Br)
AU
TBD
Call TI
Call TI
TBD
Call TI
Call TI
50
TBD
Call TI
Call TI
20
Green (RoHS &
no Sb/Br)
AU
(1)
Call TI
Level-3-260C-168 HR
N / A for Pkg Type
N / A for Pkg Type
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
www.BDTIC.com/TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2010
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
www.BDTIC.com/TI
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA627AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA637AU/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
www.BDTIC.com/TI
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA627AU/2K5
SOIC
D
8
2500
346.0
346.0
29.0
OPA637AU/2K5
SOIC
D
8
2500
346.0
346.0
29.0
www.BDTIC.com/TI
Pack Materials-Page 2
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
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