MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface General Description

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Download MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface General Description

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MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface General Description

19-4126; Rev 1; 2/09
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
The MAX1377/MAX1379/MAX1383 feature two simultaneous-sampling, low-power, 12-bit ADCs with serial
interface and internal voltage reference. Fast sampling
rate, low power dissipation, and excellent dynamic performance make the MAX1377/MAX1379/MAX1383
ideal for industrial process control, motor control, and
RF applications.
Conversion results are available through a SPI™-/
QSPI™-/MICROWIRE™-/DSP-compatible interface with
independent serial digital outputs for each channel. The
serial outputs allow twice as much data to be transferred
at the given clock rate. The conversion results for both
ADCs can also be output on a single digital output for
microcontrollers (µCs) and DSPs with only a single serial
input available.
The MAX1377 operates from a 2.7V to 3.6V analog supply and the MAX1379/MAX1383 operate from a 4.75V
to 5.25V analog supply. A separate 1.8V to AVDD digital supply allows interfacing to low voltage logic without
the use of level translators.
Two power-down modes, partial and full, allow the
MAX1377/MAX1379 and MAX1383 (full power-down only)
to save power between conversions. Partial power-down
mode reduces the supply current to 2mA while leaving
the reference enabled for quick power-up. Full powerdown mode reduces the supply current to 1µA.
The MAX1377/MAX1379 inputs accept voltages
between zero and the reference voltage or ±VREF/2.
The MAX1383 offers an input voltage range of ±10V,
which is ideal for industrial and motor-control applications. The input to each of the ADCs supports either a
true-differential input or two single-ended inputs.
The MAX1377/MAX1379/MAX1383 are available in a
20-pin TQFN package, and are specified for the automotive (-40°C to +125°C) temperature range.
Features
♦ Dual, Simultaneous-Sampling, 12-Bit Successive
Approximation Register (SAR) ADCs
♦ 2 x 2 Mux Inputs or Two Differential Inputs
♦ 1.25Msps Sampling Rate per ADC
♦ Internal or External Reference
♦ Excellent Dynamic Performance
70dB SINAD (MAX1377)
71dB SINAD (MAX1379/MAX1383)
84dBc/SFDR
1MHz Full-Linear Bandwidth
♦ 2.7V to 3.6V Low-Power Operation (MAX1377)
50mW (Normal Operation)
6mW (Partial Power-Down)
3µW (Full Power-Down)
♦ 4.75V to 5.25V Low-Power Operation (MAX1379)
90mW (Normal Operation)
10mW (Partial Power-Down)
5µW (Full Power-Down)
♦ 4.75V to 5.25V Low-Power Operation (MAX1383)
280mW (Normal Operation)
2.5µW (Full Power-Down)
♦ 20MHz, SPI-Compatible, 3-Wire Serial Interface
User-Selectable Single (0.625Msps max) or Dual
Outputs (1.25Msps max)
♦ Input Range: ±10V (MAX1383), 0–VREF or
±VREF/2 (MAX1377/MAX1379)
♦ Small 20-Pin TQFN Package
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Functional Diagram
VL
AVDD
AIN1A
AIN1B
12-BIT
SAR
ADC1
T/H
MUX
MAX1377
MAX1379
MAX1383
OUTPUT
BUFFER
Applications
CS
REF
Motor Control
Communications
Data Acquisition
Bill Validation
Portable Instruments
SERIAL
INTERFACE
AND TIMING
REFSEL
INTERNAL
REFERENCE
RGND
TEMP RANGE
MAX1377ATP+
-40°C to +125°C
PIN-PACKAGE
-40°C to +125°C
20 TQFN-EP*
MAX1383ATP+
-40°C to +125°C
20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SCLK
U/B
CONTROL
LOGIC
S/D
VL
AIN2A
MUX
20 TQFN-EP*
MAX1379ATP+
CNVST
A=1
Ordering Information
PART
DOUT1
12-BIT
SAR
ADC2
T/H
AIN2B
SEL
AGND
OUTPUT
BUFFER
DOUT2
DGND
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
www.BDTIC.com/maxim
MAX1377/MAX1379/MAX1383
General Description
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V
VL to DGND ..............................................................-0.3V to +6V
SCLK, CS, CNVST, U/B, S/D, SEL,
REFSEL to DGND.......................................-0.3V to (VL + 0.3V)
DOUT_ to DGND...........................................-0.3V to (VL + 0.3V)
AIN1A, AIN1B, AIN2A, AIN2B to AGND
MAX1377/MAX1379 .............................-0.3V to (AVDD + 0.3V)
MAX1383 ..............................................................-12V to +12V
RGND to AGND.....................................................-0.3V to +0.3V
RGND to DGND.....................................................-0.3V to +0.3V
DGND to AGND.....................................................-0.3V to +0.3V
Maximum Current into Any Pin (except power-supply pins).....50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin Thin QFN (derate 34.5mW/°C above +70°C) ...2758.6mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1377
(VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF =
1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Relative Accuracy
INL
Differential Nonlinearity
DNL
(Note 1)
Bits
-1.25
+1.25
LSB
-1
+1.5
LSB
±8
LSB
Offset Error
Offset-Error Matching
Gain Error
(Note 2)
Gain-Error Matching
(Note 2)
±12
LSB
±6
LSB
±6
Gain Temperature Coefficient
DC Input Isolation
AIN1A to AIN1B, AIN2A to AIN2B
80
AIN1A to AIN2A, AIN1B to AIN2B
80
LSB
ppm/oC
±2
dB
DYNAMIC SPECIFICATIONS (fIN = 500kHz, 2VP-P sine wave, 1.25Msps, 20MHz fSCLK)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
Unipolar
66
69.5
Bipolar
67
70
Unipolar
66
70
Bipolar
67
70
Up to the 5th harmonic
fIN1 = 103.5kHz, fIN2 = 113.5kHz
dB
dB
-84
-74
dB
-86
-76
dB
-78
dB
Full-Power Bandwidth
-3dB point
5
MHz
Full-Linear Bandwidth
(S/N + D) > 68dB, 1V input
1
MHz
CONVERSION RATE (Figure 4)
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate for
Full Bandwidth Signal
2
tCONV
16 clock cycles per conversion (Note 3)
0.800
Dual output mode, S/D = 0
1.25
Single output mode, S/D = 1
0.625
(Note 4)
10
_______________________________________________________________________________________
www.BDTIC.com/maxim
µs
Msps
ksps
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
(VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF =
1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Track-and-Hold Acquisition Time
tACQ
CONDITIONS
MIN
TYP
MAX
UNITS
125
ns
Aperture Delay
2
ns
Aperture-Delay Matching
2
ns
Aperture Jitter
(Note 5)
External Clock Frequency
30
ps
fSCLK
20
MHz
VREF
V
ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)
Input Range
U/B = 0, VAIN_A - RGND
Differential Input Range
U/B = 1, VAIN_A - VAIN_B
Absolute Voltage Range
0
-VREF/2
0
+VREF/2
V
AVDD
V
DC Leakage Current
±1
Input Impedance
Input Capacitance
At each analog input
µA
34
kΩ
16
pF
EXTERNAL REFERENCE (REFSEL = 1)
Absolute Input Voltage Range
VREF
1.0
Input Capacitance
AVDD
+ 0.05
V
±1
µA
50
pF
DC Leakage Current
Input Current
Time averaged at maximum throughput rate
800
µA
INTERNAL REFERENCE (REFSEL = 0)
Reference Voltage Level
2.028
Load Regulation
2.048
ISOURCE = 0 to 1mA
1
ISINK = 0 to 50µA
1
Voltage Temperature Coefficient
2.068
V
mV/mA
ppm/oC
±50.0
DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)
Input-Voltage Low
VIL
Input-Voltage High
VIH
Input Leakage Current
IIL
0.3 x
VL
0.7 x
VL
V
V
±10
µA
30
pF
0.4
V
DIGITAL OUTPUT (DOUT1, DOUT2)
Output Load Capacitance
Output-Voltage Low
CDOUT
VOL
For stated timing performance
ISINK = 5mA
Output-Voltage High
VOH
ISOURCE = 1mA, VL ≥ 2.7V
Output Leakage Current
IOL
High-impedance mode (Figure 9)
VL
- 0.5V
V
±0.2
µA
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
2.7
Digital Supply Voltage
VL
1.8
3.0
3.6
V
AVDD
V
_______________________________________________________________________________________
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3
MAX1377/MAX1379/MAX1383
ELECTRICAL CHARACTERISTICS—MAX1377 (continued)
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX1377 (continued)
(VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF =
1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Analog Supply Current
SYMBOL
IAVDD
CONDITIONS
MIN
TYP
MAX
Normal operation
13
15
Partial power-down mode (Note 5)
2
Full power-down mode (Note 5)
1
Average Static Supply Current
Digital Supply Current
Power-Supply Rejection
IVL
PSR
fSCLK = 20MHz, VL = 3V, CL = 30pF
VAVDD = 3V ±10%, full-scale input
UNITS
mA
5
µA
8
10
mA
1
1.5
mA
±0.2
±3
mV
ELECTRICAL CHARACTERISTICS—MAX1379
(VAVDD = 4.75V to 5.25V, VL = 3V, fSCLK = 20MHz (50% duty cycle), VREF = 4.096V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA =
TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-1.25
+1.25
LSB
-1
+1
LSB
Offset Error
±8
LSB
Offset-Error Matching
±9
LSB
±6
LSB
DC ACCURACY
Resolution
12
Relative Accuracy
INL
Differential Nonlinearity
DNL
(Note 1)
Gain Error
(Note 2)
Gain-Error Matching
(Note 2)
Bits
±9
Gain Temperature Coefficient
DC Input Isolation
AIN1A to AIN1B, AIN2A to AIN2B
80
AIN1A to AIN2A, AIN1B to AIN2B
80
LSB
ppm/oC
±2
dB
DYNAMIC SPECIFICATIONS (fIN = 500kHz , 4VP-P sine wave, 1.25Msps, 20MHz fSCLK)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
Unipolar
69
70
Bipolar
70
71
Unipolar
70
71
Bipolar
70
72
Up to the 5th harmonic
fIN1 = 103.5kHz, fIN2 = 113.5kHz
dB
dB
-84
-76
dB
-84
-76
dB
-78
dB
Full-Power Bandwidth
-3dB point
5
MHz
Full-Linear Bandwidth
(S/N + D) > 68dB, 1V input
1
MHz
CONVERSION RATE (Figure 6)
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate for
Full Bandwidth Signal
4
tCONV
16 clock cycles per conversion (Note 3)
0.8
Dual-output mode, S/D = 0
1.25
Single-output mode, S/D = 1
0.625
(Note 4)
10
_______________________________________________________________________________________
www.BDTIC.com/maxim
µs
Msps
ksps
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
(VAVDD = 4.75V to 5.25V, VL = 3V, fSCLK = 20MHz (50% duty cycle), VREF = 4.096V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA =
TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Track-and-Hold Acquisition Time
tACQ
CONDITIONS
MIN
TYP
MAX
UNITS
125
ns
Aperture Delay
2
ns
Aperture-Delay Matching
2
ns
30
ps
Aperture Jitter
(Note 5)
External Clock Frequency
fSCLK
20
MHz
ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)
Input Range
U/B = 0, VAIN_A - RGND
0
VREF
Differential Input Range
U/B = 1, VAIN_A - VAIN_B
-VREF/2
+VREF/2
0
AVDD
Absolute Voltage Range
DC Leakage Current
±1
Input Impedance
Input Capcitance
At each analog input
V
V
µA
34
kΩ
16
pF
EXTERNAL REFERENCE (REFSEL = 1)
Absolute Input Voltage Range
VREF
AVDD
+ 0.05
1.0
Input Capacitance
50
pF
DC Leakage Current
±1
Input Current
Time averaged at maximum throughput rate
V
800
µA
µA
INTERNAL REFERENCE (REFSEL = 0)
Reference Voltage Level
4.086
Load Regulation
4.096
ISOURCE = 0 to 1mA
1
ISINK = 0 to 50µA
1
Voltage Temperature Coefficient
4.106
V
mV/mA
ppm/oC
±50.0
DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)
Input-Voltage Low
VIL
Input-Voltage High
VIH
Input Leakage Current
IIL
0.3 x
VL
0.7 x
VL
V
V
±10
µA
30
pF
0.4
V
DIGITAL OUTPUT (DOUT1, DOUT2)
Output Load Capacitance
Output-Voltage Low
CDOUT
VOL
For stated timing performance
ISINK = 5mA
Output-Voltage High
VOH
ISOURCE = 1mA, VL ≥ 2.7V
Output Leakage Current
IOL
High-impedance mode (Figure 9)
VL 0.5V
V
±0.2
µA
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
4.25
Digital Supply Voltage
VL
1.8
5.0
5.25
V
AVDD
V
_______________________________________________________________________________________
www.BDTIC.com/maxim
5
MAX1377/MAX1379/MAX1383
ELECTRICAL CHARACTERISTICS—MAX1379 (continued)
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX1379 (continued)
(VAVDD = 4.75V to 5.25V, VL = 3V, fSCLK = 20MHz (50% duty cycle), VREF = 4.096V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA =
TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Analog Supply Current
SYMBOL
IAVDD
CONDITIONS
MIN
TYP
MAX
Normal operation
16
18
Partial power-down mode (Note 5)
2
Full power-down mode (Note 5)
Average Static Supply Current
Digital Supply Current
Power-Supply Rejection
IVL
PSR
µA
mA
9
10
2
3
fSCLK = 20MHz, VL = 3V, CL = 30pF
1
±0.2
mA
5
fSCLK = 20MHz, VL = 5V, CL = 30pF
VAVDD = 5V ±10%, full-scale input
UNITS
±3
mA
mV
ELECTRICAL CHARACTERISTICS—MAX1383
(VAVDD = 4.75V to 5.25V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.50V, REFSEL = VL, S/D = DGND, CREF =
1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-1.5
+1.5
LSB
-1
+1.5
LSB
DC ACCURACY
Resolution
12
Relative Accuracy
INL
Differential Nonlinearity
DNL
Offset Error
(Note 1)
Bits
Unipolar
±12
Bipolar
±16
Offset-Error Matching
Gain Error
(Note 2)
Gain-Error Matching
(Note 2)
±10
LSB
±8
LSB
±6
Gain Temperature Coefficient
AIN1A to AIN1B, AIN2A to AIN2B
74
AIN1A to AIN2A, AIN1B to AIN2B
80
LSB
ppm/oC
±2
DC Input Isolation
LSB
dB
DYNAMIC SPECIFICATIONS (fIN = 100kHz, 20VP-P sine wave, 1.25Msps, 20MHz fSCLK)
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Unipolar
67
71
Bipolar
69
72
Unipolar
67
71
Bipolar
69
72
Up to the 5th harmonic
dB
dB
-84
-72
-86
-72
dB
dB
fIN1 = 103.5kHz, fIN2 = 113.5kHz
-78
dB
Full-Power Bandwidth
-3dB point
10
MHz
Full-Linear Bandwidth
(S/N + D) > 68dB, 1V input
1
MHz
Intermodulation Distortion
IMD
CONVERSION RATE (Figure 4)
Minimum Conversion Time
Maximum Throughput Rate
6
tCONV
16 clock cycles per conversion (Note 3)
0.800
Dual output mode, S/D = 0
1.25
Single output mode, S/D = 1
0.625
_______________________________________________________________________________________
www.BDTIC.com/maxim
µs
Msps
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
(VAVDD = 4.75V to 5.25V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.50V, REFSEL = VL, S/D = DGND, CREF =
1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Minimum Throughput Rate for
Full Bandwidth Signal
CONDITIONS
(Note 4)
Track-and-Hold Acquisition Time
MIN
TYP
MAX
10
tACQ
UNITS
ksps
125
ns
Aperture Delay
2
ns
Aperture-Delay Matching
2
ns
30
ps
Aperture Jitter
(Note 5)
External Clock Frequency
fSCLK
20
MHz
+10
V
ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)
Input Range
U/B = 0, VAIN_A - RGND
Differential Input Range
U/B = 1, VAIN_A - VAIN_B
Absolute Voltage Range
-10
-10
+10
V
-10
+10
V
Input Impedance
Input Capacitance
At each analog input
10
kΩ
10
pF
EXTERNAL REFERENCE (REFSEL = 1)
Absolute Input Voltage Range
VREF
1.25
Input Capacitance
Input Current
Time averaged at maximum throughput rate
2.5
V
50
pF
1600
µA
INTERNAL REFERENCE (REFSEL = 0)
Reference Voltage Level
2.48
Load Regulation
2.50
ISOURCE = 0 to 1mA
1
ISINK = 0 to 50µA
1
Voltage Temperature Coefficient
2.52
V
mV/mA
ppm/oC
±50.0
DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)
Input-Voltage Low
VIL
Input-Voltage High
VIH
Input Leakage Current
IIL
0.3 x VL
V
±10
µA
0.7 x VL
V
DIGITAL OUTPUTS (DOUT1, DOUT2)
Output Load Capacitance
For stated timing performance
30
pF
Output-Voltage Low
CDOUT
VOL
ISINK = 5mA
0.4
V
Output-Voltage High
VOH
ISOURCE = 1mA, VL ≥ 2.7V
Output Leakage Current
IOL
High-impedance mode (Figure 9)
VL - 0.5V
V
±0.2
µA
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
Digital Supply Voltage
VL
Analog Supply Current
IAVDD
4.75
1.8
Power-Supply Rejection
IVL
PSR
5.25
V
AVDD
V
Normal operation
55
65
mA
Full power-down mode (Note 5)
0.5
10
µA
44
58
mA
2
3.0
mA
±5
±30
mV
Average Static Supply Current
Digital Supply Current
5.0
fSCLK = 20MHz, VL = 3V, CL = 30pF
VAVDD = 5V ±10%, full-scale input
_______________________________________________________________________________________
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7
MAX1377/MAX1379/MAX1383
ELECTRICAL CHARACTERISTICS—MAX1383 (continued)
TIMING CHARACTERISTICS (Figures 6, 10)
VAVDD = 4.25V to 5.25V, VL = 1.8V to AVDD, VREF = 4.096V, fSCLK = 20MHz for MAX1379, 50% duty cycle, CL = 30pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
SCLK Clock Period
CONDITIONS
MIN
TYP
tCP
50
tCH/tCL
45
SCLK Pulse-Width High
tCH
22.5
SCLK Pulse-Width Low
tCL
22.5
SCLK Duty Cycle
SCLK Rise to DOUT_ Transition
tDOUT
DOUT_ Remains Valid After
SCLK
tDHOLD
CNVST Fall to SCLK Fall
tSETUP
CNVST Pulse Width
SEL to CNVST Fall
MAX
ns
%
ns
ns
14
CL = 30pF, VL = 3V
17
CL = 30pF, VL = 1.8V
24
CL = 30pF
UNITS
55
CL = 30pF, VL = 5V
tCSW
Power-Up Time; Full Power-Down
ns
4
ns
10
ns
20
tPWR-UP
ns
External load on REF < 3µF
tSEL_SETUP
100
SEL Hold to CNVST Fall
2
ms
120
ns
10
ns
CS Fall To CNVST Fall
tCST
External load on REF < 3µF
2
ms
Restart Time; Partial Power-Down
tRCV
No external load
16
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: Offset nulled.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period. Clock has 50% duty cycle.
Note 4: At sample rates below 10ksps, the input full linear bandwidth is reduced to 5kHz.
Note 5: SCLK and CNVST not switching during measurement.
Typical Operating Characteristics
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
-80
-100
-60
-80
100
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
600
-60
-80
-120
-120
0
-40
-100
-100
-120
8
-40
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 500kHz
SINAD = 68.542dB
SNR = 68.554dB
THD = -90.391dB
SFDR = 94.350dB
VREF = 2.048V
-20
AMPLITUDE (dB)
-60
AMPLITUDE (dB)
-40
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 250kHz
SINAD = 68.720dB
SNR = 68.769dB
THD = -88.244dB
SFDR = 91.237dB
VREF = 2.048V
-20
0
MAX1377 toc02
MAX1377 toc01
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 100kHz
SINAD = 60.052dB
SNR = 69.073dB
THD = -92.267dB
SFDR = 93.225dB
VREF = 2.048V
-20
MAX1377 BIPOLAR FFT
MAX1377 BIPOLAR FFT
0
MAX1377 toc03
MAX1377 BIPOLAR FFT
0
AMPLITUDE (dB)
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
0
100
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
600
0
100
200
300
400
500
ANALOG INPUT FREQUENCY (kHz)
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600
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
MAX1377 UNIPOLAR FFT
-80
-60
-100
-100
100
200
300
400
500
300
400
500
600
0
0.8
0.6
0.2
INL (LSB)
0.4
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
-1.0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
MAX1377 BIPOLAR DNL
vs. DIGITAL OUTPUT CODE
MAX1379 UNIPOLAR INL
vs. DIGITAL OUTPUT CODE
MAX1379 BIPOLAR INL
vs. DIGITAL OUTPUT CODE
0.8
0.6
1.0
MAX1377 toc11
1.0
MAX1377 toc10
1.0
0.8
0.6
0.8
0.6
0.4
0.2
0.2
0.2
INL (LSB)
0.4
INL (LSB)
0.4
0
0
0
-0.2
-0.2
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
-1.0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
600
0
-0.4
0
500
0.6
0.2
500 1000 1500 2000 2500 3000 3500 4000 4500
400
0.8
0.2
0
300
1.0
0.4
-0.2
200
MAX1377 UNIPOLAR INL
vs. DIGITAL OUTPUT CODE
0.4
0
100
ANALOG INPUT FREQUENCY (kHz)
MAX1377 toc08
MAX1377 toc07
1.0
INL (LSB)
DNL (LSB)
0.6
200
MAX1377 BIPOLAR INL
vs. DIGITAL OUTPUT CODE
MAX1377 UNIPOLAR DNL
vs. DIGITAL OUTPUT CODE
0.8
100
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
1.0
-80
-120
0
600
-60
0
1024
2048
3072
DIGITAL OUTPUT CODE
4096
MAX1377 toc12
0
-40
-100
-120
-120
DNL (LSB)
MAX1377 toc05
-80
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 500kHz
SINAD = 68.645dB
SNR = 68.715dB
THD = -83.617dB
SFDR = 88.709dB
VREF = 2.048V
-20
MAX1377 toc09
-60
-40
0
AMPLITUDE (dB)
-40
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 250kHz
SINAD = 68.947dB
SNR = 69.054dB
THD = -85.101dB
SFDR = 86.718dB
VREF = 2.048V
-20
AMPLITUDE (dB)
AMPLITUDE (dB)
MAX1377 toc04
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 100kHz
SINAD = 69.324dB
SNR = 69.400dB
THD = -86.952dB
SFDR = 89.213dB
VREF = 2.048V
-20
MAX1377 UNIPOLAR FFT
0
MAX1377 toc06
MAX1377 UNIPOLAR FFT
0
0
1024
2048
3072
4096
DIGITAL OUTPUT CODE
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9
MAX1377/MAX1379/MAX1383
Typical Operating Characteristics (continued)
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
MAX1379 BIPOLAR DNL
vs. DIGITAL OUTPUT CODE
0.8
0.6
0.2
0.2
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
2048
3072
0
4096
MAX1379 GAIN ERROR
vs. TEMPERATURE
3072
4096
-40
1.2
CHANNEL 1
0.8
0.4
-40
-60
35
60
-80
85
fSAMPLE = 1.8Msps
fSCLK = 28.8MHz
fIN = 250kHz
SINAD = 70.05dB
SNR = 70.32dB
THD = -82.35dB
SFDR = 83.22dB
VREF = 4.096V
-20
-40
-60
-80
-120
300
600
900
0
300
600
900
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
MAX1379 FFT PLOT
MAX1379 FFT PLOT
MAX1379 TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDENCE
-60
-80
-100
MAX1377 toc20
fSAMPLE = 1.8Msps
fSCLK = 28.8MHz
fIN = 500kHz
SINAD = 69.58dB
SNR = 69.75dB
THD = -83.79dB
SFDR = 84.69dB
VREF = 4.096V
-40
-60
-80
-100
-120
-120
200
400
600
ANALOG INPUT FREQUENCY (kHz)
800
-72
TOTAL HARMONIC DISTORTION (dBc)
-40
-20
AMPLITUDE (dB)
-20
0
MAX1377 toc19
fSAMPLE = 1.8Msps
fSCLK = 28.8MHz
fIN = 300kHz
SINAD = 70dB
SNR = 70.27dB
THD = -82.2dB
SFDR = 81.81dB
VREF = 4.096V
-74
fIN = 500kHz
MAX1377 toc21
TEMPERATURE (°C)
0
0
60
-100
0
85
35
MAX1379 FFT PLOT
-120
10
10
0
-100
0
-15
TEMPERATURE (°C)
fSAMPLE = 1.8Msps
fSCLK = 28.8MHz
fIN = 100kHz
SINAD = 70.43dB
SNR = 70.72dB
THD = -82.33dB
SFDR = 82.78dB
VREF = 4.096V
-20
AMPLITUDE (dB)
1.6
GAIN ERROR (LSB)
2048
0
MAX1377 toc16
CHANNEL 2
10
1024
MAX1379 FFT PLOT
2.0
-15
CHANNEL 2
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
-40
CHANNEL 1
-0.9
-1.5
AMPLITUDE (dB)
1024
-0.6
-1.2
MAX1377 toc17
0
-0.3
MAX1377 toc18
0.4
DNL (LSB)
0.4
OFFSET ERROR (LSB)
0.6
0
MAX1377 toc14
0.8
DNL (LSB)
1.0
MAX1377 toc13
1.0
MAX1379 OFFSET ERROR
vs. TEMPERATURE
MAX1377 toc15
MAX1379 UNIPOLAR DNL
vs. DIGITAL OUTPUT CODE
AMPLITUDE (dB)
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
-76
-78
-80
-82
fIN = 100kHz
-84
-86
0
300
600
ANALOG INPUT FREQUENCY (kHz)
900
10
100
SOURCE IMPEDANCE (Ω)
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1000
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
MAX1379 AVDD FULL POWER-DOWN
CURRENT vs. TEMPERATURE
0.8
AVDD FULL POWER-DOWN CURRENT (mA)
0.9
0.7
0.6
-60
0.5
0.4
-80
0.3
0.2
-100
0.1
-120
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0
300
600
900
-40 -25 -10
ANALOG INPUT FREQUENCY (kHz)
5
20
35
50
65
-40 -25 -10
80
13.0
12.5
12.0
11.5
11.0
35
50
65
80
MAX1377 toc26
20
18
AVDD SUPPLY CURRENT (mA)
13.5
20
MAX1379 AVDD SUPPLY CURRENT
vs. CONVERSION RATE
MAX1377 toc25
14.0
5
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX1379 AVDD SUPPLY CURRENT
vs. TEMPERATURE
10.5
16
14
12
10
8
6
4
2
10.0
0
-40 -25 -10
5
20
35
50
65
80
0
400
800
1200
1600
2000
TEMPERATURE (°C)
CONVERSION RATE (kHz)
MAX1379 FULL-SCALE AMPLITUDE
vs. FREQUENCY
MAX1379 INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
4.10
MAX1377 toc27
3850
3800
MAX1377 toc28
AVDD SUPPLY CURRENT (mA)
4.09
4.08
TA = +25°C
4.07
3750
VREF (V)
0
OUTPUT SWING (LSB)
AMPLITUDE (dB)
-40
4.0
MAX1377 toc23
fSAMPLE = 1.8Msps
fSCLK = 28.8MHz
fIN1 = 250kHz
fIN1 = 300kHz
IMD = -81.53dB
VREF = 4.096V
-20
1.0
MAX1377 toc22
0
MAX1379 AVDD PARTIAL POWER-DOWN
CURRENT vs. TEMPERATURE
MAX1377 toc24
MAX1379 INTERMODULATION PLOT
3700
3650
4.06
4.05
TA = -40°C
4.04
4.03
TA = +85°C
3600
4.02
4.01
3550
1
10
FREQUENCY (MHz)
4.20
4.45
4.70
4.95
5.20
AVDD (V)
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11
MAX1377/MAX1379/MAX1383
Typical Operating Characteristics (continued)
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
0.8
0.6
0.8
0.6
0.4
0.2
0.2
0.2
-0.2
INL (LSB)
0.4
DNL (LSB)
0.4
0
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
-1.0
1024
2048
3072
0
4096
1024
2048
3072
0
4096
1024
2048
3072
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
MAX1383 UNIPOLAR DNL
vs. DIGITAL OUTPUT CODE
MAX1383 OFFSET ERROR
vs. TEMPERATURE
MAX1383 GAIN ERROR
vs. TEMPERATURE
8
OFFSET ERROR (LSB)
0.6
CHANNEL 1
0.4
0.2
0
-0.2
-0.4
-0.6
4
2
GAIN ERROR (LSB)
0.8
4096
MAX1377 toc34
10
MAX1377 toc32
1.0
MAX1377 toc33
0
MAX1377 toc31
0.6
1.0
MAX1377 toc30
0.8
INL (LSB)
1.0
MAX1377 toc29
1.0
DNL (LSB)
MAX1383 UNIPOLAR INL
vs. DIGITAL OUTPUT CODE
MAX1383 BIPOLAR DNL
vs. DIGITAL OUTPUT CODE
MAX1383 BIPOLAR INL
vs. DIGITAL OUTPUT CODE
6
CHANNEL 2
4
CHANNEL 2
0
CHANNEL 1
-2
2
-0.8
-4
0
1024
2048
3072
4096
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
-40
-60
-80
-100
-120
-87.5
-88.0
-88.5
-89.0
-89.5
fIN = 100kHz
fSAMPLE = 1.25Msps
125
250
375
500
ANALOG INPUT FREQUENCY (kHz)
625
2000
1800
1600
1400
1200
1000
800
600
400
200
0
-90.0
0
12
MAX1377 toc36
-20
-87.0
TOTAL HARMONIC DISTORTION (dBc)
fSAMPLE = 1.25Msps
fSCLK = 20MHz
fIN = 100kHz
SINAD = 70.07dB
SNR = 70.15dB
THD = -87.39dB
SFDR = 90.1dB
VREF = 2.5V
MAX1377 toc35
0
MAX1383 AVDD FULL POWER-DOWN
CURRENT vs. TEMPERATURE
MAX1383 TOTAL HARMONIC DISTORTION
vs. SOURCE IMPEDANCE
MAX1383 FFT PLOT
AVDD FULL POWER-DOWN CURRENT (nA)
0
MAX1377 toc37
-1.0
AMPLITUDE (dB)
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
0
100
200
300
SOURCE IMPEDANCE (Ω)
400
500
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
CONVERTING AT 1.25Msps
50
48
STATIC
46
42
54
53
52
50
-1
-2
500
1000
1500
2000
10
CONVERSION RATE (kHz)
FREQUENCY (MHz)
MAX1383 AVDD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1383 AVDD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1383 INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
50
CONVERTING AT 1.25Msps
48
STATIC
46
44
50
CONVERTING AT 1.25Msps
48
46
STATIC
44
4.65
4.85
5.05
5.25
TEMPERATURE AT TA = -40°C
2.494
TEMPERATURE AT TA = +85°C
2.493
2.492
2.491
40
4.45
TEMPERATURE AT TA = +25°C
2.495
42
40
2.496
MAX1377 toc43
52
42
2.497
MAX1377 toc42
EXTERNAL REFERENCE
VREFIO (V)
52
54
AVDD SUPPLY CURRENT (mA)
MAX1377 toc41
INTERNAL REFERENCE
4.25
1
TEMPERATURE (°C)
56
54
-3
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE AT TA = +125°C
2.490
4.25
4.45
4.65
4.85
5.05
5.25
4.75
4.85
4.95
5.05
5.15
5.25
VCC (V)
VCC (V)
VCC (V)
MAX1383 INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1383 EXTERNAL REFERENCE SUPPLY
CURRENT vs. TEMPERATURE
MAX1383 DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
VAVDD = 5V
1.47
IEXREFIO (µA)
2.497
2.495
2.493
1.70
MAX1377 toc46
1.48
MAX1377 toc44
2.499
1.68
1.46
IDVDD (mA)
AVDD SUPPLY CURRENT (mA)
MAX1377 toc39
55
51
44
VREFIO (V)
0
OUTPUT SWING (dB)
52
MAX1383 FULL-SCALE AMPLITUDE
vs. FREQUENCY
MAX1377 toc45
AVDD SUPPLY CURRENT (mA)
54
56
AVDD SUPPLY CURRENT (mA)
MAX1383 toc38
56
MAX1383 AVDD SUPPLY CURRENT
vs. CONVERSION RATE
MAX1377 toc40
MAX1383 AVDD SUPPLY CURRENT
vs. TEMPERATURE
1.45
1.66
1.64
1.44
2.491
1.62
1.43
2.489
1.60
1.42
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
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13
MAX1377/MAX1379/MAX1383
Typical Operating Characteristics (continued)
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
MAX1377/MAX1379/MAX1383
Pin Description
14
PIN
NAME
FUNCTION
1
REFSEL
2
REF
Internal Reference Output/External Reference Input. For internal reference mode, bypass REF to
RGND with a ≥ 1µF capacitor. For external reference mode, apply a reference voltage at REF.
3
RGND
Reference Ground/Common Negative Input. In bipolar mode, RGND is the reference ground. In
unipolar mode, RGND is the common negative input for all four analog inputs (see Figure 3).
4, 18
AGND
Analog Ground
5
AVDD
Analog-Supply Input. Bypass AVDD with a 10µF || 10nF capacitor to ground.
6
AIN2A
Primary/Positive Analog Input Channel 2. AIN2A is the primary channel 2 input (AIN2A) if using
single-ended inputs (U/B is low) and the positive channel 2 input (AIN2+) if using differential inputs
(U/B is high) (see Figure 3).
7
AIN2B
Secondary/Negative Analog Input Channel 2. AIN2B is the secondary channel 2 input (AIN2B) if
using single-ended inputs (U/B is low) and the negative channel 2 input (AIN2-) if using differential
inputs (U/B is high) (see Figure 3).
8
U/B
Reference-Select Input. Drive REFSEL high to select external reference mode and power down the
internal reference. Drive REFSEL low to select internal reference mode.
Unipolar/Bipolar Input. Drive U/B low to select unipolar mode. Drive U/B high to select bipolar
mode. In bipolar mode, the analog inputs are differential.
9
DGND
10
VL
Digital Supply Ground
11
DOUT2
Serial-Data Output 2. Data is clocked out on the rising edge of SCLK.
12
DOUT1
Serial-Data Output 1. Data is clocked out on the rising edge of SCLK.
13
SCLK
Serial-Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion time.
14
CNVST
Conversion-Start Input. Forcing CNVST high prepares the device for a conversion. Conversion
begins on the falling edge of CNVST.
15
CS
Active-Low, Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT1
and DOUT2 are high impedance, the serial interface resets, and the device powers down.
16
S/D
Single-Output/Dual-Output Selection Input. Drive S/D high to route ADC2 data through DOUT1 after
ADC1 data. Drive S/D low for dual outputs with ADC1 data going to DOUT1 and ADC2 data going
to DOUT2. See the Single-/Dual-Output Modes (S/D) section.
17
SEL
Analog-Input Selection Input. If U/B is low (unipolar mode), drive SEL low to select the primary
inputs, AIN1A and AIN2A. Drive SEL high to select the secondary inputs, AIN1B and AIN2B. In
bipolar mode, SEL is ignored.
19
AIN1B
Secondary/Negative Analog Input Channel 1. AIN1B is the secondary channel 1 input (AIN1B) if
using single-ended inputs (U/B is low) and the negative channel 1 input (AIN1-) if using differential
inputs (U/B is high) (see Figure 3).
20
AIN1A
Primary/Positive Analog Input Channel 1. AIN1A is the primary channel 1 input (AIN1A) if using
single-ended inputs (U/B is low) and the positive channel 1 input (AIN1+) if using differential inputs
(U/B is high) (see Figure 3).
—
EP
Digital Supply Input. Bypass VL with a 10µF || 10nF capacitor to ground.
Exposed Pad. EP is internally connected to AGND.
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
The MAX1377/MAX1379/MAX1383 use an input track
and hold (T/H) and SAR circuitry to convert an analog
input signal to a digital 12-bit output. The dual serial
interface requires a minimum of three digital lines
(SCLK, CNVST, and DOUT) and provides easy interfacing to microprocessors (µPs) and DSPs. Four digital
lines are required for dual-output mode.
Input T/H Circuit
Upon power-up, the input T/H circuit enters its tracking
mode immediately. Following a conversion, the T/H
enters the tracking mode on the 14th SCLK rising edge
of the previous conversion (Figure 6). The T/H enters the
hold mode on the falling edge of CNVST. The time
required for the T/H to acquire an input signal is determined by how quickly the input capacitance is charged.
If the input signal’s source impedance is high, the acquisition time lengthens. For the MAX1377/MAX1379, the
acquisition time, tACQ, is the minimum time needed for
the signal to be acquired (see the Definitions section).
tACQ is calculated by the following equation:
tACQ ≥ 9 x (RS + RIN) x CIN (MAX1377/MAX1379)
where RIN = 450Ω, CIN = 16pF, and RS is the source
impedance of the input signal.
Figure 1 shows the acquisition time as tested using the
circuit of Figure 2. The acquisition time is the time
between the rising edge of a 1V to 3V step input and
the falling edge of CONVST which produced a stable
sample. Rs represents the source impedance of the
function generator (50Ω) and Rx represents the variable filter resistance.
For the MAX1383, tACQ has a typical constant value of
125ns. Also, it has a typical constant input impedance
of 11kΩ. Since the input voltage seen at the pin is a
function of a resistive voltage divider i.e., VIN x RIN/(RIN
+ RX) = VIN x 11kΩ/(11kΩ + RX), it is very important to
select an RX << 11kΩ to avoid large gain error.
MAX1377/MAX1379 Unipolar Mode
The MAX1377/MAX1379 support two simultaneously
sampled, single-ended conversions in unipolar mode.
Drive U/B low for unipolar mode. In unipolar mode,
switches A–D in Figure 3a close according to the position of SEL. Drive SEL low to close switches A and D
and designate AIN1A and AIN2A as the active, singleended inputs referenced to RGND. Drive SEL high to
close switches B and D and select AIN1B and AIN2B
as the active, single-ended inputs referenced to RGND.
The output code in unipolar mode is straight binary.
See Figure 4a for the unipolar transfer function.
MAX1377/MAX1379 Bipolar Mode
Drive U/B high to configure the inputs for bipolar/differential mode. Switches A and C in Figure 3a are closed,
designating AIN1A (AIN2A) and AIN1B (AIN2B) as the
active, differential inputs. In bipolar mode, SEL is
ignored. The output code is in two’s complement.
Figure 5 shows the transfer function for bipolar mode.
MAX1383 Input Mode
A ±10V input mode is available on the MAX1383. It is
accomplished by utilizing a resistive divider on the
input followed by a low distortion amplifier to drive the
track and hold circuit. Special high voltage ESD structures are also utilized on these channels. When using
Rs
MAX1377 fig01
1800
ACQUISITION TIME (ns)
1600
Rx
ADC
1V TO 3V
STEP
C
CONVST
1400
1200
1000
C = 1nF
800
Figure 2. Test Circuit
600
400
C = 120pF
AIN1A
(AIN2A)
200
0
0
50
100
150
200
AIN1B
(AIN2B)
RGND
CIN
RIN
TO ADC+
B
C
SOURCE IMPEDANCE, Rx (Ω)
Figure 1. MAX1377/MAX1379 Acquisition Time vs. Source
Impedance
A
CIN
RIN
TO ADC-
D
Figure 3a. MAX1377/MAX1379 Equivalent Input Circuit
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15
MAX1377/MAX1379/MAX1383
Detailed Description
the MAX1383, the signal bandwidth is limited to 100kHz
by specification. Since ±10V signals are divided down to
a 2.5V range, this version should only be used with signals greater than 5V. For those applications with signals
5V or less, use the MAX1377/MAX1379 for best SNR performance. The configuration is shown on Figure 3b.
Input Bandwidth
The ADC’s input-tracking circuitry has a 5MHz smallsignal bandwidth, allowing the ADC to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
±10V input swings. All inputs must not exceed the stated ranges for accurate conversions.
Internal Reference Mode
Drive REFSEL low to select internal reference mode. The
MAX1377 includes an on-chip 2.048V reference; the
MAX1379 has a 4.096V reference; and the MAX1383
includes a 2.5V internal reference. The reference output
at REF can be used as a reference voltage source for
other components. REF can source up to 2mA. Bypass
REF with a 10nF capacitor and a 4.7µF capacitor to
RGND. It is important to select a low ESR capacitor and
keep the trace resistance as low as possible.
Analog Input Protection
REF (2.5V)
R2
RIN ~ 11KΩ (typ) R1
INPUT
FULL-SCALE
TRANSITION
MAX1383
+FS = 4VREF
111...111
111...110
ZS = 0
111...101
-FS = -4VREF
8 x VREF
1 LSB =
4096
DIGITAL OUTPUT CODE
Internal protection diodes that clamp the analog input
to AVDD and AGND allow the analog inputs to swing
from AGND - 0.3V to AVDD + 0.3V without damage to
the MAX1377 and MAX1379. The MAX1383 can handle
000...011
R4
INA
000...010
3pF
R3
000...001
T/H
000...000
-FS
INTERNAL
SIGNAL
GROUND
VREF - 1 LSB
+FS
+FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 4b. MAX1383 Single-Ended Input
Figure 3b. MAX1383 Equivalent Input Circuit
FULL-SCALE
TRANSITION
FULL-SCALE
TRANSITION
MAX1377/
MAX1379
011...111
111...111
111...101
FS = VREF
011...100
ZS = 0
V
1 LSB = REF
4096
000...010
DIGITAL OUTPUT CODE
111...110
DIGITAL OUTPUT CODE
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
VREF
2
ZS = 0
-VREF
-FS =
2
V
1 LSB = REF
4096
+FS =
000...001
000...000
111...111
MAX1383
111...110
+FS = 4VREF
ZS = 0
-FS = -4VREF
8 x VREF
1 LSB =
4096
111...101
000...011
000...010
100...001
000...001
100...000
000...000
0
1
2
3
INPUT VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 4a. MAX1377/MAX1379 Unipolar Transfer Function (U/B
= Low)
16
-FS
VREF - 1 LSB
DIFFERENTIAL INPUT VOLTAGE (LSB)
+FS
+FS - 3/2 LSB
Figure 5. Bipolar Transfer Function (U/B = High)
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
Initialization After Power-Up
Upon initial power-up, the MAX1377/MAX1379/ MAX1383
require a complete conversion cycle to initialize the internal calibration. Following this initialization, the ADC is
ready for normal operation. This initialization is only
required after a hardware power-on reset and is not
required after exiting partial or full power-down mode.
Input Voltage Range (MAX1383)
The input range on the MAX1383 has an 8x relationship
with the reference voltage. For example, when the reference voltage (internal or external) is 2.5V, the input
range is ±10V (20VP-P).
Starting a Conversion and Reading the Output
With SCLK idling high or low, a falling edge on CNVST
begins a conversion (see Figure 6). This causes the
analog input stage to transition from track to hold
mode. SCLK provides the timing for the conversion
process, and data is shifted out as each bit of the result
is determined. A rising edge in CNVST forces the
device into one of three modes. The mode is determined by the clock cycle in which the transition occurs
and whether the device is set for single or dual outputs.
Figures 7 and 8 show each mode that is activated with
a rising CNVST edge for single and dual outputs.
External Reference Mode
Drive REFSEL high to select external reference mode.
Apply a reference voltage at REF. Bypass REF with
a 10nF capacitor and a 4.7µF capacitor to RGND. As
with the internal reference, it is important to select a low
ESR capacitor and keep the trace resistance as low
as possible.
CS
tCSW
CNVST
tSETUP
tCH
13
1
SCLK
tCL
tCST
14
tACQ
tDOUT
D11
DOUT_
D10
D9
D8
D7
D6
D5
D4
D3
D2
D0
D1
tDHOLD
INTERNAL T/H STATE
TRACKING
HOLD MODE
Figure 6. Detailed Serial-Interface Timing Diagram
CS
CNVST
POWER-DOWN
CONTINUOUS MODE
DOUT1 HI-Z
DOUT1 GOES HI-Z
SCLK
1
2
3
4
14
28
29
Figure 7. Single-Output CNVST Transition Modes
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17
MAX1377/MAX1379/MAX1383
Serial Interface
The internal reference is continuously powered-up during both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Allow at least 2ms recovery time after a power-on reset
or exiting full power-down mode for the reference to
settle to its intended value.
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
CS
CNVST
POWER-DOWN
1
SCLK
3
2
4
CONTINUOUS MODE
16
15
14
DOUT_ HI-Z
17
DOUT_ HI-Z
Figure 8. Dual-Output CNVST Transition Modes
SINGLE CONVERSION
CNVST
8
1
SCLK
0
DOUT_
0
0
D11
D10
D9
16
9
D4
D5
D6
D7
D8
D3
D2
D1
D0
HIGH-Z
HIGH-Z
CONTINUOUS-CONVERSION
SELECTION WINDOW*
CONTINUOUS CONVERSION
CNVST
SCLK
DOUT_
8
1
0
0
0
D11
D10
D9
D8
14
9
D7
D6
D5
D4
D3
D2
16
D1
1
D0
*CNVST MUST GO HIGH BETWEEN THE 14TH RISING AND 16TH FALLING EDGES OF SCLK.
TO MAINTAIN CONTINUOUS CONVERSIONS, DOUT_ REMAINS LOW BETWEEN
CONVERSION RESULTS IN CONTINUOUS-CONVERSION DUAL-OUTPUT MODE.
Figure 9. Dual-Output Mode, Single and Continuous Conversions
DOUT1 (and DOUT2, if S/D = low) transitions from high
impedance to being actively driven low once the ADC
enters hold mode. DOUT_ remains low for the first three
SCLK pulses and begins outputting the conversion result
after the 4th rising edge of SCLK, MSB first. DOUT_ transitions complete tDOUT after each SCLK rising edge and
the DOUT_ values remain valid for tHOLD after the next
rising edge of SCLK. A total of 16 SCLK pulses are
required to complete a normal conversion in dual-output
mode and 28 SCLK pulses in single-output mode.
DOUT_ goes low after the 16th rising edge of SCLK and
goes high-impedance when CNVST goes high.
18
For continuous operation in single-output mode, pull
CNVST high after the 14th rising and before the 28th
rising edge of SCLK. In dual-output mode, if CNVST
returns high after the 14th rising and before the 16th
falling edge of SCLK, DOUT_ remains active so continuous conversions can be sustained. If CNVST is low
during the 16th edge of SCLK (dual-conversion mode)
and the 28th falling edge of SCLK (single-output mode),
DOUT_ returns to its high-impedance state on the next
rising edge of CNVST or SCLK, enabling the serial interface to be shared by multiple devices. See Figures 9
and 10 for single and continuous conversion timing
diagrams.
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
Partial Power-Down (PPD)
Reduce power consumption by placing the MAX1377/
MAX1379 in partial power-down mode. Partial powerdown mode is ideal for infrequent data sampling and
applications requiring fast wake-up times. Pull CNVST
high after the 3rd and before the 14th rising edge of
SCLK to place the device in partial power-down mode.
This reduces the analog supply current to 2mA. While
in partial power-down mode, the internal reference
remains enabled (if REFSEL = GND). Figure 11 shows
the timing sequence to enter partial power-down mode.
Full Power-Down Mode (FPD)
Full power-down mode is ideal for infrequent data sampling and very low-supply current applications. To enter
full power-down mode, place the MAX1377/MAX1379/
MAX1383 first in partial power-down mode. Perform the
CNVST/SCLK sequence necessary to enter partial
power-down mode. Repeat the same sequence to enter
full power-down mode. In full power-down mode, the
internal reference is disabled to minimize power consumption. Figure 12 shows the timing sequence to
enter full power-down mode.
Another way to enter the full power-down mode is to
drive CS high. If CS is high, the MAX1377/MAX1379/
MAX1383 act as if the full power-down sequence were
issued. To exit the CS-initiated power-down mode,
drive CS low. Allow 2ms for the reference to wake up
and settle before performing a conversion.
SINGLE CONVERSION
(SINGLE OUTPUT)
CNVST
SCLK
DOUT1
8
1
0
0
0
D11 D10 D9 D8
9
D7
16
D6 D5 D4 D3 D2 D1 D0
17
24
D11 D10 D9 D8
CHANNEL 1
CONVERSION RESULT
D7 D6 D5 D4
28
D3
D2 D1 D0
HIGH-Z
CHANNEL 2
CONVERSION RESULT
CONTINUOUS CONVERSION
(SINGLE OUTPUT)
CNVST
SCLK
DOUT1
8
1
0
0
0
D11 D10 D9 D8
9
14
D7 D6 D5 D4 D3 D2 D1 D0
CHANNEL 1
CONVERSION RESULT
16
17
24
D11 D10 D9 D8
D7 D6 D5 D4
CHANNEL 2
CONVERSION RESULT
25
D3
27
28
D2 D1 D0
Figure 10. Single-Output Mode, Single and Continuous Conversions
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19
MAX1377/MAX1379/MAX1383
Power-Down Modes
Single-/Dual-Output Modes (S/D)
In dual-output mode, conversion results from the two
channels appear on separate outputs. DOUT1 outputs
the result from channel 1 and DOUT2 outputs the result
from channel 2. Drive S/D low to operate in dual-output
mode. For DSPs with two-buffer and two-input-stream
capability, use the dual-output mode to allow for easier
DSP software for dual streams. Two buffer locations can
be used so the streams do not need to be separated.
In single-output mode, the results from both channels
appear on DOUT1. The channel 2 conversion result follows the channel 1 conversion result (see Figure 10).
The MSB (D11) of the channel 2 conversion result
appears on DOUT1 after the 16th rising edge of SCLK.
The LSB (D0) of the channel 2 conversion result
appears on DOUT1 after the 27th rising edge of SCLK
and is ready to be clocked in on the 28th rising edge of
SCLK. DOUT2 is high-impedance when S/D is high.
If CNVST goes high after the 28th rising edge of SCLK,
DOUT1 goes high impedance until the next conversion
is initiated (single-conversion mode). If CNVST goes
high after the 14th rising edge and before the 28th rising edge of SCLK, DOUT1 is actively driven low until
the next conversion results are ready (continuous- conversion mode).
Note: In single-output mode, the conversion speed is
limited to 0.625Msps by the maximum SCLK.
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
PPD WINDOW
CNVST
CNVST MUST GO HIGH AFTER THE 3RD
BUT BEFORE THE 14TH
SCLK RISING EDGE
SCLK
3
1
9
1ST SCLK RISING EDGE
0
DOUT_
0
0
MODE
14
DOUT_ GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
D11
D10
D9
D8
D7
NORMAL
PARTIAL POWER-DOWN
ENABLED
REF
Figure 11. Partial Power-Down Timing Sequence
EXECUTE PARTIAL POWER-DOWN SEQUENCE TWICE
CNVST
SCLK
1ST SCLK RISING EDGE
DOUT_
MODE
0
0
0
DOUT_ ENTERS THREE-STATE ONCE CNVST GOES HIGH
1ST SCLK RISING EDGE
D11
D10
D9
D8
D7
0
NORMAL
0
0
0
0
0
0
0
FPD
PPD
ENABLED
REF
DISABLED
Figure 12. Full Power-Down Mode Timing Sequence
Exiting Partial and Full Power-Down Modes
Drive CNVST low and allow at least 14 SCLK cycles to
elapse before driving CNVST high to exit partial or full
power-down mode. When exiting partial power-down
mode, conversions can begin immediately without having to wait for the reference to wake-up. When exiting
full power-down mode, allow at least 2ms recovery time
after exiting to ensure that the internal reference has
settled.
In partial or full power-down mode, maintain idle SCLK
low or high to minimize power.
20
Applications Information
SPI and MICROWIRE
The MAX1377/MAX1379/MAX1383 are compatible with
all four modes programmed with the CPHA and CPOL
bits in the SPI or MICROWIRE control register.
Conversion begins with a CNVST falling edge. DOUT_
goes low, indicating a conversion is in progress. Two
consecutive 8-bit reads are required to get the full 12
bits from the ADC. DOUT_ transitions on the rising edge
of SCLK. DOUT_ is guaranteed to be valid tDOUT after
the rising edge of SCLK and remains valid until tDHOLD
after the next SCLK rising edge (see Figure 13).
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
QSPI
Unlike SPI, which requires two 8-bit reads to acquire
the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the
data. The MAX1377/MAX1379/MAX1383 require 16
clock cycles from the µC to clock out the 12 bits of
data. The conversion result contains three zeros followed by the 12 data bits, and a trailing zero with the
data in the MSB-first format.
Three-Phase Motor Controller
The MAX1377/MAX1379/MAX1383 are ideally suited for
motor-control systems (Figure 16). The devices’ simultaneously sampled inputs eliminate the need for complicated DSP algorithms that realign sequentially sampled
data into a simultaneous sample set. The ±10V
(MAX1383) input allows for standard industrial inputs,
eliminating the need for voltage-scaling amplifiers.
CNVST
I/O
SCLK
tDOUT
tDHOLD
SCK
SCLK
MISO1
DOUT1
MISO2
DOUT2
3V TO 5V
MAX1377
MAX1379
MAX1383
DOUT_
SS
A) SPI
Figure 13. Data Valid and Hold Times
CNVST
CS
SCK
SCLK
MISO1
DOUT1
DOUT2
MISO2
3V TO 5V
SUPPLIES
ANALOG
SUPPLY
DIGITAL
SUPPLY
RETURN
RETURN
SS
OPTIONAL
FERRITE
BEAD
AVDD
MAX1377
MAX1379
MAX1383
B) QSPI
VL
AGND
MAX1377
MAX1379
MAX1383
DGND
VDD
GND
I/O
CNVST
SK
SCLK
SI1
DOUT1
SI2
DOUT2
MAX1377
MAX1379
MAX1383
DIGITAL
CIRCUITRY
C) MICROWIRE
Figure 14. Power-Supply Grounding and Bypassing
Figure 15. Common Serial-Interface Connections to the
MAX1377/MAX1379/MAX1383
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21
MAX1377/MAX1379/MAX1383
For CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA =
1, the data is clocked into the µC on the rising edge of
SCLK. For CPOL = 0 and CPHA = 1 or CPOL = 1 and
CPHA = 0, the data is clocked into the µC on the falling
edge of SCLK. The MAX1377/MAX1379/MAX1383 are
compatible with all CPOL/CPHA configurations since
the data is valid on the falling and rising edge of SCLK.
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
MAX1383
AIN1A
MISO1
12-BIT
ADC
T/H
MISO2
12-BIT
ADC
T/H
DSP-BASED DIGITAL
PROCESSING ENGINE
AIN1B
AIN2A
AIN2B
IGBT CURRENT DRIVERS
CURRENT
SENSORS
IPHASE2
IPHASE1
THREE-PHASE ELECTRIC MOTOR
PHASE 2
PHASE 1
PHASE 3
SIN/COS
POSITION
RESOLVER
IPHASE3 = - IPHASE1 - IPHASE2
Figure 16. Three-Phase Motor Control
22
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
AVDD
VL
MAX1377
I
QUADRATURE
DEMODULATOR Q
Establish a single-point analog ground (star ground point)
at AGND, separate from the digital ground, DGND.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. The ground return
to the power supply for this ground should be low impedance and as short as possible for noise-free operation.
See Figure 14.
High-frequency noise in the AVDD power supply affects
the ADC’s high-speed comparator. Bypass the supply
to the single-point analog ground with 0.01µF and 10µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection.
Definitions
Integral Nonlinearity
12-BIT
ADC
12-BIT
ADC
DSP
PROCESSING
T/R
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package.
VL
DAC
QUADRATURE
TRANSMITTER
DAC
Figure 17. Quadrature Wireless-Communication System
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analogto-digital noise is caused by quantization error, and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nulled. The static
linearity parameters for the MAX1377/MAX1379/
MAX1383 are measured using the end-points method.
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Differential Nonlinearity
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log(SignalRMS/NoiseRMS)
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB or less guarantees no
missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Signal-to-Noise Plus Distortion
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
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23
MAX1377/MAX1379/MAX1383
Wireless Communication
Use the MAX1377/MAX1379/MAX1383 in a variety of
wireless communication systems. These devices allow
precise, simultaneous sampling of the I and Q signals
of quadrature RF receiver systems. Figure 17 shows the
MAX1377 in a simplified quadrature system. The device
has a differential input option that allows either full differential or psuedo-differential signals. The 2:1 input
mux allows measurement of RSSI and other systemmonitoring functions with this device.
Intermodulation Distortion
zation noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
Any device with nonlinearities creates distortion products when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1
and f2. The individual input tone levels are at
-6dBFS.
⎛ SINAD − 1.76 ⎞
ENOB = ⎜
⎟
⎝
⎠
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
CNVST
SCLK
DOUT1
DOUT2
Pin Configuration
⎞
⎟
⎟
⎠
CS
⎛
V 22 + V 32 + V 4 2 + V 52
THD = 20 × log⎜
V1
⎜
⎝
15
14
13
12
11
TOP VIEW
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
S/D 16
SEL 17
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distortion component.
MAX1377
MAX1379
MAX1383
AGND 18
AIN1B 19
AIN1A 20
10
VL
9
DGND
8
U/B
7
AIN2B
6
AIN2A
(EXPOSED PAD)*
+
Full-Linear Bandwidth
4
5
AVDD
TQFN
*CONNECT PAD TO AGND
Full-linear bandwidth is the frequency at which the signal-to-noise plus distortion (SINAD) is equal to 56dB.
3
AGND
2
RGND
1
REF
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
REFSEL
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
Selector Guide
SUPPLY VOLTAGE (V)
INTERNAL
REFERENCE
VOLTAGE (V)
INPUT VOLTAGE
RANGE
SAMPLING RATE
(Msps)
MAX1377
2.7 to 3.6
2.048
0 to VREF, ±VREF/2
1.25
MAX1379
4.75 to 5.25
4.096
0 to VREF, ±VREF/2
1.25
MAX1383
4.75 to 5.25
2.5
±10V
1.25
PART
Package Information
Chip Information
PROCESS: BiCMOS
24
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 TQFN-EP
T2055-4
21-0140
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Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
7/08
Initial release of the MAX1377/MAX1379
—
1
2/09
Initial release of the MAX1383
—
DESCRIPTION
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
www.BDTIC.com/maxim
MAX1377/MAX1379/MAX1383
Revision History