P160 Communications Module User Guide

P160
Communications Module
User Guide
Version 2.0
December 2002
PN# DS-MANUAL-MBEXP1
Table of Contents
1
OVERVIEW ....................................................................................................................1
2
THE P160 COMMUNICATIONS MODULE BOARD .........................................................1
2.1
10/100 ETHERNET ....................................................................................................2
2.2
USB PORT ..............................................................................................................3
2.3
RS232 PORT...........................................................................................................3
2.4
I2C PORT................................................................................................................4
2.5
SPI PORT ...............................................................................................................4
2.6
FLASH AND SRAM ..................................................................................................4
2.7
PS/2 KEYBOARD INTERFACE ......................................................................................6
2.8
OPTIONAL LCD INTERFACE ........................................................................................7
2.9
COOL R UNNER CPLD ................................................................................................7
2.10
P160 COMMUNICATION M ODULE S IGNAL ASSIGNMENTS .................................................8
REVISION HISTORY............................................................................................................ 10
APPENDIX A - P1160 COMMUNICATION MODULE (REV 2) SCHEMATICS ......................... 11
December 1, 2002
i
Figures
FIGURE 1 – P160 COMMUNICATIONS MODULE B OARD ...................................................................1
FIGURE 2 – P160 COMMUNICATION MODULE BLOCK D IAGRAM........................................................2
FIGURE 3 – 10/100 ETHERNET INTERFACE ...................................................................................2
FIGURE 4 – USB INTERFACE ......................................................................................................3
FIGURE 5 – RS232 INTERFACE...................................................................................................4
FIGURE 6 – FLASH AND SRAM INTERFACE ...................................................................................5
December 1, 2002
ii
Tables
TABLE 1 – ETHERNET P IN ASSIGNMENTS .....................................................................................3
TABLE 2 – RS232 P IN ASSIGNMENTS ..........................................................................................4
TABLE 3 – I2C JP6 P IN ASSIGNMENTS ........................................................................................4
TABLE 4 – SPI JP4 PIN ASSIGNMENTS ........................................................................................4
TABLE 5 – FLASH/SRAM JX P IN ASSIGNMENTS ............................................................................5
TABLE 6 – K EYBOARD JP3 PIN ASSIGNMENTS ..............................................................................7
TABLE 7 – JP12 LCD CONNECTOR P IN ASSIGNMENTS ..................................................................7
TABLE 8 – C OOLR UNNER USER P IN ASSIGNMENTS ........................................................................7
TABLE 9 – JX1 USER I/O CONNECTOR ........................................................................................8
TABLE 10 – JX2 USER I/O CONNECTOR ......................................................................................9
December 1, 2002
iii
1
Overview
The P160 Communications Module provides a useful set of peripherals and memory banks in a
small, low cost daughter card form-factor, compatible with any main system board containing the
P160 expansion interface. The Spartan-II, Spartan-IIE, and Virtex-II system boards from Memec
Design all include the P160 interface and can support the P160 Communications Module. If you
are planning on using the P160 module with the Memec Design Virtex-II Pro board, you should
verify that you have a Rev 2 version of the P160 Communications module. The Rev 2 module
contains its own JTAG header and does not share the JTAG chain of the system board. Only the
Memec Design Virtex-II Pro board requires this due to a special 2.5V JTAG chain.
Proper user configuration of the main system board is required to enable the P160 interface and
the corresponding expansion module functions. This user guide helps provide the necessary
details to develop such a configuration. Complete board schematics are provided in Appendix A
for your reference.
2
The P160 Communications Module Board
The P160 Communications Module includes interfaces for USB, 10/100 Ethernet, RS-232, PS/2
Keyboard, I2C, SPI, and an LCD display. The module also contains both 2M x 32 Flash and
256K x 32 SRAM. Figure 1 shows the module and its corresponding components, while Figure 2
illustrates the functional block diagram.
Figure 1 – P160 Communications Module Board
December 1, 2002
1
LCD I/F
RS-232
10/100 PHY
SPI
Flash
USB
2Mx32
I/O Connectors
I/O Connectors
I2C
SRAM
PS/2
256K x 32
JTAG
Figure 2 – P160 Communication Module Block Diagram
2.1 10/100 Ethernet
The P160 Communications Module provides a 10/100 Ethernet PHY interface. The Broadcom
BCM5221 implements the PHY function while the 10/100 Ethernet core must reside on the main
system board, usually inside the FPGA device. The following figure shows a high-level block
diagram of the 10/100 interface on the P160 Communications Module.
Receive
clk_tx
TD+
TD-
control_tx
data_rx[3:0]
RD+
clk_rx
RD-
RJ45
Connector
data_tx[3:0]
10/100
Magnetics
I/O Module Connector
Transmit
BCM5221
10/100 PHY
control_rx
Crystal
25Mhz
phy_reset
LEDs
Figure 3 – 10/100 Ethernet Interface
December 1, 2002
2
Table 1 – Ethernet Pin Assignments
Signal Name
PHY_RESETn
ETH_MDIO
ETH_MDC
ETH_COL
ETH_CRS
ETH_TXD0
ETH_TXD1
ETH_TXD2
ETH_TXD3
ETH_TXEN
ETH_TXC
ETH_TXER
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RXDV
ETH_RXC
ETH_RXER
JX1 Pin #
B31
A13
B14
B24
B25
A21
B22
B23
A23
B21
A35
A19
B17
B16
A15
B15
A17
A33
B19
FPGA I/O/B
O
B
O
I
I
O
O
O
O
O
I
O
I
I
I
I
I
I
I
2.2 USB Port
The P160 Communications Module provides a USB transceiver interfac e that can be used for
USB end-point applications (USB master applications are not supported on this module). The
P160 module utilizes the Fairchild USB1T11A device to implement the transceiver function while
the USB core must reside in the FPGA on the main system board. Figure 4 shows a high-level
block diagram of the USB interface.
RCV
D+
+
-
VP
D-
VM
USB
Connector
I/O Module
Connector
USB1T11A
OE
VPO
VMO
USB_PWR
USB_GND
Figure 4 – USB Interface
2.3 RS232 Port
The P160 Communications Module provides a simple RS232 port. This board utilizes the TI
MAX3221 RS232 driver for driving the RD and TD signals. Figure 4 shows the RS232 interface.
December 1, 2002
3
JP5
RS232_TX
I/O Module
Connector
RS232_RX
Din
Rout
RS232
Drivers
MAX3221
RD
Dout
TD
Rin
2
3
Figure 5 – RS232 Interface
Table 2 – RS232 Pin Assignments
JX1 Pin #
B12
B13
Signal Name
RS232_TX
RS232_RX
JP5 Pin #
2
3
2.4 I2C Port
The P160 Communications Module provides one I2C port. Please refer to the P160 module
connector pin assignments and schematics for more information on these signals.
Table 3 – I2C JP6 Pin Assignments
JP6 Pin #
1
2
3
2.5
Signal Name
I2C_DATA
I2C-CLK
GND
SPI Port
The P160 Communications module provides one SPI port. Please refer to the P160 module
connector pin assignments and schematics for more information on these signals.
Table 4 – SPI JP4 Pin Assignments
JP4 Pin #
1
2
3
4
Signal Name
SPI_CLK
SPI_OUT
SPI_IN
GND
2.6 FLASH and SRAM
The P160 Communications Module provides 8MB of Flash (2M x 32). Two Toshiba
TH50VSF2581 devices (2M x 16 each) are used to achieve this density. In addition to the Flash,
these two devices provide 1MB of SRAM. The following figure shows the Flash/SRAM interface
on the I/O module.
December 1, 2002
4
Data[15:0]
Addr[22:0]
CE1Sn
CEFn
OEn
WEn
RDY
MEM_RESETn
BLBn
BUBn
Multi-Chip
256K x 16 SRAM
2M x 16 FLASH
(TH50VSF2581)
I/O
Connector
Data[31:16]
Multi-Chip
256K x 16 SRAM
2M x 16 FLASH
(TH50VSF2581)
ALBn
AUBn
Figure 6 – Flash and SRAM Interface
Table 5 – Flash/SRAM JX Pin Assignments
Signal Name
MEM_RESETn
MEM.RY/BY
MEM.AUBn
MEM.BUBn
MEM.ALBn
MEM.BLBn
MEM.WEn
MEM.OEn
MEM.CEFn
MEM.CE1Sn
MEM_DU
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
December 1, 2002
JX Pin #
JX1-B37
JX2-A39
JX1-A27
JX1-B27
JX1-A25
JX1-B26
JX2-A40
JX2-A19
JX2-B20
JX2-A20
JX1-B38
JX2-B32
JX2-A34
JX2-A35
JX2-B36
JX2-A33
JX2-A36
JX2-A37
JX2-A38
JX2-A1
JX2-A3
JX2-B6
JX2-B2
FPGA I/O/B
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
5
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
JX2-A4
JX2-A5
JX2-A8
JX2-B4
JX2-B8
JX2-B34
JX2-B38
JX2-A2
JX2-B40
JX2-A6
JX2-A7
JX2-A18
JX2-A21
JX2-A17
JX2-B14
JX2-A13
JX2-A14
JX2-A9
JX2-A11
JX2-B18
JX2-A16
JX2-B16
JX2-A15
JX2-A12
JX2-B10
JX2-B12
JX2-A10
JX2-B30
JX2-A32
JX2-B28
JX2-A27
JX2-B26
JX2-A26
JX2-A22
JX2-A23
JX2-A30
JX2-A31
JX2-A29
JX2-A28
JX2-A25
JX2-A24
JX2-B24
JX2-B22
O
O
O
O
O
O
O
O
O
O
O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2.7 PS/2 Keyboard Interface
The P160 module provides standard PS/2 keyboard connector (JP3) for connecting a PS/2
compatible keyboard. The signals present on JP3 are not driven directly from the P160
connectors JX1 and JX2. Instead, they are buffered through a Xilinx CoolRunner CPLD. The
CoolRunner device handles 3.3V to 5V level compatibility requirements for the keyboard signals.
As delivered, the CoolRunner is pre-programmed for a standard pass through connection mode.
December 1, 2002
6
Table 6 – Keyboard JP3 Pin Assignments
JP3 Pin #
1
2
3
4
5
6
7
8
9
Signal Name (at JX1/2))
PLD_KB_DATA
N/C
GND
5V
PLD_KB_CLK
N/C
GND
GND
GND
2.8 Optional LCD Interface
The P160 module provides a 2x7 I/O header (JP12) for an optional LCD connection (Seiko L1672
compatible with additional Samtec SSQ-107-01-F-D receptacle). The following table shows the
JP12 pin assignments for the LCD connection. It should be noted that R26 potentiometer located
on the I/O module is used to control the contrast of the LCD panel.
The signals present on JP12 are not driven directly from the P160 connectors JX1 and JX2.
Instead, they are buffered through a Xilinx CoolRunner CPLD. The CoolRunner device handles
3.3V to 5V level compatibility requirements for the LCD. As delivered, the CoolRunner is preprogrammed for a standard pass through connection mode. Also note that the LCD data signals
D0 through D7 going to the CPLDare shared with the Flash and SRAM memory.
Table 7 – JP12 LCD Connector Pin Assignments
Signal Name (at JX1/2)
D7
D5
D3
D1
PLD_LCD_EN
PLD_LCD_RS
GND
JP12 Pin #
1
3
5
7
9
11
13
2
4
6
8
10
12
14
Signal Name (at JX1/2)
D6
D4
D2
D0
PLD_LCD_R/Wn
Contrast Voltage
+5V
2.9 CoolRunner CPLD
A Xilinx CoolRunner CPLD is included as a buffering device between the module I/O and the LCD
and keyboard connectors. In addition, there are two user I/O signals and two clock signals that
connect between the JX1 connector and the CPLD. These signals are user defined and can be
used as needed.
Table 8 – CoolRunner User Pin Assignments
JX1 Pin #
A37
A39
B40
B39
December 1, 2002
JX1 Signal Name
USERIO_1
USERIO_2
PLD_CLK0
PLD_CLK2
CoolRunner Pin #
B10
F10
C5
C7
7
2.10 P160 Communication Module Signal Assignments
The following tables show the P160 connector pin assignments to the P160 Communication
Module connectors (JX1 & JX2).
Table 9 – JX1 User I/O Connector
I/O Module
Usage
NC
GND
NC
Vin
NC
GND
NC
3.3V
USB_VM
GND
USB_OEn
2.5V
ETH_MDIO
GND
ETH_RXD2
Vin
ETH_RXDV
GND
ETH_TXER
3.3V
ETH_TXD0
GND
ETH_TXD3
2.5V
MEM.ALBn
GND
MEM.AUBn
Vin
PLD_KB_DATA
GND
PLD_KB_CLK
3.3V
ETH_RXC
GND
ETH_TXC
2.5V
USER_IO_1
GND
USER_IO_2
Vin
December 1, 2002
I/O
Connector
Signal Name
NC
GND
NC
Vin
NC
GND
NC
3.3V
LIOA9
GND
LIOA11
2.5V
LIOA13
GND
LIOA15
Vin
LIOA17
GND
LIOA19
3.3V
LIOA21
GND
LIOA23
2.5V
LIOA25
GND
LIOA27
Vin
LIOA29
GND
LIOA31
3.3V
LIOA33
GND
LIOA35
2.5V
LIOA37
GND
LIOA39
Vin
JX1 Pin #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
I/O
Connector
Signal Name
FPGA.BITSTREAM
SM.DOUT/BUSY
FPGA.CCLK
DONE
INITn
PROGRAMn
NC
LIOB8
LIOB9
LIOB10
LIOB11
LIOB12
LIOB13
LIOB14
LIOB15
LIOB16
LIOB17
LIOB18
LIOB19
LIOB20
LIOB21
LIOB22
LIOB23
LIOB24
LIOB25
LIOB26
LIOB27
LIOB28
LIOB29
LIOB30
LIOB31
LIOB32
LIOB33
LIOB34
LIOB35
LIOB36
LIOB37
LIOB38
LIOB39
LIOB40
I/O Module
Usage
NC
NC
NC
NC
NC
NC
NC
USB_VPO
USB_VMO
USB_VP
USB_RCV
RS232_TX
RS232_RX
ETH_MDC
ETH_RXD3
ETH_RXD1
ETH_RXD0
NC
ETH_RXER
NC
ETH_TXEN
ETH_TXD1
ETH_TXD2
ETH_COL
ETH_CRS
MEM.BLBn
MEM.BUBn
PLD_LCD_EN
PLD_LCD_RS
PLD_LCD_R/WN
PHY_RESETn
I2C_DATA
I2C_CLK
SPI_OUT
SPI_IN
SPI_CLK
MEM_RESETn
MEM_DU
PLD_CLK2
PLD_CLK0
8
Table 10 – JX2 User I/O Connector
I/O Module
Usage
A8
A19
A9
A12
A13
A21
A22
A14
D6
D15
D7
D12
D4
D5
D11
D9
D2
D0
MEM.OEn
MEM.CE1Sn
D1
D22
D23
D29
D28
D21
D19
D27
D26
D24
D25
D17
A4
A1
A2
A5
A6
A7
MEM.RY/BY
MEM.WEn
December 1, 2002
I/O
Connector
Signal Name
RIOA1
RIOA2
RIOA3
RIOA4
RIOA5
RIOA6
RIOA7
RIOA8
RIOA9
RIOA10
RIOA11
RIOA12
RIOA13
RIOA14
RIOA15
RIOA16
RIOA17
RIOA18
RIOA19
RIOA20
RIOA21
RIOA22
RIOA23
RIOA24
RIOA25
RIOA26
RIOA27
RIOA28
RIOA29
RIOA30
RIOA31
RIOA32
RIOA33
RIOA34
RIOA35
RIOA36
RIOA37
RIOA38
RIOA39
RIOA40
JX2 Pin #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
I/O
Connector
Signal Name
GND
RIOB2
Vin
RIOB4
GND
RIOB6
3.3V
RIOB8
GND
RIOB10
2.5V
RIOB12
GND
RIOB14
Vin
RIOB16
GND
RIOB18
3.3V
RIOB20
GND
RIOB22
2.5V
RIOB24
GND
RIOB26
Vin
RIOB28
GND
RIOB30
3.3V
RIOB32
GND
RIOB34
2.5V
RIOB36
GND
RIOB38
Vin
RIOB40
I/O Module
Usage
GND
A11
Vin
A15
GND
A10
3.3V
A16
GND
D13
2.5V
D14
GND
D3
Vin
D10
GND
D8
3.3V
MEM.CEFn
GND
D31
2.5V
D30
GND
D20
Vin
D18
GND
D16
3.3V
A0
GND
A17
2.5V
A3
GND
A18
Vin
A20
9
Revision History
V1.0
Initial Release
2/13/02
V2.0
Rev 2 Board Release
Added Table 1 – Ethernet pin assignments
Added Table 2 – RS232 pin assignments
Added Table 5 – Flash/SRAM pin assignments
Removed User I/O 3 from Table 8
Removed JTAG signals from JX1 in Table 9
12/1/02
December 1, 2002
10
Appendix A
P160 Communication Module (Rev 2) Schematics
December 1, 2002
11
5
4
Ethernet PHY
3.3V
3
2
1
2.5V
JP1
1
3
NE1
2
SHUNT-LO-CL
1X3
2.5V
C6
C7
1nF
MII/RMII INTERFACE
RCVLEDn/ACTLEDn/MDIX_DIS/TDO
XMTLEDn/INTRn/FDXLEDn
LNKLEDn/MEDIA_CONVn/TDI
SDPLEDn/ADV_PAUSEn/TMS
DGND
DGND
DGND
DGND
RXER
RXC
RXDV
RXD0
RXD1
RXD2
RXD3
31
30
14
11
7
2.5V
41
42
61
62
ETH_TXD3
ETH_TXD2
ETH_TXD1
ETH_TXD0
ETH_TXEN
FB1
FB321611T-601Y-S
5V
R3
10k
1%
R4
10k
1%
C8
.1u
R5
1.5k
5%
R6
49.9
1%
R7
49.9
1%
JP3
KB_DATA
2
1
2
1
2
3
4
5
6
7
8
9
9
H1102
Pulse
2.5V
R8
75R
5%
KB_CLK
R9
75R
5%
FB3
C12
560pF
ETH_MDIO
C13
560pF
FB321611T-121Y-S
C11
1nF
2kV
C14
1nF
R10
KBDAT
TP095
KBSIGND
KB5V
KBCLK
TP096
KBSHGND
KBSHGND
KBSHGND
2MJ-0104A120
Mini DIN
6 pos
ETH_TXC
ETH_TXER
51
50
49
48
47
44
43
ETH_RXER
D
FB2
FB321611T-121Y-S
1
RJ45
ETH_MDC
ETH_COL
ETH_CRS
60
59
58
57
56
53
52
8
5V
1
2
3
4
5
6
7
8
3
6
26
25
10
. MEDIA
CONNECTIONS
AVDD
AVDD
BIASVDD
REGDVDD
REGAVDD
28
27
22
3
20
TXD3
TXD2
TXD1
TXD0
TXEN
TXC
TXER
LEDS
40
45
54
63
AGND
TD+
TDRD+
RD-
BCM5221KPT
DIGITAL
32
AGND
ANALOG GND
16
2
MDIO
MDC
COL
CRS/CRS_DV
BROADCOM
JP2
1
33R 5%
R11
ETH_RXC
FB4
ETH_RXDV
33R 5%
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
1
2.5V
2
FB321611T-601Y-S
Serial Peripheral
Interface (SPI)
33
34
35
36
RESETn
PHYAD0/FDX_LEDn
PHYAD1/COL_LEDn
PHYAD2/ACT_LEDn
PHYAD3/PAUSE
PHYAD4
TESTEN
LOW_PWR
ENERGY_DET
MII_EN
SDSD+
F100/TCK
ANEN/TRSTn
FDX
29
1
46
8
2
55
POWER
MODE
9
10
11
12
13
14
15
16
17
18
19
21
37
38
39
REF_CLK
XTALO
XTALI
XTALGND
RDAC
BIASGND
PHY_RESETn
JTAG_EN
CLOCK
4
5
6
7
DVDD
DVDD
64
5V
C5
1nF
U1
U2
C10
18pF
R2
49.9
1%
2
R1
49.9
1%
15
C4
.01u
1nF
C9
18pF
C3
.1u
OVDD
OVDD
OVDD/NC
D
C2
.1u
23
24
Y1
CM309B25.000MABJT
1
4
2
3
PS/2
Keyboard
Connector
2.5V
+
2.5V
1
C1
150u
2.5V
C
C
R13
R14
1.27k
1%
DS1 LST670-HK
3.3V
130
R15
4.7k
1%
1%
3.3V
100MB/s
R20
130
3.3V
DS2 LST670-HK
1%
R17
10k
1%
R18
10k
1%
R19
10k
1%
Link
R21
DS3 LST670-HK
FB5
FB321611T-121Y-S
SPI_CLK
1
2
1
2
JP4
1
130
Transmit Activity
SPI_OUT
2
FB6
FB321611T-121Y-S
1
SPI_IN
3.3V
U3
C19
.1u
C20
.1u
B
C21
.1u
C22
.1u
C18
1u
TEXAS
INSTRUMENTS
EN
C1+
V+
C1C2+
C2VRIN
FORCEOFF
VCC
GND
DOUT
FORCEON
DIN
INVALID
ROUT
C16
47pF
3
4
Header 1x4
0.1"
Spacing
C17
47pF
JP5
1
16
15
14
13
12
11
10
9
2
FB7
FB321611T-121Y-S
C15
47pF
2
3
4
RS232
1
2
3
4
5
6
7
8
1
1%
DCD
DSR
2
RD
RTS
3
TD
CTS
4
RS232_TX
5
RS232_RX
MAX3221
DTR
RI
6
7
8
9
GND
DB9-R
B
I2C
DB9 Connector
Female Right
Angle
3.3V
R22
10k
1%
FB8
FB321611T-121Y-S
1
I2C_DATA
Universal Serial Bus
2
C23
560pF
3.3V
3.3V
3.3V
JP6
R16
1.5k
5%
R12
1.5k
5%
1
R23
10k
1%
3.3V
2
2
3
1
I2C_CLK
C24
560pF
JP10
2
2
FB9
FB321611T-121Y-S
1
2
3
1X3
1x3 Header
0.1" Spacing
JP8
C25
.1u
U4
A
MODE
VCC
OE
VMO/FSEO
RCV
VPO
VP
D+
VM
DSUSPND
SPEED
GND
NC
USB1T11A
1X2
14
13
12
11
10
9
8
1X2
JP7
1
1
2
3
4
5
6
7
USB_VMO
USB_VPO
1
USB_OEn
USB_RCV
USB_VP
USB_VM
3.3V
1
2
3
4
5
VCC GND
DATADATA+
6
GND GND
897-30-004-90-000
USB B Style
Connector
A
R24
2
10k 1%
JP9
MicroBlaze Communications Board DS-BD-MBEXP1
1X2
SHUNT-LO-CL
NE3
SHUNT-LO-CL
External Interfaces
Last Modified
Thursday, September 19, 2002
Rev
Size
2
C
Designer
Sheet
Brian Dewald
1 of 3
Memec Board
1
NE2
Suite 540 1212 31 Ave NE
Calgary, Alberta
Canada
T2E 7S8
5
4
3
2
1
5
4
3
2
1
D
D
2.5V
5V
3.3V
3.3V
5V
2.5V
JX1
C
USB_VM
USB_OEn
ETH_MDIO
ETH_RXD2
ETH_RXDV
ETH_TXER
ETH_TXD0
ETH_TXD3
MEM.ALBn
MEM.AUBn
PLD_KB_DATA
PLD_KB_CLK
ETH_RXC
ETH_TXC
USERIO_1
USERIO_2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
TCK
GND
TMS
VIN
TDI
GND
TDO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
P160 Left Header DB
DIN
DOUT
CCLK
DONE
INITn
PROGRAMn
NC
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
JX2
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
USB_VPO
USB_VMO
USB_VP
USB_RCV
RS232_TX
RS232_RX
ETH_MDC
ETH_RXD3
ETH_RXD1
ETH_RXD0
ETH_RXER
ETH_TXEN
ETH_TXD1
ETH_TXD2
ETH_COL
ETH_CRS
MEM.BLBn
MEM.BUBn
PLD_LCD_EN
PLD_LCD_RS
PLD_LCD_R/Wn
PHY_RESETn
I2C_DATA
I2C_CLK
SPI_OUT
SPI_IN
SPI_CLK
MEM_RESETn
MEM_DU
PLD_CLK2
PLD_CLK0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A8
A19
A9
A12
A13
A21
A22
A14
D6
D15
D7
D12
D4
D5
D11
D9
D2
D0
MEM.OEn
MEM.CE1Sn
D1
D22
D23
D29
D28
D21
D19
D27
D26
D24
D25
D17
A4
A1
A2
A5
A6
A7
MEM.RY/BY
MEM.WEn
R44
10k
1%
P160 Right Header DB
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
A11
A15
C
A10
A16
D13
D14
D3
D10
D8
MEM.CEFn
D31
D30
D20
D18
D16
A0
A17
A3
A18
A20
B
B
Hirose
FX2C-80S-1.27DSAL
Hirose
FX2C-80S-1.27DSAL
LCD
Connector
5V
R29
10k
1%
5V
R31
10k
1%
5V
R33
10k
1%
5V
R35
10k
1%
5V
R37
10k
1%
5V
5V
R38
10k
1%
5V
R39
10k
1%
5V
R36
10k
1%
5V
R34
10k
1%
5V
R32
10k
1%
R30
10k
1%
JP12
LCD_D7
LCD_D5
LCD_D3
LCD_D1
LCD_EN
LCD_RS
1
2
3
4
5
6
7
8
9
10
11 12
13 14
2X7
0.1" straight
TH Receptacle
LCD_D6
LCD_D4
LCD_D2
LCD_D0
LCD_R/Wn
3.3V
R25
2.2k
5%
5V
3
C28
10u
A
A
Compatible LCD's:
HD-16216H-D Hantronics
L167200j000 Seiko
LCM-01602D-XX/C
Luminex
2
R26
500 pot
1
Contrast
Control
MicroBlaze Communications Board DS-BD-MBEXP1
Motherboard Connectors, LCD Connector & 5V Regulator
Last Modified
Thursday, September 19, 2002
Rev
Size
2
C
Designer
Sheet
Brian Dewald
2 of 3
Memec Board
Suite 540 1212 31 Ave NE
Calgary, Alberta
Canada
T2E 7S8
5
4
3
2
1
5
4
3
2
1
D
D
3.3V
3.3V
C29
.1u
J2
D6
H2
H3
C6
C4
D4
E5
D5
C5
K6
H9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3.3V
3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
3.3V
R45
10k
1%
R46
10k
1%
MEM.CE1Sn
MEM.CEFn
MEM.OEn
MEM.WEn
MEM.BLBn
MEM.BUBn
R27
10k
1%
MEM.RY/BY
MEM_RESETn
MEM_DU
G2
F2
E2
D2
F3
E3
D3
C3
C7
E7
F7
C8
D8
E8
F8
D9
G9
F4
E4
D7
E6
E9
F9
A1
A10
B1
B10
C1
F1
F10
G1
G10
L1
L10
M1
M10
G8
J5
J6
VCCf
VCCs
J5
J6
CE1S
CE2S
CEF
OE
WE
LB
UB
RY/BY
RESET
WP/ACC
CIOS
CIOF
J3
G4
K4
H5
H6
K7
G7
J8
K3
H4
J4
K5
J7
H7
K8
H8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
Toshiba
TH50VSF2581AASB
SRAM/FLASH
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CE1S
CE2S
CEF
OE
WE
LB
UB
RY/BY
RESET
WP/ACC
CIOS
CIOF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DU
J3
G4
K4
H5
H6
K7
G7
J8
K3
H4
J4
K5
J7
H7
K8
H8
J2
D6
H2
H3
C6
C4
D4
E5
D5
C5
K6
H9
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
3.3V
3.3V
R47
10k
1%
MEM.CE1Sn
MEM.CEFn
MEM.OEn
MEM.WEn
MEM.ALBn
MEM.AUBn
MEM.RY/BY
MEM_RESETn
R28
10k
1%
C
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DU
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U7
G3
J9
MEM_DU
A1
A10
B1
B10
C1
F1
F10
G1
G10
L1
L10
M1
M10
G8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
C32
.1u
G3
J9
C
G2
F2
E2
D2
F3
E3
D3
C3
C7
E7
F7
C8
D8
E8
F8
D9
G9
F4
E4
D7
E6
E9
F9
SRAM/FLASH
VCCf
VCCs
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
C31
.1u
Toshiba
TH50VSF2581AASB
GND
GND
U6
C30
.1u
B
B
3.3V
5V/3.3V
Level
Translator
3.3V
3.3V
C36
.1u
USERIO_2
LCD_D5
LCD_D7
LCD_D6
PLD_KB_CLK
PLD_KB_DATA
LCD_D4
LCD_D3
LCD_D2
LCD_D1
3.3V
J1
1
2
3
4
5
6
7
VCC
GND
NC
TCK
TDO
TDI
TMS
A
F10
C10
C1
G1
JTAG7
E1
Internal Connection Chart
Baseboard Signal
PLD_LCD_R/Wn
PLD_LCD_EN
PLD_LCD_RS
PLD_KB_CLK
D0 - D7
5
C4
C3
A1
B1
A2
A3
D1
D3
E3
F1
4
to
VCC
VCC
VCC
VCC
A0
A1
A3
A4
A5
A7
A9
A10
A13
A14
C35
.1u
D14
D12
D11
D10
D9
D8
D7
D4
D3
D1
B0
B1
B2
B4
B6
B7
B9
B10
B13
B14
C11
C10
C9
C8
C7
C6
C14
C3
C12
C1
TCK/C0
TDO/A8
TDI/B8
TMS/D0
PORT_EN
CLK3/IN3
CLK2/IN2
CLK1/IN1
CLK0/IN0
K6
GND
G10
A7 GND
GND
PLD_LCD_RS
USERIO_1
C8
A8
A9
A5
A10
B10
D8
E8
F8
E10
C34
.1u
H1
H5
D10
A4
C33
.1u
U8
PLD_LCD_R/Wn
PLD_LCD_EN
NOTE:
The bit stream for
the CPLD must have
JTAG enable set.
3.3V
K5
H4
H3
K3
K2
K4
K1
J1
G3
F3
H7
H8
J10
K9
K10
K8
K7
H10
H6
G8
A6
C7
C6
C5
D3
LCD_RS
D0
D2
D1
LCD_R/Wn
LCD_EN
LCD_D0
KB_DATA
D6
D7
D5
D4
KB_CLK
3.3V
3.3V
R40
10k
1%
3.3V
R41
1k
1%
3.3V
R42
10k
1%
R43
1k
1%
A
PLD_CLK2
Xilinx
PLD_CLK0
XCR3064XL-10CP56C
Module Signal
LCD_R/Wn
LCD_EN
LCD_RS
KB_CLK
LCD_D0 - LCD_D7
MicroBlaze Communications Board DS-BD-MBEXP1
Memory & CPLD Level Translator
Last Modified
Thursday, September 19, 2002
Rev
Size
2
C
Designer
Sheet
Brian Dewald
3 of 3
Memec Board
Suite 540 1212 31 Ave NE
Calgary, Alberta
Canada
T2E 7S8
3
2
1