L1 Calo Firmware Overview: Languages, Tools, Methods

L1 Calo Firmware Overview:
Languages, Tools, Methods
• Beginners Guide to…
– Languages
– The Design Flow & Associated Tools
– Version Management
• Breakdown of Languages
Languages, Tools & Methods by Institute
• Conclusions
26 March 2009
Ian Brawn
1
Languages
•
HDL: Hardware Description Language
•
VHDL Verilog,
VHDL,
V il
System
S
C….
C
•
Comparable to computer languages, except for concurrent nature
sig_A <= sig_B;
sig_B <= sig_C;
– sequential processes can be implemented (all processes run concurrently)
•
Used for:
– Synthesizable code (RTL = Resistor Transfer Level)
– High-level
g
behavioural descriptions
p
for simulation
•
Logic can be functionally correct but unsynthesizable
•
VHDL: many constructs and commands exist for simulation only
26 March 2009
Ian Brawn
2
Graphical Design Entry
HDL files
•
•
•
•
•
Entirely optional
Converts block diagrams, state machine diagrams, truth tables, flow charts → HDL
Manage files, navigate design hierarchy
Coupled to simulator
Documentation
26 March 2009
Ian Brawn
3
Simulation
•
Number of approaches to testing:
– Input test vectors by hand, via files, or from HDL test engines…
– Verify performance by
• Visual waveform inspection,
• Automated test benches – examine data and report errors
• Write data to files (+ test by external software)
26 March 2009
Ian Brawn
4
The Design Flow (1)
Graphics
Proprietary graphics files
HDL Generator
HDL
VHLD / Verilog
Simulation
Synthesis
Constraints
HDL + SDF
Gate-level
+ timing info
26 March 2009
Net list
Implementation
bit
Ian Brawn
machine (+ human) readable
net list e.g., EDIF
Proprietary vendor tools
Load to FPGA
5
The Design Flow (2)
Graphics
Proprietary graphics files
HDL Generator
HDL
VHLD / Verilog
Simulation
Synthesis
Constraints
HDL + SDF
Gate-level
+ timing info
26 March 2009
Net list
Implementation
bit
Ian Brawn
Proprietary net list, e.g. NGC
Proprietary vendor tools
Load to FPGA
6
The Design Flow (3)
Graphics
HDL Generator
HDL
Simulation
Synthesis
Constraints
HDL + SDF
Net list
Implementation
bit
26 March 2009
Ian Brawn
Proprietary vendor tools
Load to FPGA
7
Version Management / Archiving
Graphics
HDL Generator
HDL
Version Management /
Archiving
Simulation
Synthesis
• St
Stand-alone
d l
or iintegrated
t
t d with
ith
design tools
Constraints
HDL + SDF
Net list
Implementation
bit
26 March 2009
Ian Brawn
• Archiving
– Back-up
• Version Management
– Branching
– Access control for
multiple Users
8
Design Tools Used in L1 Calo
Graphical
Design Entry
Simulation
Synthesis
HDL Designer
Modelsim
Precision
Xilinx ISE
ISE/Modelsim
XST
ISE
Altera
Quartus II
AlteraModelsim
Quartus
Quartus
Mentor graphics
FPGAdvantage
26 March 2009
Ian Brawn
Implementation
9
Tools & Methods Spreadsheet (1)
Main
responsibilities
Language
B’ham
H’berg
Mainz
RAL
S’holm
CPM
PPR
JEM
CMM,,
ROD,
CPM
JEM
VHDL
Verilog
Vendor
Altera
Xilinx
Devices
FPGA
CPLD
Entry
HDL
HDL Designer
Synthesis
Precision
XST
Quartus
Implement
Quartus
ISE
26 March 2009
Ian Brawn
10
Tools & Methods Spreadsheet (2)
B’ham
Simulation
H’berg
Mainz
RAL
S’holm
Modelsim
ISE
Behavioural
Gate-level
high-level models
IP
Vendor
3rd Party
Tool Use
GUI
Scripting
Embedded
Archiving &
Version
Management
CVS
Synchronicity
Subversion
TAR/zip
Documentation
26 March 2009
Firmware
Designs
Ian Brawn
11
Conclusions
•
Language: VHDL / Verilog:
– tools can handle both in one design.
– So can designers, if they have to….
•
Front-end entry packages option
– Many advantages for design entry, organisation, navigation
– However, not portable
– Don’t rely on long-term availability of these tools for maintenance
– (Suspect functionality will be incorporated into vendor tools)
•
VHDL is
i the
th prime
i
source for
f archiving
hi i
and
d sharing
h i
•
•
Proprietary vendor firmware unavoidable
Proprietary vendor IP desirable
•
•
We should all review our archiving policy
We should all review our documentation
•
Many thanks to all who supplied information
26 March 2009
Ian Brawn
12
Conclusions
•
Language: VHDL / Verilog:
– tools can handle both in one design.
– So can designers, if they have to….
•
Front-end entry packages option
– Many advantages for design entry, organisation, navigation
– However, not portable
– Don’t rely on long-term availability of these tools for maintenance
– (Suspect functionality will be incorporated into vendor tools)
•
VHDL is
i the
th prime
i
source for
f archiving
hi i
and
d sharing
h i
•
•
Proprietary vendor firmware unavoidable
Proprietary vendor IP desirable
•
•
We should all review our archiving policy
We should all review our documentation
•
Many thanks to all who supplied information
26 March 2009
Ian Brawn
… but not right now.
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