7 Series FPGAs Packaging and Pinout www.BDTIC.com/XILINX Advance Specification

7 Series FPGAs
Packaging and Pinout
Advance Specification
UG475 (v1.4) October 17, 2011
www.BDTIC.com/XILINX
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
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brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and
conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any
application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:
http://www.xilinx.com/warranty.htm#critapps.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE
XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES
THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF
XILINX PRODUCTS IN SUCH APPLICATIONS.
© Copyright 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, and other designated brands included herein
are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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7 Series FPGAs Packaging
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UG475 (v1.4) October 17, 2011
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
03/01/11
1.0
Initial Xilinx release.
04/06/11
1.1
Removed the SBG324 package from the entire document. Added three Kintex-7 devices:
XC7K355T, XC7K420T, and XC7K480T.
Updated disclaimer and copyright on page 2. Updated package size of FF1156 in
Table 1-1. Updated DXP_0, DXN_0 in Table 1-9.
The Table 2-2 single ASCII device files have been updated for both the XC7K70T and
XC7K160T. All ASCII TXT files and the overall ZIP file have been updated on the web.
Updated the XC7K70TFBG676 figures: Figure 3-13, Figure 3-14, Figure 3-15, and
Figure 3-16.
Added information to Chapter 4, Mechanical Drawings, Chapter 5, Thermal
Specifications, and Chapter 6, Package Marking.
06/14/11
1.2
Added Virtex-7 device information including updating Table 1-1, adding Table 1-5,
Table 1-8, Table 2-3, and Table 3-3. In Table 1-9, updated Note 3, the Configuration Pins
section, and the Analog to Digital Converter (XADC) Pins section.
Updated Figure 3-11, Figure 3-12, Figure 3-15, Figure 3-16, Figure 3-19, Figure 3-20,
Figure 3-23, Figure 3-24, Figure 3-27, Figure 3-28, Figure 3-31, and Figure 3-32. Added
Figure 3-33 through Figure 3-88.
Added Figure 4-7 the mechanical drawing for the Kintex-7 devices FFG1156 package.
Also added some Virtex-7 device mechanical drawings in Figure 4-8 through
Figure 4-11.
Added thermal resistance data to Table 5-1.
10/03/11
1.3
Added Artix-7 device information including updating Table 1-1, adding Table 1-3,
Table 1-6, Table 2-1, and Table 3-1.
Clarified the interposer in Figure 1-12 and Figure 1-13. Revised horizontal center for the
XC7VX415T in Figure 1-15. Updated the DXP_0/DXN_0 description and notes in
Table 1-9. Added devices to the Die Level Bank Numbering Overview section. Clarified
the I/O banks summary: section.
Added Artix-7 device diagrams in the CSG324 package: Figure 3-1 through Figure 3-8.
Added XC7V585T device diagrams Figure 3-53 through Figure 3-60.
Moved AD4P/N, AD12P/N, and AD5P/N pins from [IO_L2P_T0_35:IO_L4N_T0_35] to
[IO_L1P_T0_35:IO_L3N_T0_35] in Figure 3-61, Figure 3-65, Figure 3-69, Figure 3-73,
Figure 3-77, Figure 3-81, and Figure 3-85.
Fixed the labeling for EMCCLK in Figure 3-37, Figure 3-41, Figure 3-45, Figure 3-49,
Figure 3-53, Figure 3-61, Figure 3-65, Figure 3-69, Figure 3-73, Figure 3-77, Figure 3-81,
and Figure 3-85.
Updated the mechanical drawings for Figure 4-9 and Figure 4-11.
Updated thermal resistance data in Table 5-1.
Updated Chapter 6, Package Marking.
10/17/11
1.4
Revised the FBG484 Package section describing XC7K160T Banks.
Added the mechanical drawings: Figure 4-10 and Figure 4-12. Updated Figure 4-11 to
include the FF(G)1928 package.
Added thermal resistance data to Table 5-1.
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UG475 (v1.4) October 17, 2011
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7 Series FPGAs Packaging
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
www.xilinx.com
UG475 (v1.4) October 17, 2011
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1: Packaging Overview
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Serial Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Banking and Clocking Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7A8 or XC7A15 Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7A30T or XC7A50T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7A100T Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSG324 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K70T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG484 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K160T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG484 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 and FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K325T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 and FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG900 and FFG900 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K355T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG901 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K410T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 and FFG676 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG900 and FFG900 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K420T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG901 and FFG1156 Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7K480T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG901 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1156 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7V585T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7V1500T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7V2000T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7 Series FPGAs Packaging
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FHG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FLG1925 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
XC7VX330T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX415T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX485T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX550T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX690T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1157 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1158 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1761 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1926 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1927 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX980T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1926 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1928 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC7VX1140T Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLG1928 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLG1930 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 2: 7 Series FPGAs Package Files
About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 3: Device Diagrams
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Artix-7 FPGAs Device Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSG324 Package—XC7A8 and XC7A15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T . . . . . . . . . . . . . . . . . . . . . . . 55
Kintex-7 FPGAs Device Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FBG484 Package—XC7K70T and XC7K160T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 Package—XC7K70T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FBG676 Package—XC7K160T, XC7K325T, and XC7K410T . . . . . . . . . . . . . . . . . . . . . .
FBG900 Package—XC7K325T and XC7K410T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T . . . . . . . . . . . . . . . . . . . . . .
FFG900 Package—XC7K325T and XC7K410T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG901 Package—XC7K355T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFG901 Package—XC7K420T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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UG475 (v1.4) October 17, 2011
FFG901 Package—XC7K480T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
FFG1156 Package—XC7K420T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
FFG1156 Package—XC7K480T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Virtex-7 FPGAs Device Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
FFG1157 Package—XC7V585T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
FFG1761 Package—XC7V585T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
FLG1925 Package—XC7V2000T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
FHG1761 Package—XC7V2000T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
FFG1157 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
FFG1158 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
FFG1761 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
FFG1927 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
FFG1930 Package—XC7VX485T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 4: Mechanical Drawings
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)676 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)900 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)901 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)1156 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)1157 and FF(G)1158 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)1761 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FH(G)1761 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FF(G)1926, FF(G)1927, FF(G)1928, and FF(G)1930 Flip-Chip BGA
(Virtex-7 FPGAs) (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FL(G)1925, FL(G)1928, and FL(G)1930 Flip-Chip BGA
(Virtex-7 FPGAs) (1.0 mm Pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
135
136
137
138
139
140
141
142
143
144
145
146
147
Chapter 5: Thermal Specifications
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Some Thermal Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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149
153
155
156
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 6: Package Marking
Appendix A: Recommended PCB Design Rules for BGA Packages
8
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UG475 (v1.4) October 17, 2011
Preface
About This Guide
Xilinx® 7 series FPGAs include three unified FPGA families that are all designed for
lowest power to enable a common design to scale across families for optimal power,
performance, and cost. The Artix™-7 family is optimized for lowest cost and absolute
power for the highest volume applications. The Virtex®-7 family is optimized for highest
system performance and capacity. The Kintex™-7 family is an innovative class of FPGAs
optimized for the best price-performance. This guide serves as a technical reference
describing the 7 series packaging and pinout specifications.
This 7 series packaging and pinout specification, part of an overall set of documentation on
the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7.
Guide Contents
This manual contains the following chapters:
•
Chapter 1, Packaging Overview
•
Chapter 2, 7 Series FPGAs Package Files
•
Chapter 3, Device Diagrams
•
Chapter 4, Mechanical Drawings
•
Chapter 5, Thermal Specifications
•
Chapter 6, Package Marking
•
Appendix A, Recommended PCB Design Rules for BGA Packages
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
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9
Preface: About This Guide
10
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Chapter 1
Packaging Overview
Summary
This chapter covers the following topics:
•
Introduction
•
Device/Package Combinations and Maximum I/Os
•
Pin Definitions
•
Die Level Bank Numbering Overview
Introduction
This section describes the pinouts for the 7 series FPGAs in 0.5 mm chip-scale, 0.8 mm chip
scale, and 1.0 mm in various fine pitch and flip-chip BGA packages.
Artix™-7 and Kintex™-7 devices are offered in low-cost, space-saving packages that are
optimally designed for the maximum number of user I/Os.
Virtex®-7 and Virtex-7X devices are offered exclusively in high performance flip-chip BGA
packages that are optimally designed for improved signal integrity and jitter.
Package inductance is minimized as a result of optimal placement and even distribution as
well as an increased number of Power and GND pins.
All packages are available as Pb-free (G) with selected packages including a Pb-only
option.
All of the 7 series devices supported in a particular package are pinout compatible and are
listed in the same table (one table per package). Pins that are not available for the smaller
devices are listed as “No Connects”.
Each device is split into I/O banks to allow for flexibility in the choice of I/O standards
(see UG471, 7 Series FPGAs SelectIO Resources User Guide). Global pins, including JTAG,
configuration, and power/ground pins, are listed at the end of each table. Table 1-9
provides definitions for all pin types.
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11
Chapter 1: Packaging Overview
Device/Package Combinations and Maximum I/Os
Table 1-1 shows the maximum number of user I/Os possible in the 7 series FPGAs BGA
packages. Some devices are available in both Pb and Pb-free (additional G) packages as
standard ordering options.
Table 1-1:
7 Series FPGAs Package Specifications
Packages(1)
Package Specifications
Description
Package Type
Pitch (mm)
Size (mm)
Maximum I/Os(2)
BGA
0.5
10 x 10
140
BGA
0.8
12 x 12
100
CSG324
BGA
0.8
15 x 15
210
FTG256
BGA
1.0
17 x 17
170
BGA
1.0
23 x 23
285
FGG676
BGA
1.0
27 x 27
300
FB(G)484
BGA
1.0
23 x 23
285
BGA
1.0
27 x 27
400
FB(G)900
BGA
1.0
31 x 31
500
FF(G)676
BGA
1.0
27 x 27
400
FF(G)900
BGA
1.0
31 x 31
500
FF(G)901
BGA
1.0
31 x 31
380
FF(G)1156
BGA
1.0
35 x 35
600
FF(G)1157
BGA
1.0
35 x 35
600
FF(G)1158
BGA
1.0
35 x 35
350
FF(G)1761
BGA
1.0
42.5 x 42.5
850
BGA
1.0
45 x 45
720
BGA
1.0
45 x 45
600
FF(G)1928
BGA
1.0
45 x 45
480
FF(G)1930
BGA
1.0
45 x 45
1000
FL(G)1761
BGA
1.0
42.5 x 42.5
850
FL(G)1925
BGA
1.0
45 x 45
1200
FL(G)1928
BGA
1.0
45 x 45
480
FL(G)1930
BGA
1.0
45 x 45
1100
FH(G)1761
BGA
1.0
45 x 45
850
CPG236
CSG225
FGG484
FB(G)676
FF(G)1926
FF(G)1927
Wire-bond chip-scale
Wire-bond fine-pitch
Flip-chip bare-die
Flip-chip fine-pitch
Notes:
1. Leaded package options (FFxxx/FBxxx) are available for the Kintex-7 XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, and
XC7K480Tdevices.
2. The maximum I/O numbers do not include pins in the configuration Bank 0 (Table 1-2) or the GTX serial transceivers.
12
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Device/Package Combinations and Maximum I/Os
Table 1-2 lists the 21 dedicated I/O pins.
Table 1-2:
7 series FPGAs I/O Pins in the Dedicated Configuration Bank (Bank0)
DXP_0
VCCBATT_0
INIT_B_0
M0_0
TDO_0
TDI_0
GNDADC_0
DXN_0
DONE_0
VN_0
M1_0
TCK_0
VREFN_0
VCCADC_0
PROGRAM_B_0
CCLK_0
VP_0
M2_0
TMS_0
VREFP_0
CFGBVS_0
Serial Transceiver Channels by Device/Package
Table 1-3 lists the quantity of GTP serial transceiver channels for the Artix-7 FPGAs.
Table 1-4 lists the quantity of GTX serial transceiver channels for the Kintex-7 FPGAs.
Table 1-5 lists the quantity of GTX and GTH serial transceiver channels for the Virtex-7
FPGAs. In all devices, a serial transceiver channel is one set of MGTRXP, MGTRXN,
MGTTXP, and MGTTXN pins.
Table 1-3:
Serial Transceiver Channels (GTPs) by Device/Package (Artix-7 FPGAs)
GTP Channels by Package
Device
CPG236
CSG225
CSG324
FTG256
FGG484
FGG676
FBG484
FBG676
FFG1156
XC7A8
0
0
0
–
–
–
–
–
–
XC7A15
0
0
0
–
–
–
–
–
–
XC7A30T
–
4
0
0
4
–
–
–
–
XC7A50T
–
4
0
0
4
–
–
–
–
XC7A100T
–
–
0
0
4
8
–
–
–
XC7A200T
–
–
–
–
–
–
4
8
16
XC7A350T
–
–
–
–
–
–
4
8
16
Table 1-4:
Serial Transceiver Channels (GTXs) by Device/Package (Kintex-7 FPGAs)
GTX Channels by Package
Device
FBG484
FBG676
FBG900
FFG676
FFG900
FFG901
FFG1156
XC7K70T
4
8
–
–
–
–
–
XC7K160T
4
8
–
8
–
–
–
XC7K325T
–
8
16
8
16
–
–
XC7K355T
–
–
–
–
–
24
–
XC7K410T
–
8
16
8
16
–
–
XC7K420T
–
–
–
–
–
28
28
XC7K480T
–
–
–
–
–
28
32
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7 Series FPGAs Packaging
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13
Chapter 1: Packaging Overview
Table 1-5:
Serial Transceiver Channels (GTX/GTH) by Device/Package (Virtex-7 FPGAs)
GTX or GTH Channels by Package
Device
XC7V585T
FFG
FFG
FFG
FFG
FFG
FFG
FFG
FLG
FLG
FLG
FLG
FHG
1157
1158
1761
1926
1927
1928
1930
1761
1925
1928
1930s
1761
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
36
0
20
0
36
–
0
XC7V1500T
–
–
–
–
–
–
–
XC7V2000T
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
XC7VX330T
0
20
XC7VX415T
0
20
0
48
XC7VX485T
20
0
48
0
0
48
0
48
XC7VX550T
XC7VX690T
–
0
20
–
28
–
28
0
–
0
36
XC7VX980T
–
–
–
XC7VX1140T
–
–
–
14
–
0
48
–
–
56
0
–
–
0
64
–
0
80
–
0
64
0
64
–
–
–
0
24
36
0
–
72
–
0
16
0
0
24
–
–
–
–
–
0
24
–
–
–
–
–
–
–
–
0
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96
0
24
–
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Device/Package Combinations and Maximum I/Os
Table 1-6 shows the number of available I/Os and the number of differential I/Os for each
Artix-7 device/package combination. Table 1-7 shows the number of available I/Os and
the number of differential I/Os for each Kintex-7 device/package combination. Table 1-8
shows the number of available I/Os and the number of differential I/Os for each Virtex-7
device/package combination. When applicable, it also lists the number of user I/Os in the
3.3V-capable high-range (HR) banks and the number of 1.8V-capable high-performance
(HP) banks.
Table 1-6:
Artix-7
Devices
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
Available I/O Pin/Device/Package Combinations for Artix-7 FPGAs
User I/O
Pins
User I/O
Artix-7 Packages: HR I/O Banks Only
CPG236 CSG225 CSG324 FTG256 FGG484 FGG676 FBG484 FBG676 FFG1156
140
Differential
User I/O
140
Differential
–
200
–
192
–
200
–
192
100
210
170
170
170
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
250
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
300
–
–
–
–
–
–
285
400
500
285
400
600
User I/O
–
Differential
–
User I/O
–
Differential
–
User I/O
–
–
210
Differential
–
–
202
User I/O
–
–
–
–
–
–
Differential
–
–
–
–
–
–
User I/O
–
–
–
–
–
–
Differential
–
–
–
–
–
–
202
100
210
170
250
202
170
285
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
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15
Chapter 1: Packaging Overview
Table 1-7:
Available I/O Pin/Device/Package Combinations for Kintex-7 FPGAs
Kintex-7 Packages: HR and HP I/O Banks
Kintex-7
Devices
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
16
User I/O
Pins
FBG484
FBG676
FBG900
FFG676
FFG900
HP
HR
HP
HR
HP
HR
HP
HR
HP
HR
HP
HR
HP
HR
User I/O
100
185
100
200
–
–
–
–
–
–
–
–
–
–
Differential
96
179
96
192
–
–
–
–
–
–
–
–
–
–
User I/O
100
185
150
250
–
–
150
250
–
–
–
–
–
–
Differential
96
179
144
240
–
–
144
240
–
–
–
–
–
–
User I/O
–
–
150
250
150
350
150
250
150
350
–
–
–
–
Differential
–
–
144
240
144
336
144
240
144
336
–
–
–
–
User I/O
–
–
–
–
–
–
–
–
–
–
0
300
–
–
Differential
–
–
–
–
–
–
–
–
–
–
0
288
–
–
User I/O
–
–
150
250
150
350
150
250
150
350
–
–
–
–
Differential
–
–
144
240
144
336
144
240
144
336
–
–
–
–
User I/O
–
–
–
–
–
–
–
–
–
–
0
350
0
350
Differential
–
–
–
–
–
–
–
–
–
–
0
336
0
366
User I/O
–
–
–
–
–
–
–
–
–
–
0
380
0
400
Differential
–
–
–
–
–
–
–
–
–
–
0
366
0
384
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FFG901
FFG1156
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Device/Package Combinations and Maximum I/Os
Table 1-8:
Available I/O Pin/Device/Package Combinations for Virtex-7 FPGAs
Virtex-7 Packages: HR and HP I/O Banks
User FFG
Virtex-7
I/O
Devices
Pins 1157
FFG
FFG
FFG
FFG
FFG
FFG
FLG
FLG
FLG
FLG
FHG
1158
1761
1926
1927
1928
1930
1761
1925
1928
1930
1761
HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR HP HR
User 600 0
–
750 100
–
–
–
–
–
–
–
–
–
Diff
576 0
–
720 96
–
–
–
–
–
–
–
–
–
User
–
–
–
–
–
–
–
850 0
–
–
–
–
Diff
–
–
–
–
–
–
–
816 0
–
–
–
–
User
–
–
–
–
–
–
–
–
1200 0
–
–
850 0
Diff
–
–
–
–
–
–
–
–
1152 0
–
–
816 0
–
650 50
–
–
–
–
–
–
–
–
–
–
624 48
–
–
–
–
–
–
–
–
–
–
–
600 0
–
–
–
–
–
–
–
–
–
576 0
–
–
–
–
–
–
–
XC7VX User 600 0 350 0 700 0
485T
Diff 576 0 336 0 672 0
–
600 0
–
700
0
–
–
–
–
–
–
576 0
–
672
0
–
–
–
–
–
–
350 0
–
–
600 0
–
–
–
–
–
–
–
–
336 0
–
–
576 0
–
–
–
–
–
–
–
XC7VX User 600 0 350 0 850 0 720 0 600 0
690T
Diff 576 0 336 0 816 0 690 0 576 0
–
1000 0
–
–
–
–
–
–
960
0
–
–
–
–
–
XC7V
585T
XC7V
1500T
XC7V
2000T
XC7VX User 600 0
330T
Diff 576 0
XC7VX User 600 0 350 0
415T
Diff 576 0 336 0
XC7VX User
550T
Diff
XC7VX User
980T
Diff
–
–
–
720 0
–
480 0
900
0
–
–
–
–
–
–
–
–
690 0
–
460 0
864
0
–
–
–
–
–
XC7VX User
1140T
Diff
–
–
–
–
–
–
–
–
–
480 0 1100 0
–
–
–
–
–
–
–
–
–
–
460 0 1056 0
–
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7 Series FPGAs Packaging
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17
Chapter 1: Packaging Overview
Pin Definitions
Table 1-9 lists the pin definitions used in 7 series FPGAs packages.
Note: There are dedicated general purpose user I/O pins listed separately in Table 1-9. There are
also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,
where ZZZ represents one or more functions in addition to being general purpose user I/O. If not used
for their special function, these pins can be user I/O.
Table 1-9:
7 series FPGAs Pin Definitions
Pin Name
Type
Direction
Description
User I/O Pins
IO_LXXY_#
IO_XX_#
Dedicated
Input/
Output
Most user I/O pins are capable of differential signaling and
can be implemented as pairs. The top and bottom I/O pins
are always single ended. Each user I/O is labeled
IO_LXXY_#, where:
• IO indicates a user I/O pin.
• L indicates a differential pair, with XX a unique pair in
the bank and Y = [P|N] for the positive/negative sides
of the differential pair.
• # indicates a bank number.
Configuration Pins
For more information, see the Configuration Pin Definitions table in UG470, 7 Series FPGAs Configuration User Guide.
CCLK_0
Dedicated(1)
Input/
Output
Configuration clock. Output in Master mode or input in
Slave mode.
DONE_0
Dedicated(1)
Bidirectional
Active High, DONE indicates successful completion of
configuration.
INIT_B_0
Dedicated(1)
Bidirectional Active Low, indicates initialization of configuration memory.
(open-drain)
M0_0, M1_0, or M2_0
Dedicated(1)
Input
Configuration mode selection
PROGRAM_B_0
Dedicated(1)
Input
Active Low, asynchronous reset to configuration logic.
TCK_0
Dedicated(1)
Input
JTAG clock.
TDI_0
Dedicated(1)
Input
JTAG data input.
TDO_0
Dedicated(1)
Output
JTAG data output.
TMS_0
Dedicated(1)
Input
JTAG mode select.
Input
This pin selects the preconfiguration I/O standard type for
the dedicated and multi-function configuration banks 0, 14,
and 15. If the VCCO for banks 0, 14, or 15 is 2.5V or 3.3V, then
this pin must be connect to VCCO_0. If the VCCO for banks 0,
14, and 15 are less than or equal to 1.8V, then this pin should
be connected to GND.
CFGBVS_0
Dedicated(1)
Note: To avoid device damage, this pin must be connected
correctly. See the Configuration Bank Voltage Select section in
UG470: 7 Series FPGAs Configuration User Guide for more
information.
D00 through D31
18
Multi-function
Bidirectional Configuration data pins.
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7 Series FPGAs Packaging
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Pin Definitions
Table 1-9:
7 series FPGAs Pin Definitions (Cont’d)
Pin Name
Type
Direction
ADV_B
Multi-function
Output
BPI Flash address valid output
A00 through A28
Multi-function
Output
Address A00–A28 BPI address output.
RS0 or RS1
Multi-function
Output
RS0 and RS1 revision select output.
FCS_B
Multi-function
Output
BPI and SPI flash chip select.
FOE_B
Multi-function
Output
BPI flash output enable.
MOSI
Multi-function
Output
SPI flash command output. Also known as the SPI bus
master output, slave input signal.
FWE_B
Multi-function
Output
BPI flash write enable.
DOUT
Multi-function
Output
Data output for serial daisy-chain configuration.
CSO_B
Multi-function
Output
Active Low chip-select output for parallel daisy-chain.
CSI_B
Multi-function
Input
PUDC_B
Multi-function
Input
Description
SelectMAP active Low chip-select input.
Active Low input enables internal pull-ups during
configuration on all SelectIO pins:
0 = Weak preconfiguration I/O pull-up resistors enabled
1 = Weak preconfiguration I/O pull-up resistors disabled
RDWR_B
Multi-function
Input
SelectMAP data bus direction control signal for reading or
writing configuration data.
EMCCLK
Multi-function
Input
External master configuration clock.
GND
Dedicated
N/A
Ground.
VCCAUX
Dedicated
N/A
1.8V power-supply pins for auxiliary circuits.
VCCAUX_IO_G#(2)
Dedicated
N/A
1.8V/2.0V power-supply pins for auxiliary I/O circuits.
VCCINT
Dedicated
N/A
0.9V/1.0V power-supply pins for the internal core logic.
VCCO_#(3)
Dedicated
N/A
Power-supply pins for the output drivers (per bank).
VCCBRAM
Dedicated
N/A
1.0V power-supply pins for the FPGA logic block RAM.
VCCBATT_0
Dedicated
N/A
Decryptor key memory backup supply; this pin should be
tied to the appropriate VCC or GND when not used.(4)
VREF
Multi-function
N/A
These are input threshold voltage pins. They become user I/
Os when an external threshold voltage is not needed (per
bank).
Power/Ground Pins
Analog to Digital Converter (XADC) Pins
For more information, see the XADC Package Pins table in UG480, 7 Series FPGAs XADC User Guide.
VCCADC_0(5)
Dedicated
N/A
XADC analog positive supply voltage.
(5)
Dedicated
N/A
XADC analog ground reference.
VP_0(5)
Dedicated
Input
XADC dedicated differential analog input (positive side).
VN_0(5)
Dedicated
Input
XADC dedicated differential analog input (negative side).
GNDADC_0
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19
Chapter 1: Packaging Overview
Table 1-9:
7 series FPGAs Pin Definitions (Cont’d)
Pin Name
(5)
Type
Direction
Description
VREFP_0
Dedicated
N/A
1.25V reference input.
VREFN_ 0(5)
Dedicated
N/A
1.25V reference GND reference.
AD0P through AD15P
AD0N through AD15N
Multi-function
Input
XADC (analog-to-digital converter) differential auxiliary
analog inputs 0–15.
Auxiliary channels 6, 7, 13, 14, and 15 are not supported on
Kintex-7 devices.
Multi-gigabit Serial Transceiver Pins (GTXE2 and GTHE2)
For more information on the GTXE2 pins see the Pin Description and Design Guidelines section in UG476, 7 Series FPGAs
GTX Transceivers User Guide.
MGTXRXP[0:3]
Dedicated
Input
Positive differential receive port GTX Quad.
MGTXRXN[0:3]
Dedicated
Input
Negative differential receive port GTX Quad.
MGTXTXP[0:3]
Dedicated
Output
Positive differential transmit port GTX Quad.
MGTXTXN[0:3]
Dedicated
Output
Negative differential transmit port GTX Quad.
MGTHRXP[0:3]
Dedicated
Input
Positive differential receive port GTH Quad.
MGTHRXN[0:3]
Dedicated
Input
Negative differential receive port GTH Quad.
MGTHTXP[0:3]
Dedicated
Output
Positive differential transmit port GTH Quad.
MGTHTXN[0:3]
Dedicated
Output
Negative differential transmit port GTH Quad.
MGTAVCC_G#
Dedicated
Input
1.0V analog power-supply pin for the receiver and
transmitter internal circuits.
MGTAVTT_G#
Dedicated
Input
1.2V analog power-supply pin for the transmit driver.
MGTVCCAUX_G#
Dedicated
Input
1.8V auxiliary analog Quad PLL (QPLL) voltage supply for
the transceivers.
MGTREFCLK0/1P
Dedicated
Input
Positive differential reference clock for the transceivers.
MGTREFCLK0/1N
Dedicated
Input
Negative differential reference clock for the transceivers.
MGTAVTTRCAL
Dedicated
N/A
Precision reference resistor pin for internal calibration
termination. Not used for Artix-7 devices.
MGTRREF
Dedicated
Input
Precision reference resistor pin for internal calibration
termination.
Dedicated
N/A
Reserved. No Connection; leave floating.
Input
These are the clock capable I/Os driving BUFRs, BUFIOs,
BUFGs, and MMCMs/PLLs. In addition, these pins can drive
the BUFMR for multi-region BUFIO and BUFR support.
These pins become regular user I/Os when not needed as a
clock. When connecting a single-ended clock to the
differential CC pair of pins, it must be connected to the
positive (P) side of the pair. The MRCC (multi-region) pins,
when used as single region resource, can drive four BUFIOs
and four BUFR in a single bank.
Other Pins
RSVD
MRCC
20
Multi-function
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7 Series FPGAs Packaging
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Pin Definitions
Table 1-9:
7 series FPGAs Pin Definitions (Cont’d)
Pin Name
Type
Direction
Description
SRCC
Multi-function
Input
These are the clock capable I/Os driving BUFRs, BUFIOs,
and MMCMs/PLLs. These pins become regular user I/Os
when not needed for clocks. When connecting a single-ended
clock to the differential CC pair of pins, it must be connected
to the positive (P) side of the pair. The SRCC (single region)
pins can drive four BUFIOs and four BUFRs in a single bank.
VRN(6)
Multi-function
N/A
This pin is for the DCI voltage reference resistor of N
transistor (per bank, to be pulled High with reference
resistor).
VRP(6)
Multi-function
N/A
This pin is for the DCI voltage reference resistor of P
transistor (per bank, to be pulled Low with reference
resistor).
Temperature-sensing diode pins (Anode: DXP; Cathode:
DXN). The thermal diode is accessed by using the DXP and
DXN pins in bank 0. When not used, tie to GND.
DXP_0, DXN_0
Dedicated
Input
To use the thermal diode an appropriate external thermal
monitoring IC must be added. Consult the external thermal
monitoring IC data sheet for usage guidelines.
The recommended temperature monitoring solution for
7 series FPGAs uses the temperature sensor in the XADC
block.
T0, T1, T2, or T3
Multi-function
Input
This pin belongs to the memory byte group 0-3.
T0_DQS, T1_DQS,
T2_DQS, or T3_DQS
Multi-function
Input
The DDR DQS strobe pin that belongs to the memory byte
group T0–T3.
Notes:
1. All dedicated pins (JTAG and configuration) are powered by VCCO_0.
2. For devices that do not include VCCAUX_IO_G# pins, auxiliary I/O circuits are powered by VCCAUX pins.
3. VCCO pins in unbonded banks must be connected to the VCCO for that bank for package migration. Do NOT connect unbonded
VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be tied to a common
supply (VCCO or ground).
4. Refer to the data sheet for VCCBATT_0 specifications.
5. See UG480, 7 Series FPGAs XADC User Guide for the default connections required to support on-chip monitoring.
6. The DCI guidelines in the 7 series FPGAs are different from previous Virtex device DCI guidelines. See the DCI sections in UG471:
7 Series FPGAs SelectIO Resources User Guide for more information on the VRN/VRP pins.
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21
Chapter 1: Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
•
The center clocking backbone contains all vertical clock tracks and clock buffer
connectivity.
•
The CMT backbone contains all vertical CMT connectivity and is located in the CMT
column.
•
Not all banks are bonded out in every part/package combination.
•
GTP/GTX/GTH columns summary:
•
•
One bank = One GT Quad = Four transceivers = Four GTPE2s or GTXE2s or
GTHE2 primitives.
•
Not all GT Quads are bonded out in every package.
I/O banks summary:
•
•
•
•
Each bank has four pairs of clock capable (CC) inputs for four differential or four
single ended clock inputs.
-
Can connect to the CMT in the same region and the region above and below
(with restrictions).
-
Two MRCC pairs can connect to the BUFRs and BUFIOs in the same region/
banks and the regions/banks above and below.
-
Two SRCCs pairs can only connect to the BUFRs and BUFIOs in the same
region/bank.
-
There are no global clock pins (GC pins) in the 7 series FPGAs.
Each user I/O bank has 50 single-ended I/Os or 24 differential pairs (48
differential I/Os). The top and bottom I/O pin are always single ended. All 50
pads of a bank are not always bonded out to pins.
Bank locations of dedicated and dual-purpose pins:
•
In most devices, banks 14 and 15 always contain the dual-purpose configuration
pins. Bank 15 and 35 contains the XADC auxiliary inputs; however, in Kintex-7
devices, the auxiliary inputs are only in bank 15. Bank 0 contains the dedicated
configuration pins.
•
In the XC7V1500T and XC7V2000T devices, banks 11 and 12 contain the
dual-purpose configuration pins. Bank 12 and 32 contains the XADC auxiliary
inputs. Bank 0 contains the dedicated configuration pins.
•
All dedicated configuration I/Os (bank 0) are 3.3V capable
The physical XY locations for each IDELAYCTRL start at X0Y0 in the bottom left-most
bank and are then increment by one starting with the lowest bank number in each
column in the vertical Y direction and by one for each column in the horizontal X
direction. IDELAYCTRLs are located in each of the HROWs.
Figure 1-1 through Figure 1-20 visually describe a die view of the FPGA bank numbering.
Note: The figures for some Artix-7 and Virtex-7 FPGAs are in development.
22
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Die Level Bank Numbering Overview
XC7A8 or XC7A15 Banks
Figure 1-4 shows the I/O banks for the XC7A8 and XC7A15. These devices do not include
transceiver banks.
CSG324 Package
•
All HR banks are fully bonded out.
X-Ref Target - Figure 1-1
Left I/O
Column
Banks
Right I/O
Column
Banks
HROW
Bank 15
HR
PLL11
Bank 35
HR
CMT
16 BUFGs
MMCM11
16 BUFGs
PLL10
Horizontal Center
Bank 14
HR
Bank 34
HR
CMT
MMCM10
Clocking
Backbone
Figure 1-1:
Bank
50 I/Os
CMT
Backbone
UG475_c1_01_082411
XC7A8 and XC7A15 Banks
XC7A30T or XC7A50T Banks
Figure 1-2 shows the I/O and transceiver banks for the XC7A30T or XC7A50T.
CSG324 Package
•
HR bank 16 is partially bonded out.
•
The GTX Quad bank 116 is not bonded out.
X-Ref Target - Figure 1-2
Left I/O
Column
Banks
Bank 16
HR
Bank 15
HR
Right I/O
Column
Banks
PLL02
CMT
HROW
GTP Quad 116
MMCM02
PLL01
PLL11
CMT
CMT
MMCM01
16 BUFGs
MMCM11
PLL00
16 BUFGs
PLL10
Quad
GTP
Bank 35
HR
Horizontal Center
Bank 14
HR
CMT
MMCM00
CMT
Backbone
Figure 1-2:
CMT
MMCM10
Clocking
Backbone
Bank 34
HR
CMT
Backbone
Bank
50 I/Os
UG475_c1_02_081211
XC7A30T and XC7A50T Banks
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23
Chapter 1: Packaging Overview
XC7A100T Bank
Figure 1-3 shows the I/O and transceiver banks for the XC7A100T.
CSG324 Package
•
HR bank 13 is not bonded out.
•
HR bank 16 is partially bonded out.
•
The GTX Quad bank 116 is not bonded out.
X-Ref Target - Figure 1-3
Left I/O
Column
Banks
Bank 16
HR
Bank 15
HR
Right I/O
Column
Banks
PLL03
CMT
GTP Quad 116
MMCM03
PLL02
PLL11
CMT
CMT
MMCM02
16 BUFGs
MMCM11
PLL01
16 BUFGs
PLL10
Quad
GTP
Bank 35
HR
Horizontal Center
Bank 14
HR
Bank 13
HR
CMT
MMCM01
PLL00
CMT
CMT
MMCM10
HROW
Bank 34
HR
Bank
50 I/Os
GTP Quad 113
MMCM00
CMT
Backbone
Clocking
Backbone
CMT
Backbone
UG475_c1_03_081211
Figure 1-3:
24
XC7A100T Banks
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7 Series FPGAs Packaging
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Die Level Bank Numbering Overview
XC7K70T Banks
Figure 1-4 shows the I/O and transceiver banks for the XC7K70T.
FBG484 Package
•
HR bank 16 is partially bonded out.
•
All HP banks are fully bonded out.
•
The GTX Quad bank 116 is not bonded out.
FBG676 Package
•
All HR and HP banks and the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-4
Left I/O
Column
Banks
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Right I/O
Column
Banks
PLL03
GTX Quad 116
CMT
MMCM03
Quad
GTX
PLL02
CMT
MMCM02
PLL01
CMT
GTX Quad 115
16 BUFGs
16 BUFGs
MMCM01
PLL00
CMT
CMT
MMCM11
PLL10
HROW
CMT
MMCM00
CMT
Backbone
PLL11
MMCM10
Clocking
Backbone
Bank 34
HP
Bank 33
HP
Horizontal
Center
Bank
50 I/Os
CMT
Backbone
UG475_c1_08_081211
Figure 1-4:
XC7K70T Banks
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25
Chapter 1: Packaging Overview
XC7K160T Banks
Figure 1-5 shows the I/O and transceiver banks for the XC7K160T.
FBG484 Package
•
HR bank 12 is not bonded out and bank 16 is partially bonded out.
•
HP bank 32 is not bonded out.
•
The GTX Quad bank 116 is not bonded out.
FBG676 and FFG676 Packages
•
All HR and HP banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-5
Left I/O
Column
Banks
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
Right I/O
Column
Banks
PLL04
CMT
GTX Quad 116
MMCM04
Quad
GTX
PLL03
CMT
MMCM03
PLL02
GTX Quad 115
16 BUFGs
16 BUFGs
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
PLL10
HROW
CMT
CMT
MMCM00
CMT
Backbone
MMCM10
Clocking
Backbone
Bank 34
HP
Horizontal
Center
Bank 33
HP
Bank 32
HP
Bank
50 I/Os
CMT
Backbone
UG475_c1_09_081211
Figure 1-5:
26
XC7K160T Banks
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7 Series FPGAs Packaging
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Die Level Bank Numbering Overview
XC7K325T Banks
Figure 1-6 shows the I/O and transceiver banks for the XC7K325T.
FBG676 and FFG676 Packages
•
HR banks 17 and 18 are not bonded out.
•
All HP banks are fully bonded out.
•
GTX Quads 117 and 118 are not bonded out.
FBG900 and FFG900 Packages
All HR and HP banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-6
Left I/O
Column
Banks
Bank 18
HR
Bank 17
HR
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
Right I/O
Column
Banks
PLL06
GTX Quad 118
CMT
MMCM06
Quad
GTX
PLL05
GTX Quad 117
CMT
MMCM05
PLL04
GTX Quad 116
CMT
MMCM04
PLL03
16 BUFGs
Horizontal
Center
16 BUFGs
CMT
GTX Quad 115
MMCM03
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL0
PLL10
HROW
CMT
CMT
MMCM00
CMT
Backbone
MMCM10
Clocking
Backbone
Bank 34
HP
Bank 33
HP
Bank 32
HP
Bank
50 I/Os
CMT
Backbone
UG475_c1_10_081211
Figure 1-6:
XC7K325T Banks
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27
Chapter 1: Packaging Overview
XC7K355T Banks
Figure 1-7 shows the I/O and transceiver banks for the XC7K355T.
FFG901 Package
All HR banks and the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-7
Left I/O
Column
Banks
Bank 17
HR
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
PLL04
CMT
GTX Quad 117
MMCM05
Quad
GTX
PLL04
CMT
GTX Quad 116
MMCM04
PLL03
GTX Quad 115
CMT
MMCM03
16 BUFGs
PLL02
16 BUFGs
CMT
Horizontal
Center
GTX Quad 114
MMCM02
PLL01
CMT
GTX Quad 113
MMCM01
PLL00
HROW
CMT
GTX Quad 112
MMCM00
CMT
Backbone
Clocking
Backbone
UG475_c1_11_060711
Figure 1-7:
28
XC7K355T Banks
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Die Level Bank Numbering Overview
XC7K410T Banks
Figure 1-8 shows the I/O and transceiver banks for the XC7K410T.
FBG676 and FFG676 Packages
•
HR banks 17 and 18 are not bonded out.
•
All HP banks are fully bonded out.
•
GTX Quads 117 and 118 are not bonded out.
FBG900 and FFG900 Packages
All HR and HP banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-8
Left I/O
Column
Banks
Bank 18
HR
Bank 17
HR
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
Right I/O
Column
Banks
PLL06
GTX Quad 118
CMT
MMCM06
Quad
GTX
PLL05
GTX Quad 117
CMT
MMCM05
PLL04
CMT
MMCM04
PLL03
CMT
GTX Quad 116
16 BUFGs
Horizontal
Center
16 BUFGs
GTX Quad 115
MMCM03
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL0
CMT
PLL10
HROW
CMT
MMCM00
CMT
Backbone
MMCM10
Clocking
Backbone
Bank 34
HP
Bank 33
HP
Bank 32
HP
Bank
50 I/Os
CMT
Backbone
UG475_c1_12_081211
Figure 1-8:
XC7K410T Banks
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Chapter 1: Packaging Overview
XC7K420T Banks
Figure 1-9 shows the I/O and transceiver banks for the XC7K420T.
FFG901 and FFG1156 Packages
•
All HR banks and the GTX Quads are fully bonded out in these packages.
X-Ref Target - Figure 1-9
Left I/O
Column
Banks
Bank 17
HR
Bank 16
HR
PLL06
CMT
GTX Quad 117
MMCM06
Quad
GTX
PLL05
CMT
GTX Quad 116
MMCM05
PLL04
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
Bank 11
HR
GTX Quad 115
CMT
MMCM04
16 BUFGs
PLL03
16 BUFGs
CMT
Horizontal
Center
GTX Quad 114
MMCM03
PLL02
GTX Quad 113
CMT
MMCM02
PLL01
CMT
GTX Quad 112
MMCM01
PLL0
HROW
CMT
GTX
Quad 111
I/O Clocking
MMCM00
CMT
Backbone
Backbone
Clocking
Backbone
UG475_c1_13_060711
Figure 1-9:
30
XC7K420T Banks
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Die Level Bank Numbering Overview
XC7K480T Banks
Figure 1-10 shows the I/O and transceiver banks for the XC7K480T.
FFG901 Package
•
HR bank 18 is not fully bonded out.
•
GTX Quad bank 118 is not bonded out.
FFG1156 Package
All HR banks and the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-10
Left I/O
Column
Banks
Bank 18
HR
Bank 17
HR
Bank 16
HR
Bank 15
HR
Bank 14
HR
Bank 13
HR
Bank 12
HR
Bank 11
HR
PLL07
CMT
GTX Quad 118
MMCM07
Quad
GTX
PLL06
CMT
GTX Quad 117
MMCM06
PLL05
CMT
GTX Quad 116
MMCM05
PLL04
CMT
MMCM04
16 BUFGs
PLL03
16 BUFGs
CMT
GTX Quad 115
Horizontal
Center
GTX Quad 114
MMCM03
PLL02
GTX Quad 113
CMT
MMCM02
PLL01
CMT
GTX Quad 112
MMCM01
PLL0
HROW
CMT
GTX
Quad 111
I/O Clocking
MMCM00
CMT
Backbone
Backbone
Clocking
Backbone
UG475_c1_14_060711
Figure 1-10:
XC7K480T Banks
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Chapter 1: Packaging Overview
XC7V585T Banks
Figure 1-11 shows the I/O and transceiver banks for the XC7V585T.
FFG1157 Package
•
All HR banks (11, 12, and 13) are not bonded out.
•
HP banks 31, 32, and 33 are not bonded out.
•
GTX Quads 111, 112, 113, and 119 are not bonded out.
FFG1761 Package
•
HR bank 11 is not bonded out.
•
All HP banks and the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-11
Left I/O
Column
Banks
Bank 19
HP
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank 14
HP
Bank 13
HR
Bank
50 I/Os
Bank 12
HR
Bank 11
HR
Right I/O
Column
Banks
PLL08
PLL18
CMT
CMT
MMCM08
MMCM18
PLL07
PLL17
CMT
CMT
MMCM07
MMCM17
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
PLL05
PLL15
CMT
CMT
MMCM05
16 BUFGs
PLL04
16 BUFGs
MMCM15
PLL14
CMT
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
CMT
PLL10
HROW
CMT
MMCM00
MMCM10
Bank 39
HP
GTX Quad 119
Bank 38
HP
GTX Quad 118
Bank 37
HP
GTX Quad 117
Bank 36
HP
GTX Quad 116
Bank 35
HP
GTX Quad 115
Bank 34
HP
GTX Quad 114
Bank 33
HP
GTX Quad 113
Bank 32
HP
GTX Quad 112
Bank 31
HP
GTX Quad 111
Horizontal Center
Clocking
Backbone
CMT
Backbone
UG475_c1_15_060711
Figure 1-11:
32
XC7V585T Banks
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Die Level Bank Numbering Overview
XC7V1500T Banks
Figure 1-12 shows the I/O and transceiver banks for the XC7V1500T.
FLG1761 Package
•
HP bank 11 is not bonded out.
•
All the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-12
Left I/O
Column
Banks
Bank 19
HP
Super Logic
Region 2
Bank 18
HP
Bank 17
HP
Right I/O
Column
Banks
PLL08
PLL18
CMT
CMT
MMCM08
BUFGs
PLL07
BUFGs
MMCM18
PLL17
CMT
CMT
MMCM07
MMCM17
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
Bank 39
HP
GTX Quad 119
Bank 38
HP
GTX Quad 118
Bank 37
HP
GTX Quad 117
Bank 36
HP
GTX Quad 116
Bank 35
HP
GTX Quad 115
Bank 34
HP
GTX Quad 114
Bank 33
HP
GTX Quad 113
Bank 32
HP
GTX Quad 112
Bank 31
HP
GTX Quad 111
Interposer
Bank 16
HP
Super Logic
Region 1
Bank 15
HP
Bank 14
HP
PLL05
PLL15
CMT
CMT
MMCM05
BUFGs
PLL04
BUFGs
CMT
MMCM15
PLL14
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
Interposer
Bank 13
HP
Super Logic
Region 0
Bank 12
HP
Bank 11
HP
PLL02
PLL12
CMT
CMT
MMCM02
BUFGs
PLL01
BUFGs
MMCM12
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
CMT
PLL10
HROW
CMT
MMCM00
MMCM10
Clocking
Backbone
CMT
Backbone
Horizontal Center
UG475_c1_16_090511
Figure 1-12:
XC7V1500T Banks
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33
Chapter 1: Packaging Overview
XC7V2000T Banks
Figure 1-13 shows the I/O and transceiver banks for the XC7V2000T.
FHG1761 Package
•
HP banks 11, 20, 21, 22, 40, 41, and 42 are not bonded out.
•
GTX Quads 120, 121, and 122 are not bonded out.
FLG1925 Package
34
•
All HP banks are fully bonded out in this package.
•
GTX Quads 111, 116, 117, 118, 119, 120, 121, and 122 are not bonded out.
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Die Level Bank Numbering Overview
X-Ref Target - Figure 1-13
Left I/O
Column
Banks
Bank 22
HP
Super Logic
Region 3
Bank 21
HP
Bank 20
HP
Right I/O
Column
Banks
PLL01
PLL11
CMT
CMT
MMCM11
BUFGs
PLL01
BUFGs
MMCM111
PLL11
CMT
CMT
MMCM10
MMCM110
PLL9
PLL19
CMT
CMT
MMCM09
MMCM19
Bank 42
HP
GTX Quad 122
Bank 41
HP
GTX Quad 121
Bank 40
HP
GTX Quad 120
Bank 39
HP
GTX Quad 119
Bank 38
HP
GTX Quad 118
Bank 37
HP
GTX Quad 117
Bank 36
HP
GTX Quad 116
Bank 35
HP
GTX Quad 115
Bank 34
HP
GTX Quad 114
Bank 33
HP
GTX Quad 113
Bank 32
HP
GTX Quad 112
Bank 31
HP
GTX Quad 111
Interposer
Bank 19
HP
Super Logic
Region 2
Bank 18
HP
Bank 17
HP
PLL08
PLL18
CMT
CMT
MMCM08
BUFGs
PLL07
BUFGs
MMCM18
PLL17
CMT
CMT
MMCM07
MMCM17
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
Interposer
Bank 16
HP
Super Logic
Region 1
Bank 15
HP
Bank 14
HP
PLL05
CMT
PLL15
HROW
CMT
MMCM05
BUFGs
PLL04
BUFGs
CMT
MMCM15
PLL14
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
Interposer
Bank 13
HP
Super Logic
Region 0
Bank 12
HP
Bank 11
HP
PLL02
PLL12
CMT
CMT
MMCM02
BUFGs
PLL01
BUFGs
MMCM12
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
PLL10
CMT
CMT
MMCM00
MMCM10
CMT
Backbone
Clocking
Backbone
CMT
Backbone
Horizontal Center
UG475_c1_17_090511
Figure 1-13:
XC7V2000T Banks
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Chapter 1: Packaging Overview
XC7VX330T Banks
Figure 1-14 shows the I/O and transceiver banks for the XC7VX330T.
FFG1157 Package
•
HR bank 13 is not bonded out.
•
HP bank 33 is not bonded out.
•
GTH Quads 113 and 119 are not bonded out.
FFG1761 Package
All HR and HP banks and the GTH Quads are fully bonded out in this package.
X-Ref Target - Figure 1-14
Left I/O
Column
Banks
Bank 19
HP
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank
50 I/Os
Bank 14
HP
Right I/O
Column
Banks
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
PLL05
PLL15
CMT
CMT
MMCM05
MMCM15
PLL04
PLL14
CMT
CMT
MMCM04
16 BUFGs
PLL03
16 BUFGs
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
CMT
CMT
MMCM10
Clocking
Backbone
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
Bank 33
HP
GTH Quad 113
Horizontal
Center
CMT
Backbone
Figure 1-14:
36
Bank 38
HP
PLL10
HROW
MMCM00
CMT
Backbone
GTH Quad 119
PLL13
CMT
PLL00
Bank 13
HR
MMCM14
Bank 39
HP
UG476_c1_18_060711
XC7VX330T Banks
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Die Level Bank Numbering Overview
XC7VX415T Banks
Figure 1-15 shows the I/O and transceiver banks for the XC7VX415T.
FFG1157 Package
•
All HP banks are fully bonded out.
•
GTH Quads 119, 214, 215, 216, 217, 218, and 219 are not bonded out.
FFG1158 Package
•
HP banks 18, 19, 37, 38, and 39 are not bonded out.
•
GTH Quads are fully bonded out in this package.
FFG1927 Package
All HP banks and the GTH Quads are fully bonded out in this package.
X-Ref Target - Figure 1-15
Left I/O
Column
Banks
GTH Quad 219
Bank 19
HP
Right I/O
Column
Banks
PLL05
PLL15
CMT
CMT
MMCM05
MMCM15
PLL04
GTH Quad 218
GTH Quad 217
GTH Quad 216
GTH Quad 215
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
CMT
Bank 14
HP
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
16 BUFGs
PLL00
GTH Quad 214
16 BUFGs
CMT
MMCM00
MMCM11
Bank 38
HP
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
PLL10
CMT
MMCM10
CMT
Backbone
GTH Quad 119
PLL14
HROW
MMCM01
Bank 39
HP
Clocking
Backbone
CMT
Backbone
Horizontal Center
UG476_c1_19_071411
Figure 1-15:
XC7VX415T Banks
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Chapter 1: Packaging Overview
XC7VX485T Banks
Figure 1-16 shows the I/O and transceiver banks for the XC7VX485T.
FFG1157 Package
•
HP banks 13 and 33 are not bonded out.
•
GTX Quads 113, 119, 213, 214, 215, 216, 217, 218, and 219 are not bonded out.
FFG1158 Package
•
HP banks 13, 18, 19, 33, 37, 38, and 39 are not bonded out.
•
GTX Quads 113 and 213 are not bonded out.
FFG1761 Package
•
All HP banks are fully bonded out in this package.
•
GTX Quads 213, 214, 215, 216, 217, 218, and 219 are not bonded out.
FFG1927 Package
•
HP banks 13 and 33 are not bonded out.
•
All the GTX Quads are fully bonded out in this package.
FFG1930 Package
38
•
All HP banks are fully bonded out in this package.
•
GTX Quads 119, 213, 214, 215, 216, 217, 218, and 219 are not bonded out.
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7 Series FPGAs Packaging
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Die Level Bank Numbering Overview
X-Ref Target - Figure 1-16
Left I/O
Column
Banks
GTX Quad 219
GTX Quad 218
GTX Quad 217
GTX Quad 216
GTX Quad 215
GTX Quad 214
GTX Quad 213
Bank 19
HP
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank 14
HP
Bank 13
HP
Right I/O
Column
Banks
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
PLL05
PLL15
CMT
CMT
MMCM05
MMCM15
PLL04
PLL14
CMT
CMT
MMCM04
16 BUFGs
PLL03
16 BUFGs
CMT
MMCM14
PLL13
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
CMT
PLL10
HROW
CMT
MMCM00
MMCM10
CMT
Backbone
Clocking
Backbone
Bank 39
HP
GTX Quad 119
Bank 38
HP
GTX Quad 118
Bank 37
HP
GTX Quad 117
Bank 36
HP
GTX Quad 116
Bank 35
HP
GTX Quad 115
Bank 34
HP
GTX Quad 114
Bank 33
HP
GTX Quad 113
CMT
Backbone
Horizontal Center
UG476_c1_20_060711
Figure 1-16:
XC7VX485T Banks
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Chapter 1: Packaging Overview
XC7VX550T Banks
Figure 1-17 shows the I/O and transceiver banks for the XC7VX550T.
FFG1158 Package
•
HP banks 12, 13, 18, 19, 32, 33, 37, 38, and 39 are not bonded out.
•
GTH Quads 112, 113, 212, and 213 are not bonded out.
FFG1927 Package
•
HP banks 12, 13, 32, and 33 are not bonded out.
•
All GTH Quads are fully bonded out in this package.
X-Ref Target - Figure 1-17
Left I/O
Column
Banks
GTH Quad 219
GTH Quad 218
GTH Quad 217
GTH Quad 216
GTH Quad 215
GTH Quad 214
GTH Quad 213
GTH Quad 212
Bank 19
HP
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank 14
HP
Bank 13
HP
Bank 12
HP
Right I/O
Column
Banks
PLL05
PLL15
CMT
CMT
MMCM05
MMCM15
PLL04
PLL14
CMT
CMT
MMCM04
MMCM14
PLL05
PLL15
CMT
CMT
MMCM05
MMCM15
PLL04
PLL14
CMT
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
16 BUFGs
PLL02
16 BUFGs
MMCM13
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
CMT
PLL10
HROW
CMT
MMCM00
MMCM10
CMT
Backbone
Clocking
Backbone
Bank 39
HP
GTH Quad 119
Bank 38
HP
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
Bank 33
HP
GTH Quad 114
Bank 32
HP
GTH Quad 112
CMT
Backbone
Horizontal Center
UG475_c1_22_081211
Figure 1-17:
40
XC7VX550T Banks
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UG475 (v1.4) October 17, 2011
Die Level Bank Numbering Overview
XC7VX690T Banks
Figure 1-18 shows the I/O and transceiver banks for the XC7VX690T.
FFG1157 Package
•
HP banks 10, 11, 12, 13, 30, 31, 32, and 33 are not bonded out.
•
GTH Quads 110, 111, 112, 113, 119, 210, 211, 212, 213, 214, 215, 216, 217, 218, and 219
are not bonded out.
FFG1158 Package
•
HP banks 10, 11, 12, 13, 18, 19, 30, 31, 32, 33, 37, 38, and 39 are not bonded out.
•
GTH Quads 110, 111, 112, 113, 210, 211, 212, and 213 are not bonded out.
FFG1761 Package
•
HP banks 10, 11, and 30 are not bonded out.
•
GTH Quads 110, 210, 211, 212, 213, 214, 215, 216, 217, 218, and 219 are not bonded out.
FFG1926 Package
•
HP bank 17 is partially bonded out.
•
HP banks 18, 19, 37, 38, and 39 are not bonded out.
•
GTH Quads 110, 119, 210, and 219 are not bonded out.
FFG1927 Package
•
HP banks 10, 11, 12, 13, 30, 31, 32, and 33 are not bonded out.
•
All GTH Quads are fully bonded out in this package.
FFG1930 Package
•
All HP banks are fully bonded out in this package.
•
GTH Quads 110, 111, 112, 119, 210, 211, 212, 213, 214, 215, 216, 217, 218, and 219 are not
bonded out.
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41
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-18
Left I/O
Column
Banks
GTH Quad 219
GTH Quad 218
GTH Quad 217
GTH Quad 216
GTH Quad 215
GTH Quad 214
GTH Quad 213
GTH Quad 212
GTH Quad 211
GTH Quad 210
Bank 19
HP
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank 14
HP
Bank 13
HP
Bank 12
HP
Bank 11
HP
Bank 10
HP
Right I/O
Column
Banks
PLL09
PLL19
CMT
CMT
MMCM09
MMCM19
PLL08
PLL18
CMT
CMT
MMCM08
MMCM18
PLL07
PLL17
CMT
CMT
MMCM07
MMCM17
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
PLL05
PLL15
CMT
CMT
MMCM05
16 BUFGs
PLL04
16 BUFGs
MMCM15
PLL14
CMT
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
CMT
PLL10
HROW
CMT
MMCM00
MMCM10
CMT
Backbone
Clocking
Backbone
Bank 39
HP
GTH Quad 119
Bank 38
HP
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
Bank 33
HP
GTH Quad 113
Bank 32
HP
GTH Quad 112
Bank 31
HP
GTH Quad 111
Bank 30
HP
GTH Quad 110
CMT
Backbone
Horizontal Center
UG475_c1_22_081211
Figure 1-18:
42
XC7VX690T Banks
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Die Level Bank Numbering Overview
XC7VX980T Banks
Figure 1-19 shows the I/O and transceiver banks for the XC7VX980T.
FFG1926 Package
•
HP bank 17 is partially bonded out.
•
HP banks 18, 37, and 38 are not bonded out.
•
GTH Quads 110 and 210 are not bonded out.
FFG1928 Package
•
HP bank 16 is partially bonded out.
•
HP banks 10, 11, 12, 17, 18, 30, 31, and 32 are not bonded out.
•
All GTH Quads are fully bonded out in this package.
FFG1930 Package
•
All HP banks are fully bonded out in this package.
•
GTH Quads 110, 111, 112, 210, 211, 212, 213, 214, 215, 216, 217, and 218 are not bonded
out.
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43
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-19
Left I/O
Column
Banks
GTH Quad 218
GTH Quad 217
GTH Quad 216
GTH Quad 215
GTH Quad 214
GTH Quad 213
GTH Quad 212
GTH Quad 211
GTH Quad 210
Bank 18
HP
Bank 17
HP
Bank 16
HP
Bank 15
HP
Bank 14
HP
Bank 13
HP
Bank 12
HP
Bank 11
HP
Bank 10
HP
Right I/O
Column
Banks
PLL08
CMT
PLL18
HROW
CMT
MMCM08
MMCM18
PLL07
PLL17
CMT
CMT
MMCM07
MMCM17
PLL06
PLL16
CMT
CMT
MMCM06
MMCM16
PLL05
PLL15
CMT
CMT
MMCM05
BUFGs
PLL04
BUFGs
MMCM15
PLL14
CMT
CMT
MMCM04
MMCM14
PLL03
PLL13
CMT
CMT
MMCM03
MMCM13
PLL02
PLL12
CMT
CMT
MMCM02
MMCM12
PLL01
PLL11
CMT
CMT
MMCM01
MMCM11
PLL00
PLL10
CMT
CMT
MMCM00
MMCM10
Clocking
Backbone
CMT
Backbone
Bank 38
HP
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
Bank 33
HP
GTH Quad 113
Bank 32
HP
GTH Quad 112
Bank 31
HP
GTH Quad 111
Bank 30
HP
GTH Quad 110
CMT
Backbone
Horizontal Center
UG475_c1_23_081211
Figure 1-19:
44
XC7VX980T Banks
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Die Level Bank Numbering Overview
XC7VX1140T Banks
Figure 1-20 shows the I/O and transceiver banks for the XC7VX1140T.
FLG1928 Package
•
HP bank 16 is partially bonded out.
•
HP banks 10, 11, 12, 17, 18, 19, 20, 21, 30, 31, 32, 39, 40, and 41 are not bonded out.
•
All GTH Quads are fully bonded out in this package.
FLG1930 Package
•
HP banks 40 and 41 are not bonded out.
•
GTH Quads 110, 111, 112, 119, 120, 121, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219,
220, and 221 are not bonded out.
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45
Chapter 1: Packaging Overview
X-Ref Target - Figure 1-20
Left I/O
Column Banks
GTH Quad 221
GTH Quad 220
GTH Quad 219
Bank 21
HP
Bank 20
HP
Bank 19
HP
Right I/O
Column Banks
PLL08
HROW
CMT
MMCM08
BUFGs
PLL07
BUFGs
CMT
MMCM07
PLL06
PLL18
CMT
MMCM18
PLL17
CMT
Super
Logic
Region 3
MMCM17
PLL16
CMT
CMT
MMCM06
MMCM16
Bank 41
HP
GTH Quad 121
Bank 40
HP
GTH Quad 120
Bank 39
HP
GTH Quad 119
Bank 38
HP
GTH Quad 118
Bank 37
HP
GTH Quad 117
Bank 36
HP
GTH Quad 116
Bank 35
HP
GTH Quad 115
Bank 34
HP
GTH Quad 114
Bank 33
HP
GTH Quad 113
Bank 32
HP
GTH Quad 112
Bank 31
HP
GTH Quad 111
Bank 30
HP
GTH Quad 110
Interposer
GTH Quad 218
GTH Quad 217
GTH Quad 216
Bank 18
HP
Bank 17
HP
Bank 16
HP
PLL08
PLL18
CMT
CMT
MMCM08
BUFGs
PLL07
BUFGs
CMT
MMCM07
PLL06
MMCM18
PLL17
CMT
Super
Logic
Region 2
MMCM17
PLL16
CMT
CMT
MMCM06
MMCM16
Interposer
GTH Quad 215
GTH Quad 214
GTH Quad 213
Bank 15
HP
Bank 14
HP
Bank 13
HP
PLL05
PLL15
CMT
CMT
MMCM05
BUFGs
PLL04
BUFGs
CMT
MMCM04
PLL03
MMCM15
PLL14
CMT
Super
Logic
Region 1
MMCM14
PLL13
CMT
CMT
MMCM03
MMCM13
Interposer
GTH Quad 212
GTH Quad 211
GTH Quad 210
Bank 12
HP
Bank 11
HP
Bank 10
HP
PLL02
PLL12
CMT
CMT
MMCM02
BUFGs
PLL01
BUFGs
CMT
MMCM01
PLL00
MMCM12
PLL11
CMT
Super
Logic
Region 0
MMCM11
PLL10
CMT
CMT
MMCM00
MMCM10
CMT
Backbone
Clocking
Backbone
Horizontal Center
CMT
Backbone
UG475_c1_24_090511
Figure 1-20:
XC7VX1140T Banks
Note: The figures for some Virtex-7 FPGAs are in development.
46
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Chapter 2
7 Series FPGAs Package Files
About ASCII Package Files
The ASCII files for each package include a comma-separated-values (CSV) version and a
text version optimized for a browser or text editor. Each of the files consists of the
following:
•
Device/Package name (FPGA Family—Device—Package), date and time of creation
•
Eight columns containing data for each pin:
•
•
Pin—Pin location on the package.
•
Pin Name—The name of the assigned pin.
•
Memory Byte Group—Memory byte group between 0 and 3. For more
information on the memory byte group, see UG586, 7 Series FPGAs Memory
Interface Solutions User Guide.
•
Bank—Bank number.
•
VCCAUX Group—Number corresponding to the VCCAUX_IO power supply for the
given pin. VCCAUX is shown for packages with only one VCCAUX group.
•
Super Logic Region—Number corresponding to the super logic region (SLR) in
the devices implemented with stacked silicon interconnect (SSI) technology.
•
I/O Type—CONFIG, HR, HP, or GT (GTP, GTX, GTH, GTZ) depending on the
I/O type. For more information on the I/O type, see UG471, 7 Series FPGAs
SelectIO Resources User Guide.
•
No-Connect—This list of devices is used for migration between devices that have
the same package size and are not connected at that specific pin.
Total number of pins in the package.
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7 Series FPGAs Packaging
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47
Chapter 2: 7 Series FPGAs Package Files
ASCII Pinout Files
This chapter includes the pinout information tables for the following device/packages.
Note: All package files are ASCII files in TXT and CSV file format.
To download all available Artix-7 FPGAs package/device/pinout files click here:
http://www.xilinx.com/support/packagefiles/artix-7-pkgs.htm
Note: Only the available files listed in Table 2-1 are linked and consolidated in the above ZIP file.
Table 2-1:
Device
Artix-7 FPGAs Package/Device Pinout Files
CPG236
CSG225
CSG324
FTG256
FBG484
FBG676
XC7A200T
FBG484
FBG676
XC7A350T
FBG484
FBG676
XC7A8
CPG236
CSG324
FTG256
XC7A15
CPG236
CSG324
FTG256
FGG484
XC7A30T
CSG225
CSG324
FTG256
FGG484
XC7A50T
CSG225
CSG324
FTG256
FGG484
CSG324
FTG256
FGG484
XC7A100T
FGG676
FFG1156
FGG676
FFG1156
To download all available Kintex-7 FPGAs package/device/pinout files click here:
http://www.xilinx.com/support/packagefiles/kintex-7-pkgs.htm
Table 2-2:
Device
Kintex-7 FPGAs Package/Device Pinout Files
FB(G)484
FB(G)676
XC7K70T
FBG484
FBG676
XC7K160T
FB484/
FBG484
FB676/
FBG676
XC7K325T
FB676/
FBG676
FB(G)900
FF(G)676
FF(G)900
FF(G)1156
FF676/
FFG676
FB900/
FBG900
FF676/
FFG676
FF900/
FFG900
FF901/
FFG901
XC7K355T
XC7K410T
FF(G)901
FB676/
FBG676
FB900/
FBG900
FF676/
FFG676
FF900/
FFG900
XC7K420T
FF901/
FFG901
FF1156/
FFG1156
XC7K480T
FF901/
FFG901
FF1156/
FFG1156
48
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
ASCII Pinout Files
To download all available Virtex-7 FPGAs package/device/pinout files click here:
http://www.xilinx.com/support/packagefiles/virtex-7-pkgs.htm
Note: Only the available files listed in Table 2-3 are linked and consolidated in the above ZIP file.
Table 2-3:
Virtex-7 FPGAs Package/Device Pinout Files
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FL(G)
FL(G)
FL(G)
FL(G)
FH(G)
1157
1158
1761
1926
1927
1928
1930
1761
1925
1928
1930
1761
Device
XC7V585T
FF1157/
FFG1157
FF1761/
FFG1761
XC7V1500T
FL1761/
FLG1761
XC7V2000T
FL1925/
FLG1925
XC7VX330T
FF1157/
FFG1157
XC7VX415T
FF1157/ FF1158/
FFG1157 FFG1158
FF1927/
FFG1927
XC7VX485T
FF1157/ FF1158/ FF1761/
FFG1157 FFG1158 FFG1761
FF1927/
FFG1927
XC7VX550T
FF1158/
FFG1158
FF1927/
FFG1927
XC7VX690T
FH1761/
FHG1761
FF1761/
FFG1761
FF1930/
FFG1930
FF1157/ FF1158/ FF1761/ FF1926/ FF1927/
FFG1157 FFG1158 FFG1761 FFG1926 FFG1927
XC7VX980T
FF1926/
FFG1926
FF1930/
FFG1930
FF1928/ FF1930/
FFG1928 FFG1930
XC7VX1140T
FL1928/ FL1930/
FLG1928 FLG1930
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
49
Chapter 2: 7 Series FPGAs Package Files
50
www.BDTIC.com/XILINX
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Chapter 3
Device Diagrams
Summary
This chapter provides pinout, I/O bank, high-performance and high-range I/O bank,
memory groupings, and power and ground placement diagrams for each 7 series FPGA
package/device combination. Some figures for Artix-7 FPGAs and Virtex-7 FPGAs are in
development.
•
Artix-7 FPGAs Device Diagrams Cross-Reference, page 52
•
Kintex-7 FPGAs Device Diagrams Cross-Reference, page 57
•
Virtex-7 FPGAs Device Diagrams Cross Reference, page 97
The figures provide a top-view perspective.
The symbols for the multi-function I/O pins are represented by only one of the available
pin functions; with precedence (by functionality) in this order:
•
ADV_B, FCS_B, FOE_B, MOSI, FWE_B, DOUT_CSO_B, CSI_B, PUDC_B, or RDWR_B
•
RS0–RS1
•
AD0P/AD0N–AD15P/AD15N
•
EMCCLK
•
VRN, VRP, or VREF
•
D00–D31
•
A00–A28
•
DQS, MRCC, or SRCC
For example, a pin description such as IO_L8P_SRCC_12 is represented with a SRCC
symbol, a pin description such as IO_L19N_T3_A09_D25_VREF_14 is represented with a
VREF symbol, and a pin description such as IO_L21N_T3_DQS_A06_D22_14 is
represented with a D0–D31 symbol.
Note: The available files are listed in Table 3-1, Table 3-2, and Table 3-3 are linked. Figures for
some Artix-7 FPGAs and Virtex-7 FPGAs are in development.
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51
Chapter 3: Device Diagrams
Artix-7 FPGAs Device Diagrams
Table 3-1:
Device
Artix-7 FPGAs Device Diagrams Cross-Reference
CPG236
CSG225
CSG324
XC7A8
page 52
XC7A15
page 52
XC7A30T
page 55
XC7A50T
page 55
XC7A100T
page 55
FTG256
FGG484
FGG676
FBG484
FBG676
FFG1156
XC7A200T
XC7A350T
Note: The available files are listed in Table 3-1 are linked. Figures for some Artix-7 FPGAs are in
development.
CSG324 Package—XC7A8 and XC7A15
X-Ref Target - Figure 3-1
8
9
10 11 12 13 14 15 16 17 18
A
1
2
3
4
5
6
7
n
n
n
B
n
n
n
n
D
n
n
C
K
E
A
B
C
n
C
D
I
M
E
O
s
F
F
G
s
G
B
H
H
s
J
s
K
L
S
S
r
S
S
r
L
J
B
B
s
B
B
B
L
M
M
N
N
Y
P
P
R
D
2
s
s
0
1
P
U
B
T
s
U
B
1
2
3
4
5
6
7
8
User I/O Pins
IO_LXXY_#
T
9
V
10 11 12 13 14 15 16 17 18
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
D
DONE_0
S
VREFP_0
VCCAUX
J
DXP_0
S
VREFN_0
VCCINT
L
DXN_0
IO_XX_#
Multi−Function Pins
R
U
V
s
J
K
B
ADV_B
VRN
B
FCS_B
VRP
Y
INIT_B_0
B
FOE_B
VREF
0
M0_0
B
MOSI
D00−D31
1
M1_0
B
FWE_B
A00−A28
2
M2_0
B
DOUT_CSO_B
DQS
P
PROGRAM_B_0
B
CSI_B
MRCC
K
TCK_0
B
PUDC_B
SRCC
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
O
r
RS0−RS1
M
VCCBRAM
n
NC
TMS_0
AD0P/AD0N−AD15P/AD15N
VCCADC_0
EMCCLK
VCCBATT_0
ug475_c3_301_090711
Figure 3-1:
52
CSG324 Package—XC7A8 and XC7A15 Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Artix-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-2
1
2
3
4
5
A
35
B
35 35 35 35
C
35 35
7
8
9
10 11 12 13 14 15 16 17 18
15
35 35
E
35 35 35
F
35
G
35 35 35 35
H
35 35
15 15 15 15
15 15 15 15
35 35 35 35
35 35 35 35
D
15
35 35
15 15 15 15
35
L
34
34 34
34 34 34
T
34
34 34 34 34
V
34 34
1
4
14 14 14 14
34 14 14 14
34 34 34 34
34 34 34 34
3
5
J
K
6
14
7
9
N
14 14
P
14 14 14 14
R
14 14 14 14
14 14 14 14
34 14 14 14
8
L
14 14 14 M
14 14
34 34 34 34
2
H
15 15
14 14 14 14
34 34 34 34
U
G
15 15 14 14
14 14
34 34 34
R
F
15 15 15
14 14 14 14
34
34 34 34 34
P
E
15
15 15 15 15
15
34 34 34 34
M 34 34 34 34
D
15 15 15
34 34
B
C
15 15
15 15
35 35 35
35 35 34
A
15 15 15 15
15 15 15 15
35 35 35 35
J
15
15 15 15
15 15 15 15
35 35 35
35 35 35 35
K
N
6
35 35 35 35
14
T
14 14 14
U
14 14 14 14
V
10 11 12 13 14 15 16 17 18
ug475_c3_302_081211
Figure 3-2:
CSG324 Package—XC7A8 and XC7A15 I/O Banks
X-Ref Target - Figure 3-3
1
2
3
4
5
A
35
B
35 35 35 35
C
35 35
D
8
9
10 11 12 13 14 15 16 17 18
15
35 35
35 35 35 35
35 35 35
F
35
G
35 35 35 35
H
35 35
J
7
15 15 15 15
15 15 15 15
35 35 35 35
E
15
35 35
L
34
15
T
34
34 34 34 34
V
34 34
1
4
14 14 14 14
34 14 14 14
34 34 34 34
34 34 34 34
3
5
K
6
14
7
N
14 14
P
14 14 14 14
R
9
14
T
14 14 14
U
14 14 14 14
14 14 14 14
34 14 14 14
8
L
14 14 14 M
14 14
34 34 34 34
2
J
15 15 14 14
14 14 14 14
34 34 34 34
U
H
15 15
14 14
34 34 34
34 34 34
G
14 14 14 14
34
34 34 34 34
R
F
15 15 15
15 15 15 15
34 34 34 34
34 34
P
E
15
15 15 15
34 34
M 34 34 34 34
D
15 15
35 35 35
B
C
15 15
15 15 15 15
35
A
15 15 15 15
15 15 15 15
35 35 35 35
35 35 34
15
15 15 15
15 15 15 15
35 35 35
35 35 35 35
K
N
6
35 35 35 35
14 14 14 14
V
10 11 12 13 14 15 16 17 18
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_303_081211
Figure 3-3:
CSG324 Package—XC7A8 and XC7A15 Memory Groupings
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7 Series FPGAs Packaging
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www.xilinx.com
53
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-4
1
2
3
4
5
6
A
7
8
9
10 11 12 13 14 15 16 17 18
35
A
15
16
B
B
35
C
15
C
35
D
15
D
E
E
35
F
F
G
35
G
15
15
H
J
35
H
J
34
K
15
K
14
L
L
M
M
34
N
14
N
34
P
14
P
0
R
R
34
T
14
T
34
U
14
34
V
1
2
3
4
5
6
7
8
U
14
9
V
10 11 12 13 14 15 16 17 18
Power Pins
#
VCCO_#
GND
VCCINT
VCCAUX
#
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
GNDADC_0
ug475_c3_304_090711
Figure 3-4:
54
CSG324 Package—XC7A8 and XC7A15 Power and GND Placement
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7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Artix-7 FPGAs Device Diagrams
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T
X-Ref Target - Figure 3-5
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
A
A
B
B
C
C
D
D
E
C
K
I
M
E
O
s
F
F
G
s
G
B
H
H
s
J
s
K
L
S
S
r
S
S
r
L
J
B
B
s
B
B
B
L
M
M
N
N
Y
P
P
R
D
2
s
s
0
1
P
U
R
B
T
T
s
U
U
B
V
1
2
3
4
5
6
7
8
9
User I/O Pins
V
10 11 12 13 14 15 16 17 18
Dedicated Pins
IO_LXXY_#
s
J
K
C
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
D
DONE_0
S
VREFP_0
VCCAUX
J
DXP_0
S
VREFN_0
VCCINT
L
DXN_0
IO_XX_#
Multi−Function Pins
Other Pins
CCLK_0
VCCO_#
B
ADV_B
VRN
GNDADC_0
B
FCS_B
VRP
Y
INIT_B_0
B
FOE_B
VREF
0
M0_0
B
MOSI
D00−D31
1
M1_0
B
FWE_B
A00−A28
2
M2_0
B
DOUT_CSO_B
DQS
P
PROGRAM_B_0
B
CSI_B
MRCC
K
TCK_0
B
PUDC_B
SRCC
I
TDI_0
TDO_0
U
RDWR_B
O
r
RS0−RS1
M
VCCBRAM
n
NC
TMS_0
AD0P/AD0N−AD15P/AD15N
VCCADC_0
EMCCLK
VCCBATT_0
ug475_c3_305_090711
Figure 3-5:
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T Pinout Diagram
X-Ref Target - Figure 3-6
1
2
3
4
A
35
B
35 35 35 35
C
35 35
5
7
8
35 35 35 35
E
35 35 35
F
35
G
35 35 35 35
H
35 35
9
10 11 12 13 14 15 16 17 18
16 16 16 15
35 35 16 16
35 35 35 35
D
15 15 15 15
15 15 15 15
16 16 16 15
35 35 16 16
15 15 15 15
35
L
34
34 34
34 34 34
T
34
34 34 34 34
V
34 34
1
4
14 14 14 14
34 14 14 14
34 34 34 34
34 34 34 34
3
5
J
K
6
14
7
34 14 14 14
8
9
N
14 14
P
14 14 14 14
R
14 14 14 14
14 14 14 14
L
14 14 14 M
14 14
34 34 34 34
2
H
15 15
14 14 14 14
34 34 34 34
U
G
15 15 14 14
14 14
34 34 34
R
F
15 15 15
14 14 14 14
34
34 34 34 34
P
E
15
15 15 15 15
15
34 34 34 34
M 34 34 34 34
D
15 15 15
34 34
B
C
15 15
15 15
35 35 35
35 35 34
A
15 15 15 15
15 15 15 15
35 35 35 35
J
15
15 15 15
15 15 15 15
35 35 35
35 35 35 35
K
N
6
35 35 35 35
14
T
14 14 14
U
14 14 14 14
V
10 11 12 13 14 15 16 17 18
ug475_c3_306_081211
Figure 3-6:
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T I/O Banks
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55
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-7
1
2
3
4
A
35
B
35 35 35 35
C
35 35
D
5
8
F
35
G
35 35 35 35
H
35 35
9
10 11 12 13 14 15 16 17 18
16 16 16 15
35 35 16 16
35 35 35 35
35 35 35
J
7
35 35 35 35
E
15 15 15 15
15 15 15 15
16 16 16 15
35 35 16 16
L
34
T
34
34 34 34 34
V
34 34
1
14 14 14 14
34 14 14 14
34 34 34 34
34 34 34 34
3
4
5
6
14
7
N
14 14
P
14 14 14 14
R
9
14
T
14 14 14
U
14 14 14 14
14 14 14 14
34 14 14 14
8
L
14 14 14 M
14 14
34 34 34 34
2
J
K
14 14 14 14
34 34 34 34
U
H
15 15
15 15 14 14
14 14
34 34 34
34 34 34
G
14 14 14 14
34
34 34 34 34
R
F
15 15 15
15 15 15 15
15
34 34 34 34
34 34
P
E
15
15 15 15
34 34
M 34 34 34 34
D
15 15
35 35 35
B
C
15 15
15 15 15 15
35
A
15 15 15 15
15 15 15 15
35 35 35 35
35 35 34
15
15 15 15
15 15 15 15
35 35 35
35 35 35 35
K
N
6
35 35 35 35
V
14 14 14 14
10 11 12 13 14 15 16 17 18
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_307_081211
Figure 3-7:
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T Memory Groupings
X-Ref Target - Figure 3-8
1
2
3
4
5
6
A
7
8
9
10 11 12 13 14 15 16 17 18
35
A
15
16
B
B
35
C
15
C
35
D
15
D
E
E
35
F
F
G
35
G
15
15
H
J
35
H
J
34
K
15
K
14
L
L
M
M
34
N
14
N
34
P
14
P
0
R
R
34
T
14
T
34
U
14
34
V
1
2
3
4
5
6
7
8
U
14
9
V
10 11 12 13 14 15 16 17 18
Power Pins
#
VCCO_#
GND
VCCINT
VCCAUX
#
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
GNDADC_0
ug475_c3_308_090711
Figure 3-8:
56
CSG324 Package—XC7A30T, XC7A50T, and XC7A100T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
Kintex-7 FPGAs Device Diagrams
Table 3-2:
Device
Kintex-7 FPGAs Device Diagrams Cross-Reference
FB(G)484
FB(G)676
XC7K70T
page 57
page 60
XC7K160T
page 57
page 63
XC7K325T
FB(G)900
FF(G)676
FF(G)900
FF(G)901
FF(G)1156
page 70
page 63
page 66
page 70
page 73
XC7K355T
page 77
XC7K410T
page 63
page 66
page 70
page 73
XC7K420T
page 81
page 89
XC7K480T
page 85
page 93
FBG484 Package—XC7K70T and XC7K160T
X-Ref Target - Figure 3-9
1
A
2
3
4
5
6
V
E
V
E
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
A
r
B
C
B
C
s
D
V
E
G
V
E
C
H
G
1
0
E
r
B
B
s
E
F
F
V
V
J
2
B
s
B
H
J
K
I
K
L
M
Y
M
P
P
s
G
O
s
N
S
S
B
S
S
s
L
J
B
K
B
L
B
M
U
N
P
D
R
R
T
T
s
U
U
V
V
s
W
W
Y
Y
AA
AA
AB
AB
2
User I/O Pins
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
V
1
s
D
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
MGTHRXP
O
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_13_090511
Figure 3-9:
FBG484 Package—XC7K70T and XC7K160T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
57
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-10
1
2
A
3
4
5
6
7
115 115
B 115 115
115 115
D 115 115
115 115
F 115 115
G
10 11 12 13 14 15 16 17 18 19 20 21 22
15 15 15 15
16 16 15 15
16 16 16
16 16
115 115
16 16 16 16
115 115
16
H 115 115
15 15 15 15
16 16 16
L
34
16 16 16 15
N
R
34 34 34 34
T
34
U
34 34 34
V
33 33
33 33 33 33
34 34 34 34
34 34 34 34
AA 34
2
3
33 33 33 33
4
5
6
7
8
N
P
R
T
13 13 13
13 13 13 13
13
U
V
13 13 13 13 W
13 13 13 13
33 13 13 13
33 33 33 33
9
14 14
13 13 13 13
13 13 13 13
33 33 33 13
33 33 33 33
14
14 14 14 14
13 13 13 13
33 33 13 13
33 33 33 33
33 33 33 33
34 34 33 33
AB 34 34 34
1
33 33 33 33
34 34 33 33
33 33 13 13
33 33 33 33
J
K
14 14 14 M
13 14 14 14
34 33 33 33
H
L
14 14 14 14
14 14
34 34 34 33
W 34 34
14
14 14
14 14 14 14
34 34
F
14 14 14 14
14 14 14
34 34 34 34
34 34
Y
14
E
14 14 14 G
15 14 14 14
34
P
D
14 14
14 14 14 14
34 34 34
M 34 34 34
15 15 15 15
15 14 14 14
15 15
34 34 34 34
C
15 15 15 14
J
K
B
15
15 15 15 15
16 16 15 15
16 16 16 16
15 15 15
15 15 15 15
16 16 16 15
A
15 15 15 15
15 15 15 15
15 15 15 15
16 16 16 15
115 115
E
9
16
115 115
C
8
16 16 16 16
13 13
Y
AA
13 13 13 13
13 13 13 AB
13 13 13 13
10 11 12 13 14 15 16 17 18 19 20 21 22
ug475_c3_14_011111
Figure 3-10:
FBG484 Package—XC7K70T and XC7K160T I/O Banks
X-Ref Target - Figure 3-11
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
A
16 16 16 16
B
16
C
16 16 16
D
15 15 15 15
16 16 15 15
15 15 15 15
16 16 16 15
E
16 16
F
16 16 16 16
G
16
H
16 16 16
34 34 34 34
L
34
16 16 16 15
N
R
34 34 34 34
T
34
U
34 34 34
V
Y
33 33
33 33 33 33
34 34 34 34
2
3
33 33 33 33
4
5
6
7
8
14 14
N
P
R
T
13 13 13
13 13 13 13
13
U
V
13 13 13 13 W
13 13 13 13
33 13 13 13
33 33 33 33
9
14
13 13 13 13
13 13 13 13
33 33 33 13
33 33 33 33
J
K
L
14 14 14 14
13 13 13 13
33 33 13 13
33 33 33 33
33 33 33 33
34 34 33 33
AB 34 34 34
1
33 33 33 33
34 34 33 33
33 33 13 13
33 33 33 33
H
14 14 14 M
13 14 14 14
34 33 33 33
34 34 34 34
AA 34
14 14
14 14 14 14
14 14
34 34 34 33
W 34 34
14
14 14 14 14
34 34
F
14 14 14 14
14 14 14
34 34 34 34
34 34
E
14 14 14 G
15 14 14 14
14
34
P
D
14 14
14 14 14 14
34 34 34
M 34 34 34
15 15 15 15
15 14 14 14
15 15
K
C
15 15 15 14
J
B
15
15 15 15 15
16 16 15 15
16 16 16 16
15 15 15
15 15 15 15
15 15 15 15
16 16 16 15
A
15 15 15 15
15 15 15 15
13 13
13 13 13 13
13 13 13 13
Y
AA
13 13 13 AB
10 11 12 13 14 15 16 17 18 19 20 21 22
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_15_052311
Figure 3-11:
58
FBG484 Package—XC7K70T and XC7K160T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-12
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
A
A
15
15
B
C
B
16
16
D
15
D
15
E
E
16
F
14
16
G
14
H
0
J
J
14
K
K
14
L
L
34
M
M
34
0
14
N
14
P
P
34
R
R
34
T
33
13
33
U
13
33
V
V
33
W
33
Y
13
33
AA
13
34
AB
1
2
3
4
13
5
6
7
8
9
T
U
13
34
W
F
G
15
H
N
C
15
Y
AA
AB
10 11 12 13 14 15 16 17 18 19 20 21 22
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_16_052311
Figure 3-12: FBG484 Package—XC7K70T and XC7K160T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
59
Chapter 3: Device Diagrams
FBG676 Package—XC7K70T
X-Ref Target - Figure 3-13
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
V
B
B
V
C
E
C
V
D
B
C
B
E
E
B
B
B
D
U
E
B
G
F
F
V
G
H
E
Y
E
D
H
V
J
s
J
s
K
s
L
V
M
E
V
V
K
P
2
R
s
1
M
P
I
T
r
G
V
N
O
B
M
N
S
S
S
s
P
L
J
R
T
0
V
n
n
W
n
n
Y
n
n
n
n
n
AA
n
n
n
AB
n
AC
n
AD
n
AE
AF
n
3
4
User I/O Pins
5
6
7
8
9
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
V
n
W
n
n
Y
n
n
n AB
n
n
n
n
AA
n
n
U
n
n
n
n
n
n
n
n
n
n AC
n
n AD
n
n AE
n
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Transceiver Pins
E
MGTAVCC_G#
V
MGTAVTT_G#
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
IO_XX_#
Multi−Function Pins
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
V
2
L
s
B
s
1
K
s
S
U
s
r
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
SRCC
V
VCCO_#
GNDADC_0
B
PUDC_B
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_05_090511
Figure 3-13:
60
FBG676 Package—XC7K70T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-14
1
2
3
4
5
6
7
8
116 116
A
B 116 116
9
116 116
D 116 116
16
116 116
F 116 116
16 16 16
116 116
G
H 115 115
J
16 16 16 16
115 115
16 16
115 115
K 115 115
L
16
16 15 15 15
16 16 16 16
16 16
15 15 15 15
16 16 15 15
N
115 115
15 15
115 115
R
115 115
T
34
U
34 34
V
34 34 34 34
W 34
34 34 33 33
AB 34 34
34 34 34 34
1
2
3
4
U
V
6
Y
33 33
AA
7
8
9
AB
33 33 33
AC
33
AD
33 33 33 33
AE
33 33 33 33
5
T
13 13 13 13
13 13
W
33 33 33 33
34 34 33 33
34 34 34 34
AF
P
R
13 13
33 33 33 33
34 33 33 33
AE 34 34 34
13 13 13 13
33 33 33 33
34 34 34 33
AD 34
N
13
13 13 13 13
33 33
33 33 33 33
AC 34 34 34 34
L
33 33 33 33
34 34 34 34
AA
J
K
13 13 13 M
13 13 13 13
13 13 13 13
13 13
34 33 33 33
34 34 34 34
34 34 34
Y
33
H
14
13 13
14 14 13 13
13 13 13 13
34 34 34 34
F
G
14 14 14 14
13 13 13 13
13 13 13
E
14 14 14
14 14 14 14
13 13 13 13
13
D
14 14
15 14 14 14
15 15 15 15
P 115 115
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
115 115
M 115 115
C
15 15 14 14
115 115
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
116 116
15 15 15 14
16 16 15 15
16 16 16 16
16 16 16 16
116 116
E
16 16 16 16
16 16 16 16
116 116
C
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16
33 33
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ug475_c3_06_032911
Figure 3-14:
FBG676 Package—XC7K70T I/O Banks
X-Ref Target - Figure 3-15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16
A
16 16 16 16
B
16 16 16 16
C
16
D
16 16 16 16
16 16 16 16
E
16 16 16
G
16 16 16 16
H
16 16
J
16
16 15 15 15
16 16 16 16
16 16
M
15 15
N
13 13 13 13
P
13
R
13 13 13
T
34
34 34
V
34 34 34 34
W 34
Y
AB 34 34
34 34 34 33
AC 34 34 34 34
AD 34
AF
1
2
3
4
5
13 13
13 13 13 13
8
9
N
P
R
T
V
W
Y
AA
33 33
AB
AC
33
AD
33 33 33 33
AE
33 33 33 33
7
J
K
U
13 13
33 33 33
33 33 33 33
6
13 13 13 13
33 33 33 33
34 34 33 33
34 34 34 34
13
13 13 13 13
33 33 33 33
34 33 33 33
34 34 34 34
AE 34 34 34
13 13 13 13
33 33
33 33 33 33
H
L
33 33 33 33
34 34 33 33
34 34 34 34
13 13
G
13 13 13 M
13 13 13 13
13 13
34 33 33 33
34 34 34 34
34 34 34
AA
33
14
14 14 14 14
14 14 13 13
13 13 13 13
E
F
14 14 14
14 14 14 14
13 13 13 13
34 34 34 34
D
14 14
15 14 14 14
15 15 15 15
U
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
L
C
15 15 14 14
15 15 15 15
16 16 15 15
K
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
F
15 15 15 14
16 16 15 15
AF
33 33
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_07_052311
Figure 3-15:
FBG676 Package—XC7K70T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
61
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
16
B
A
14
16
B
15
C
16
D
16
E
D
14
16
E
15
F
15
G
14
16
H
C
14
16
H
15
J
J
15
K
K
13
L
0
L
14
M
M
15
N
N
13
P
0
0
T
0
U
R
13
0
13
13
34
V
33
34
32
33
33
3
4
5
6
AE
12 AF
32
7
8
9
AD
12
32
34
2
AC
12
33
1
AB
32
32
34
AF
AA
12
34
AE
Y
12
33
AB
AD
W
32
AA 34
AC
V
12
33
T
U
12
W
Y
P
13
R
F
G
14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Power Pins
#
VCCO_#
VCCINT
MGTVCCAUX
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
VCCAUX_IO_G#
MGTAVCC
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_08_052311
Figure 3-16:
62
FBG676 Package—XC7K70T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FBG676 Package—XC7K160T, XC7K325T, and XC7K410T
X-Ref Target - Figure 3-17
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
V
B
B
V
C
E
C
B
V
D
B
E
E
B
B
D
U
E
B
G
F
F
V
G
H
E
Y
E
D
H
V
J
s
J
s
K
s
L
V
M
E
V
V
P
2
R
T
1
r
s
M
P
I
r
K
G
V
N
O
K
s
B
s
L
M
B
N
S
S
S
S
s
P
L
J
R
T
0
U
s
U
s
V
V
W
W
s
Y
Y
AA
AA
AB
AB
AC
AC
AD
AD
AE
AE
AF
AF
1
2
3
4
User I/O Pins
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Transceiver Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
C
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
DONE_0
S
VREFP_0
VCCAUX
S
VREFN_0
VCCINT
MGTVCCAUX_G#
MGTAVTTRCAL
J
DXP_0
G
MGTRREF
L
DXN_0
D
Other Pins
CCLK_0
V
Multi−Function Pins
Dedicated Pins
V
s
B
C
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
MGTHRXP
O
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_21_090511
Figure 3-17:
FBG676 Package—XC7K160T, XC7K325T, and XC7K410T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
63
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-18
1
2
3
4
5
6
7
8
116 116
A
B 116 116
116 116
D 116 116
16
116 116
F 116 116
116 116
H 115 115
115 115
16 16
16
16 15 15 15
16 16 16 16
16 16
15 15 15 15
16 16 15 15
115 115
15 15
13
115 115
R
34
T
U
34 34
V
34 34 34 34
W 34
Y
AD 34
34 34 34 34
AE 34 34 34
AF
2
3
4
5
33 33 33 33
33 33 33 33
6
7
8
9
12
12 12
12 12 12 12
P
R
U
V
Y
AA
12 12 12 AB
12 AC
12 12 12 12
12 12 12 12 AD
32 32 32 12
12 12 AE
32 12 12 12
32 32 32 32
N
12 12 12 12 W
32 32 12 12
32 32 32 32
33 33 32 32
J
K
T
12 12 12
12 12 12 12
32 32 32 32
33 32 32 32
13 13
12 12 12 12
32 32 32 32
32 32 32 32
33 33 33 32
33 33 33 33
34 34 33 33
34 34 34 34
1
33 33 33 33
34 33 33 33
32 32 32 32
33 33 32 32
13
13 13 13 13
13 13 12 12
32 32 12 12
H
L
13 13 13 13
13 13 13 13
32 32 32 32
32 32 32 32
33 33 33 33
33 33 33 33
34 34 34 33
AC 34 34 34 34
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AB 34 34
13 13
34 33 33 33
34 34 34 34
34 34 34
AA
33
G
13 13 13 M
13 13 13 13
13 13 13 13
34 34 34 34
13 13
14 14 13 13
13 13 13 13
13 13 13
14
14 14 14 14
13 13 13 13
E
F
14 14 14
14 14 14 14
13 13 13 13
P 115 115
D
14 14
15 14 14 14
15 15 15 15
115 115
N
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
115 115
L
M 115 115
C
15 15 14 14
115 115
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
115 115
J
K 115 115
16 16 16 16
16 16 16
15 15 15 14
16 16 15 15
16 16 16 16
116 116
G
16 16 16 16
16 16 16 16
116 116
E
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16 16
116 116
C
9
16 16 16
AF
12 12 12 12
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ug475_c3_22_011111
Figure 3-18: FBG676 Package—XC7K160T, XC7K325T, and XC7K410T I/O Banks
X-Ref Target - Figure 3-19
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16
A
16 16 16 16
B
16 16 16 16
C
16
D
16 16 16 16
16 16 16 16
E
16 16 16
G
16 16 16 16
H
16 16
J
16
16 15 15 15
16 16 16 16
16 16
K
13 13 13 13
P
13
R
13 13 13
34
34 34
V
34 34 34 34
W 34
Y
AD 34
34 34 34 34
AE 34 34 34
AF
2
3
4
5
33 33 33 33
33 33 33 33
6
7
33 32 32 32
8
9
12 12
U
V
Y
AA
12 AC
12 12 12 12
12 12 12 12 AD
32 12 12 12
32 32 32 32
P
R
12 12 12 AB
32 32 12 12
32 32 32 32
33 33 32 32
12
12 12 12 12
32 32 32 12
N
12 12 12 12 W
12 12 12 12
32 32 32 32
J
K
T
12 12 12
12 12 12 12
32 32 12 12
32 32 32 32
33 33 33 32
33 33 33 33
34 34 33 33
34 34 34 34
1
33 33 33 33
34 33 33 33
13 13
13 13 13 13
13 13 12 12
32 32 32 32
H
L
13
13 13 13 13
13 13 13 13
32 32 32 32
33 33 32 32
G
13 13 13 M
13 13 13 13
32 32 32 32
32 32 32 32
33 33 33 33
33 33 33 33
34 34 34 33
AC 34 34 34 34
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AB 34 34
13 13
34 33 33 33
34 34 34 34
34 34 34
AA
33
13 13
14 14 13 13
13 13 13 13
13 13 13 13
34 34 34 34
14
14 14 14 14
13 13 13 13
E
F
14 14 14
14 14 14 14
15 15 15 15
15 15
N
T
D
14 14
15 14 14 14
M
U
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
L
C
15 15 14 14
15 15 15 15
16 16 15 15
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
F
15 15 15 14
16 16 15 15
12 12 AE
12 12 12 12
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_23_052311
Figure 3-19:
64
FBG676 Package—XC7K160T, XC7K325T, and XC7K410T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-20
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
16
B
A
14
16
B
15
C
16
D
16
D
14
16
E
15
E
15
F
14
16
G
H
C
14
14
16
H
15
J
J
15
K
K
13
L
0
L
14
M
M
15
N
N
13
P
0
0
T
0
U
R
13
0
13
13
34
V
33
32
34
12
33
12
33
3
4
5
6
AE
32
7
8
9
AD
32
34
2
AC
12
33
1
AB
32
34
AF
AA
32
34
AE
Y
12
33
AB
AD
W
32
AA 34
AC
V
12
33
T
U
12
W
Y
P
13
R
F
G
12 AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_24_052311
Figure 3-20:
FBG676 Package—XC7K160T, XC7K325T, and XC7K410T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
65
Chapter 3: Device Diagrams
FBG900 Package—XC7K325T and XC7K410T
X-Ref Target - Figure 3-21
1
2
3
4
5
6
7
8
9
A
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
Y
B
V
E
C
B
C
C
V
D
V
D
E
E
V
F
K
V
E
G
M
V
H
O
V
J
E
s
s
F
s
s
s
G
s
E
I
H
E
P
K
E
D
J
V
K
V
L
L
V
M
V
N
s
r
r
B
B
M
B
N
V
P
V
E
R
s
V
V
T
V
U
V
S
S
S
L
J
s
P
R
B
T
B
U
V
V
S
B
V
W
V
V
U
B
V
B
G
W
s
Y
s
Y
s
AA
AB
AA
2
1
AB
0
AC
AC
AD
AD
AE
s
AF
AF
AG
AG
AH
AH
AJ
AJ
AK
AK
2
3
4
5
6
User I/O Pins
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
1
s
AE
s
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
MGTHRXP
O
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_25_090511
Figure 3-21:
66
FBG900 Package—XC7K325T and XC7K410T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-22
1
2
3
4
5
6
118 118
A
B 118 118
D 118 118
18
18 18 18
T 115 115
15 15 15 15
15
14 14 14
115 115
14 14
116 116
V 115 115
Y 115 115
14
115 115
33 33
115 115
33
34 33 33 33
AB
AC 34 34
34 34 34 34
AD 34 34 34 34
AF 34 34 34
AH 34 34
1
34 34 34 34
2
3
4
5
6
8
9
33 33 32 32
14 14
13 13 13
Y
13 AA
13 13 AC
13 13 13 13
AD
13 13 13 AE
12 13 13 13
13 AF
13 13 13 13 AG
12 12 13 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
32 32 12 12
T
12 12 12 13
32 12 12 12
32 32 32 32
R
U
12 12 13 13
12 12 12 12
32 32 32 12
33 32 32 32
33 33 33 33
34 33 33 33
7
32 32 32 32
33 33 32 32
33 33 33 33
34 34 34 33
32 32 12 12
N
14
13 13 13 13
12 12 12 12
L
14 14 14 14
14 13 13 13
12 12 12 13
32 12 12 12
K
P
14 14 14
12 12 13 13
12 12 12 12
32 32 32 32
33 32 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AJ 34 34 34 34
AK 34
33 33 33 33
34 34 34 34
34 34 34 34
AG
33 33 33 32
15 15
14 14 14 14
14 14 14 14
32 32 32 12
32 32 32 32
15
14 14 14 14
14 14 14 14
32 32 12 12
32 32 32 32
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
33 32 32 32
33 33 33 33
J
14 14 14 14
14 14 14 14
14 14 14 14
115 115
H
15 15 15 15 M
15 15 15 15
14 14 14 14
115 115
115 115
15 16
15 15 15
15 15 15 15
15 15 15 14
115 115
F
G
15 15 15 15
15 15 15 15
E
16 16 16 16
15 15 15 15
15 15 15 15
15 15
116 116
115 115
AE 34
18 18 17 17
B
C
16
16 16 16 16
15 15 15 15
17 17 17 15
A
D
16 16 16
16 16 16 16
17 16 16 16
17 17 17 17
18 17 17 17
18 18 18 18
116 116
116 116
AA
18 18 18 17
18 18 18 18
116 116
116 116
W
18 18
117 117
17 17 17 17
116 116
P 116 116
U
18 18 18 18
16 16
16 16 16 16
16 16 16 16
17 17 17 16
16
16 16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
16 16 16 16
17 16 16 16
17 17 17 17
17 17 17 17
18 18 18 18
18 18 18
117 117
116 116
R
18
17 17 17 16
17 17 17 17
18 18 17 17
18 18 18 18
117 117
M 116 116
N
18 18
117 117
117 117
K 117 117
18 17 17 17
18 18 18 18
117 117
H 117 117
L
18 18 18
118 118
117 117
J
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
118 118
F 117 117
G
9
118 118
118 118
E
8
118 118
118 118
C
7
118 118
13 13 AH
13 13 13 13
12 12 12 13
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ug475_c3_26_011111
Figure 3-22:
FBG900 Package—XC7K325T and XC7K410T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
67
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-23
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
18 18 18
B
18 17 17 17
18 18 18 18
C
18 18
D
18 18 18 18
E
18
F
18 18 18
G
17 17 17 16
17 17 17 17
18 18 17 17
17 17 17 17
17 17 17 17
18 18 18 18
18 18 18 18
H
18 18
J
18 18 18 18
K
18
L
18 18 18
17 17 17 17
18 18 18 17
18 18 18 18
17 17 17 15
18 18 17 17
15 15 15 15
15 15
N
15 15 15 15
P
15
R
14 14 14
T
V
14 14 14 14
W
14
Y
33 33
33
AB
34 33 33 33
AC 34 34
34 34 34 34
AD 34 34 34 34
AE 34
AF 34 34 34
AG
AH 34 34
1
34 34 34 34
2
3
4
5
6
34 33 33 33
7
8
9
33 32 32 32
33 33 33 33
33 33 32 32
32 32 12 12
13 13 AC
AD
13 13 13 13
13 13 13 AE
13 AF
12 13 13 13
13 13 13 13 AG
12 12 12 12
12 12 13 13
12 12 12 12
Y
13 AA
13 13 13 13 AB
12 12 12 13
32 12 12 12
V
W
13 13 13
12 12 13 13
12 12 12 12
32 32 32 32
14 14
13 13 13 13
12 12 12 12
32 32 32 12
T
U
14 13 13 13
12 12 12 13
32 32 12 12
32 32 32 32
33 33 32 32
33 33 33 33
34 34 34 33
32 32 32 32
33 32 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AJ 34 34 34 34
AK 34
33 33 33 33
34 34 34 34
34 34 34 34
33 33 33 32
R
14
12 12 13 13
32 12 12 12
N
14 14 14 14
14 14 14 14
12 12 12 12
L
P
14 14 14
14 14 14 14
14 14 14 14
32 32 32 12
32 32 32 32
15 15
14 14 14 14
14 14 14 14
32 32 12 12
32 32 32 32
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
33 32 32 32
33 33 33 33
15
K
15 15 15 15 M
15 15 15 15
14 14 14 14
H
J
15 15 15
14 14 14 14
14 14
15 16
15 15 15 15
15 15 15 15
U
AA
F
G
15 15 15 15
15 15 15 14
E
16 16 16 16
15 15 15 15
M
B
C
16
16 16 16 16
15 15 15 15
A
D
16 16 16
16 16 16 16
17 16 16 16
17 17 17 17
18 17 17 17
16 16
16 16 16 16
16 16 16 16
17 17 17 16
16
16 16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
16 16 16 16
17 16 16 16
13 13 AH
13 13 13 13
12 12 12 13
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_27_052311
Figure 3-23:
68
FBG900 Package—XC7K325T and XC7K410T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-24
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
C
C
16
18
17
E
16
17
F
F
16
18
G
17
H
17
J
H
16
18
K
J
15
18
K
15
L
17
L
15
M
M
15
N
N
15
P
15
14
R
0
T
14
U
U
14
V
0
W
0
33
AB
0
32
33
32
34
2
32
33
3
4
5
AG
13
32
34
1
AF
12
12
34
AK
6
7
8
9
AE
13
33
AJ
13 AD
12
34
AH
AC
32
AG 34
AB
13
12
34
AF
AA
13
33
AE
Y
12
32
34
AD
W
14
33
AC
V
14
0
Y
AA
P
R
14
T
D
E
16
18
G
B
16
18
D
A
16
17
13
AH
AJ
AK
12
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_28_052311
Figure 3-24:
FBG900 Package—XC7K325T and XC7K410T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
69
Chapter 3: Device Diagrams
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T
X-Ref Target - Figure 3-25
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
A
V
B
B
V
C
E
C
V
D
B
E
E
B
B
B
D
U
E
B
G
F
F
V
G
H
E
Y
E
D
H
V
J
s
J
s
K
s
L
V
E
M
V
V
P
2
R
K
1
r
s
M
P
I
T
r
G
V
N
K
s
B
s
L
M
B
N
S
S
S
S
P
L
J
R
O
s
T
0
U
s
U
s
V
V
W
W
s
Y
Y
AA
AA
AB
AB
AC
AC
AD
AD
AE
AE
AF
AF
2
3
4
User I/O Pins
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
1
s
B
C
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
MGTHRXP
O
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_29_090511
Figure 3-25:
70
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-26
1
2
3
4
5
6
7
116 116
A
B 116 116
8
9
116 116
D 116 116
16
116 116
F 116 116
16 16 16
116 116
G
H 115 115
16 16 16 16
115 115
16 16
115 115
J
K 115 115
16
16 15 15 15
16 16 16 16
16 16
15 15 15 15
16 16 15 15
115 115
15 15
13
115 115
R
34
T
U
34 34
V
34 34 34 34
W 34
Y
34 34 33 33
34 34 34 34
AB 34 34
AD 34
34 34 34 34
AE 34 34 34
1
2
3
4
5
33 33 33 33
33 33 33 33
6
7
8
9
12
12 12
12 12 12 12
U
V
32 32 32 12
Y
AA
12 12 12 AB
12 12 12 12
12 AC
12 12 12 12 AD
32 12 12 12
32 32 32 32
P
R
12 12 12 12 W
32 32 12 12
32 32 32 32
33 33 32 32
N
T
12 12 12
12 12 12 12
32 32 32 32
33 32 32 32
13 13
12 12 12 12
32 32 32 32
32 32 32 32
33 33 33 32
33 33 33 33
34 34 33 33
34 34 34 34
AF
33 33 33 33
34 33 33 33
32 32 32 32
33 33 32 32
13
13 13 13 13
13 13 12 12
32 32 12 12
J
K
L
13 13 13 13
13 13 13 13
32 32 32 32
32 32 32 32
33 33 33 33
33 33 33 33
34 34 34 33
AC 34 34 34 34
33 33 32 32
33 33 33 33
H
13 13 13 M
13 13 13 13
13 13 13 13
13 13
34 33 33 33
34 34 34 34
34 34 34
AA
33
13 13
14 14 13 13
13 13 13 13
34 34 34 34
14
G
14 14 14 14
13 13 13 13
13 13 13
E
F
14 14 14
14 14 14 14
13 13 13 13
P 115 115
D
14 14
15 14 14 14
15 15 15 15
115 115
N
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
115 115
L
M 115 115
C
15 15 14 14
115 115
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
116 116
15 15 15 14
16 16 15 15
16 16 16 16
16 16 16 16
116 116
E
16 16 16 16
16 16 16 16
116 116
C
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16
12 12 AE
12 12 12 12
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
ug475_c3_30_011111
Figure 3-26:
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T I/O Banks
X-Ref Target - Figure 3-27
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
16 16 16
A
16 16 16 16
B
16 16 16 16
C
16
D
16 16 16 16
16 16 16 16
E
16 16 16
G
16 16 16 16
H
16 16
J
16
16 15 15 15
16 16 16 16
16 16
K
N
13 13 13 13
P
13
R
13 13 13
34
34 34
V
34 34 34 34
W 34
Y
AB 34 34
AE 34 34 34
AF
2
3
4
5
33 33 33 33
33 33 33 33
6
7
8
9
12
12 12
U
V
Y
AA
12 AC
12 12 12 12
12 12 12 12 AD
32 12 12 12
32 32 32 32
P
R
12 12 12 AB
32 32 12 12
32 32 32 32
33 33 32 32
N
12 12 12 12 W
12 12 12 12
32 32 32 12
J
K
T
12 12 12
12 12 12 12
32 32 32 32
33 32 32 32
13 13
12 12 12 12
32 32 12 12
32 32 32 32
33 33 33 32
33 33 33 33
34 34 33 33
34 34 34 34
1
33 33 33 33
34 33 33 33
34 34 34 34
13
13 13 13 13
13 13 12 12
32 32 32 32
H
L
13 13 13 13
13 13 13 13
32 32 32 32
33 33 32 32
G
13 13 13 M
13 13 13 13
32 32 32 32
32 32 32 32
33 33 33 33
33 33 33 33
34 34 34 33
AC 34 34 34 34
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AD 34
13 13
34 33 33 33
34 34 34 34
34 34 34
AA
33
13 13
14 14 13 13
13 13 13 13
13 13 13 13
34 34 34 34
14
14 14 14 14
13 13 13 13
E
F
14 14 14
14 14 14 14
15 15 15 15
15 15
T
D
14 14
15 14 14 14
M
U
14 14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
L
C
15 15 14 14
15 15 15 15
16 16 15 15
B
14
15 14 14 14
15 15 15 15
A
14 14 14
14 14 14 14
15 15 15 14
15 15 15 15
16 16 16 15
14 14 14 14
15 14 14 14
15 15 15 15
16 16 15 15
16 16 16 16
F
15 15 15 14
16 16 15 15
12 12 AE
12 12 12 12
AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_31_052311
Figure 3-27:
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
71
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-28
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
16
B
A
14
16
B
15
16
C
D
14
16
D
14
16
E
15
E
15
F
14
16
G
H
C
14
16
H
15
J
F
G
J
15
K
K
13
L
0
L
14
M
M
15
N
N
13
P
0
R
0
T
0
U
R
13
0
13
13
34
V
33
32
34
12
33
12
33
3
4
5
6
AE
32
7
8
9
AD
32
34
AF
AC
12
33
2
AB
32
34
1
AA
32
34
AE
Y
12
33
AB
AD
W
32
AA 34
AC
V
12
33
T
U
12
W
Y
P
13
12 AF
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_32_052311
Figure 3-28:
72
FFG676 Package—XC7K160T, XC7K325T, and XC7K410T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG900 Package—XC7K325T and XC7K410T
X-Ref Target - Figure 3-29
1
2
3
4
5
6
7
8
9
A
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
Y
B
V
E
C
B
C
C
V
D
V
D
E
E
V
F
K
V
E
G
V
H
O
V
J
E
s
M
s
F
s
s
s
G
s
E
I
H
E
P
K
E
D
J
V
K
V
L
L
V
M
V
N
s
r
r
B
B
B
N
V
P
V
E
R
s
V
V
T
V
U
V
S
S
S
S
L
J
P
B
s
R
B
T
B
U
V
V
V
W
V
V
B
W
s
Y
s
Y
s
AA
2
1
AB
0
AC
AC
AD
AD
AE
s
AE
s
AF
AF
AG
AG
AH
AH
AJ
AJ
AK
AK
2
3
4
5
6
User I/O Pins
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
1
s
U
V
B
G
AA
AB
M
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
TDO_0
VCCO_#
GNDADC_0
U
RDWR_B
MGTHRXP
O
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_33_090511
Figure 3-29:
FFG900 Package—XC7K325T and XC7K410T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
73
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-30
1
2
3
4
5
6
118 118
A
B 118 118
D 118 118
18
18 18 18
T 115 115
15 15 15 15
15
14 14 14
115 115
14 14
116 116
V 115 115
Y 115 115
14
115 115
33 33
115 115
33
34 33 33 33
AB
AC 34 34
34 34 34 34
AD 34 34 34 34
AF 34 34 34
AG
AH 34 34
1
34 34 34 34
2
3
4
5
6
8
9
33 33 32 32
14 14
13 13 13
Y
13 AA
13 13 AC
13 13 13 13
AD
13 13 13 AE
12 13 13 13
13 AF
13 13 13 13 AG
12 12 13 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
32 32 12 12
T
12 12 12 13
32 12 12 12
32 32 32 32
R
U
12 12 13 13
12 12 12 12
32 32 32 12
33 32 32 32
33 33 33 33
34 33 33 33
7
32 32 32 32
33 33 32 32
33 33 33 33
34 34 34 33
32 32 12 12
N
14
13 13 13 13
12 12 12 12
L
14 14 14 14
14 13 13 13
12 12 12 13
32 12 12 12
K
P
14 14 14
12 12 13 13
12 12 12 12
32 32 32 32
33 32 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AJ 34 34 34 34
AK 34
33 33 33 33
34 34 34 34
34 34 34 34
33 33 33 32
15 15
14 14 14 14
14 14 14 14
32 32 32 12
32 32 32 32
15
14 14 14 14
14 14 14 14
32 32 12 12
32 32 32 32
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
33 32 32 32
33 33 33 33
J
14 14 14 14
14 14 14 14
14 14 14 14
115 115
H
15 15 15 15 M
15 15 15 15
14 14 14 14
115 115
115 115
15 16
15 15 15
15 15 15 15
15 15 15 14
115 115
F
G
15 15 15 15
15 15 15 15
E
16 16 16 16
15 15 15 15
15 15 15 15
15 15
116 116
115 115
AE 34
18 18 17 17
B
C
16
16 16 16 16
15 15 15 15
17 17 17 15
A
D
16 16 16
16 16 16 16
17 16 16 16
17 17 17 17
18 17 17 17
18 18 18 18
116 116
116 116
AA
18 18 18 17
18 18 18 18
116 116
116 116
W
18 18
117 117
17 17 17 17
116 116
P 116 116
U
18 18 18 18
16 16
16 16 16 16
16 16 16 16
17 17 17 16
16
16 16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
16 16 16 16
17 16 16 16
17 17 17 17
17 17 17 17
18 18 18 18
18 18 18
117 117
116 116
R
18
17 17 17 16
17 17 17 17
18 18 17 17
18 18 18 18
117 117
M 116 116
N
18 18
117 117
117 117
K 117 117
18 17 17 17
18 18 18 18
117 117
H 117 117
L
18 18 18
118 118
117 117
J
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
118 118
F 117 117
G
9
118 118
118 118
E
8
118 118
118 118
C
7
118 118
13 13 AH
13 13 13 13
12 12 12 13
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ug475_c3_34_011111
Figure 3-30:
74
FFG900 Package—XC7K325T and XC7K410T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-31
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
18 18 18
B
18 17 17 17
18 18 18 18
C
18 18
D
18 18 18 18
E
18
F
18 18 18
G
18 18 17 17
18 18 18 18
18 18
17 17 17 17
18 18 18 17
J
18 18 18 18
K
18
L
18 18 18
18 18 17 17
15 15 15 15
15 15
N
15 15 15 15
P
15
R
14 14 14
T
15 15 15 15
14 14 14 14
V
14 14 14 14
W
14
Y
33 33
33
AB
34 33 33 33
AC 34 34
34 34 34 34
AD 34 34 34 34
AE 34
AF 34 34 34
AG
AH 34 34
1
34 34 34 34
2
3
4
33 33 33 33
34 34 34 33
5
6
8
9
33 33 32 32
14 14
13 13 13
Y
13 AA
13 13 AC
AD
13 13 13 13
13 13 13 AE
13 AF
12 13 13 13
13 13 13 13 AG
12 12 13 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
32 32 12 12
T
12 12 12 13
32 12 12 12
32 32 32 32
R
U
12 12 13 13
12 12 12 12
32 32 32 12
33 32 32 32
33 33 33 33
34 33 33 33
7
32 32 32 32
33 33 32 32
N
14
13 13 13 13
12 12 12 13
32 32 12 12
L
14 14 14 14
14 13 13 13
12 12 12 12
K
P
14 14 14
12 12 13 13
32 12 12 12
32 32 32 32
33 32 32 32
33 33 33 33
34 34 33 33
34 34 34 34
AJ 34 34 34 34
AK 34
33 33 33 33
34 34 34 34
34 34 34 34
33 33 33 32
15 15
14 14 14 14
12 12 12 12
32 32 32 12
32 32 32 32
15
14 14 14 14
14 14 14 14
32 32 12 12
32 32 32 32
33 33 32 32
33 33 33 33
34 34 33 33
34 34 34 34
33 32 32 32
33 33 33 33
J
14 14 14 14
14 14 14 14
H
15 15 15 15 M
14 14 14 14
14 14
15 16
15 15 15
15 15 15 15
15 15 15 15
U
AA
F
G
15 15 15 15
15 15 15 14
E
16 16 16 16
15 15 15 15
M
B
C
16
16 16 16 16
15 15 15 15
17 17 17 15
A
D
16 16 16
16 16 16 16
17 16 16 16
17 17 17 17
18 17 17 17
18 18 18 18
16 16
16 16 16 16
16 16 16 16
17 17 17 16
16
16 16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
16 16 16 16
17 16 16 16
17 17 17 17
17 17 17 17
18 18 18 18
H
17 17 17 16
17 17 17 17
13 13 AH
13 13 13 13
12 12 12 13
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_35_052311
Figure 3-31:
FFG900 Package—XC7K325T and XC7K410T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
75
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-32
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
C
C
16
18
17
E
16
17
F
F
16
18
G
17
H
17
J
H
16
18
K
J
15
18
K
15
L
17
L
15
M
M
15
N
N
15
P
15
14
R
0
T
14
U
U
14
V
0
W
0
33
AB
0
32
33
32
34
2
32
4
5
13
13
33
3
AG
32
34
1
6
7
8
AF
12
12
34
AK
9
AE
13
33
AJ
13 AD
12
34
AH
AC
32
AG 34
AB
13
12
34
AF
AA
13
33
AE
Y
12
32
34
AD
W
14
33
AC
V
14
0
Y
AA
P
R
14
T
D
E
16
18
G
B
16
18
D
A
16
17
AH
AJ
AK
12
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_36_052311
Figure 3-32:
76
FFG900 Package—XC7K325T and XC7K410T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG901 Package—XC7K355T
X-Ref Target - Figure 3-33
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B
V
C
V
V
E
V
V
D
E
E
E
E
F
n
n
n
n
n
n
n
V
n
V
G
V
E
H
Y
J
E
V
L
K
n
B
n
n
C
n
n
n
n
n
n
n
n
C
n
n
O
n
D
V
n
F
n
G
n
n
n
E
E
s
n
H
s
s
M
s
J
B
K
L
s
M
B
E
P
G
V
R
r
V
E
T
U
E
V
N
B
V
N
r
P
s
S
S
U
S
S
B
L
J
B
B
U
B
V
E
s
V
Y
E
AB
n
V
AA
V
AC
P
V
E
n
n
E
n
n
D
2
1
0
AD
n
n
n
n
n
AE
AF
V
AG
n
V
E
n
AH
V
n
V
V
n
V
1
2
3
n
V
4
5
6
7
User I/O Pins
8
n
n
n
n
E
AJ
AK
n
n
n
n
E
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
E
n
n
n
n
AB
AC
AD
AE
s
AF
AG
n
n
n
Y
n
n
n
W
s
n
n
n
V
B
s
s
AA
n
n
n
n
n
n
n
n
n
n
AH
n
AK
AJ
n
n
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Transceiver Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
V
MGTVCCAUX_G#
V
MGTAVTTRCAL
G
MGTRREF
Multi−Function Pins
R
T
s
V
W
s
A
n
V
K
I
M
n
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
D
DONE_0
S
VREFP_0
VCCAUX
J
DXP_0
S
VREFN_0
VCCINT
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_37_090511
Figure 3-33:
FFG901 Package—XC7K355T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
77
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-34
1
2
A
3
4
5
6
116 116
B 116 116
C
D 116 116
116 116
J
115 115
T 114 114
115 115
17 17
17 17 17 17
17 17
15
114 114
14 14
114 114
113 113
Y 113 113
14
113 113
113 113
AB 113 113
AC
113 113
12
AD 113 113
AE
112 112
AF 113 113
AG
112 112
AH 112 112
AJ
12
112 112
AK 112 112
1
2
3
4
5
6
12
7
8
9
14 14
V
W
13 13 13
Y
13 AA
13 13 13 13 AB
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
13 13 13 13 AG
12 12 12 12
12 12 12 13
12 12 12 12
112 112
T
12 12 12 12
12 12
112 112
R
U
13 13 13 13
12 12 12 12
112 112
N
14
13 13 13 13
12 12 13 13
12 12
L
14 14 14 14
13 13 13 13
12 12 12 12
K
P
14 15 14
12 13 13 13
12 12 12
112 112
15 15
14 14 14 14
14 14 14 13
12 12 12 12
112 112
15
14 14 14 14
14 14 14 14
12 12
113 113
J
15 15 15 15
14 14 14 14
14 14 14 14
14 14 14
H
15 15 15 15 M
15 15 15 15
14 14 14 14
14 14 14 14
16 16
15 15 15
15 15 15 15
15 15 15 15
14 14 14 14
113 113
F
G
16 16 16 16
15 15 15 15
15 15 15 15
15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
A
D
16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
114 114
V 114 114
AA
17 17 17
16 16
16 16 16 16
17 16 16 16
17 17 17 17
117 117
115 115
114 114
W
17
16
16 16 16 16
16 16 16 16
17 17 17 16
17 17 17 17
117 117
114 114
114 114
U
17 17
117 117
16 16 16 16
17 17 16 16
17 17 17 17
117 117
115 115
114 114
R
117 117
115 115
P 114 114
17 17 17 17
17 17 17
115 115
M 115 115
N
17
116 116
115 115
K 115 115
L
117 117
117 117
116 116
H 115 115
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
117 117
116 116
F 115 115
9
117 117
116 116
G
8
116 116
116 116
E
7
117 117
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ug475_c3_38_052311
Figure 3-34:
78
FFG901 Package—XC7K355T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-35
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
17 17 17
C
17 17 17 17
17 17 17 17
D
17 17
E
17 17 17 17
F
17
G
17 17 17
H
17 17 17 17
17 17
17 17 17 17
L
17 17
M
15 15 15 15
N
15
P
15 15 15
14 14 14 14
T
14 14
14 14 14 14
V
14
W
14 14 14
AB
12
AC
12 12 12
AF
12 12 12 12
AG
12
12 12 12 12
AK
12
3
4
5
6
7
8
9
V
W
13 13 13
Y
13 AA
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
12 12
2
14 14
13 13 13 13 AB
13 13 13 13 AG
12 12 12 12
AJ
1
T
12 12 12 12
AH
R
U
13 13 13 13
12 12
N
14
13 13 13 13
12 12 13 13
AE
L
14 14 14 14
13 13 13 13
12 12 12 12
K
P
14 15 14
12 13 13 13
12 12 12 12
AD
15 15
14 14 14 14
14 14 14 13
12 12
15
14 14 14 14
14 14 14 14
AA
J
15 15 15 15
14 14 14 14
14 14 14 14
H
15 15 15 15 M
15 15 15 15
14 14 14 14
Y
16 16
15 15 15
15 15 15 15
15 15 15 15
U
F
G
16 16 16 16
15 15 15 15
15 15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
A
D
16 16 16
16 16 16 16
17 17 16 16
J
16 16
16 16 16 16
17 16 16 16
17 17 17 17
16
16 16 16 16
16 16 16 16
17 17 17 16
K
R
16 16 16 16
17 17 16 16
12 12 12 13
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_39_052311
Figure 3-35:
FFG901 Package—XC7K355T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
79
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-36
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
A
16
18
B
16
C
C
17
D
17
E
16
18
F
18
F
16
G
G
17
H
17
J
0
K
H
16
18
J
16
0
K
17
L
15
L
15
M
M
15
N
N
15
P
15
R
15
14
T
T
14
U
14
V
14
V
14
W
W
13
Y
Y
12
AA
11
AA
13
11
AB
13
AC
AC
12
AD
13 AD
12
AE
11
AF
AE
13
11
AF
12
AG
AG
12
AH
11
AJ
13
11
AK
12
2
3
4
5
6
7
8
9
AH
AJ
AK
12
1
P
R
14
U
AB
D
E
16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_40_052311
Figure 3-36:
80
FFG901 Package—XC7K355T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG901 Package—XC7K420T
X-Ref Target - Figure 3-37
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B
V
C
V
V
E
V
D
V
E
E
E
E
F
n
n
n
n
n
n
n
V
n
V
G
V
E
H
Y
J
E
V
L
B
n
n
C
n
n
n
n
n
n
C
n
n
O
n
K
n
n
n
A
n
D
n
F
n
G
n
n
n
n
V
E
H
s
s
M
E
s
V
K
I
M
n
s
J
B
K
L
s
M
B
E
P
G
V
R
r
V
E
T
U
E
V
N
B
V
N
r
P
s
S
S
U
S
S
B
L
J
B
T
s
U
V
W
B
V
E
s
V
AA
E
AB
s
P
V
W
s
Y
AA
V
AC
V
B
s
V
Y
R
B
E
D
2
1
0
s
AB
s
AC
AD
AD
AE
E
AF
AF
V
AG
V
E
AH
V
V
1
2
3
V
4
5
6
User I/O Pins
E
AH
E
AK
AJ
V
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
AK
AG
V
E
AJ
s
AE
s
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_41_090511
Figure 3-37:
FFG901 Package—XC7K420T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
81
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-38
1
2
A
3
4
5
6
116 116
B 116 116
C
D 116 116
116 116
J
115 115
T 114 114
17
17 17 17
115 115
17 17
17 17 17 17
17 17
15
114 114
14 14
114 114
113 113
Y 113 113
14
113 113
113 113
AB 113 113
AC
11 11
113 113
112 112
AD 113 113
AE
AF 113 113
111 111
112 112
112 112
AH 112 112
AJ
112 112
AK 112 112
2
4
5
6
111 111
11 11
7
8
9
11
11 11 11
14 14
13 13 13
Y
13 AA
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
13 13 13 13 AG
12 12 12 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
11 11 11 12
T
12 12 12 12
11 11 12 12
11 11 11 11
R
U
13 13 13 13
12 12 12 12
11 11 11 12
11 11 11 11
111 111
111 111
11 11 12 12
11 11 11 11
111 111
111 111
112 112
3
11 11 11
N
14
13 13 13 13
12 12 12 12
L
14 14 14 14
13 13 13 13
12 12 13 13
11 12 12 12
K
P
14 15 14
12 13 13 13
12 12 12 12
11 11 11 11
111 111
111 111
111 111
112 112
1
11
15 15
14 14 14 14
14 14 14 13
11 11 11 12
11 11 11 11
112 112
112 112
AG
11 11
111 111
15
14 14 14 14
14 14 14 14
11 11 12 12
113 113
J
15 15 15 15
14 14 14 14
14 14 14 14
14 14 14
H
15 15 15 15 M
15 15 15 15
14 14 14 14
14 14 14 14
16 16
15 15 15
15 15 15 15
15 15 15 15
14 14 14 14
113 113
F
G
16 16 16 16
15 15 15 15
15 15 15 15
15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
A
D
16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
16 16
16 16 16 16
17 16 16 16
17 17 17 17
117 117
114 114
V 114 114
AA
117 117
16
16 16 16 16
16 16 16 16
17 17 17 16
17 17 17 17
115 115
114 114
W
17 17
117 117
114 114
114 114
U
117 117
16 16 16 16
17 17 16 16
17 17 17 17
115 115
114 114
R
117 117
115 115
P 114 114
17 17 17 17
17 17 17
115 115
M 115 115
N
17
116 116
115 115
K 115 115
L
117 117
117 117
116 116
H 115 115
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
117 117
116 116
F 115 115
9
117 117
116 116
G
8
116 116
116 116
E
7
117 117
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ug475_c3_42_052311
Figure 3-38:
82
FFG901 Package—XC7K420T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-39
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
17 17 17
C
17 17 17 17
17 17 17 17
D
17 17
E
17 17 17 17
F
17
G
17 17 17
H
17 17 17 17
17 17
17 17 17 17
L
17 17
M
15 15 15 15
N
15
P
15 15 15
14 14 14 14
T
14 14
14 14 14 14
V
14
W
14 14 14
Y
AB
11 11
11 11 11 11
AD
11
AE
11 11 11
AF
11 11 11 11
AG
11 11
AH
11 11 11 11
AJ
11
AK
11 11 11
1
2
3
4
5
6
7
8
9
14 14
13 13 13
Y
13 AA
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
13 13 13 13 AG
12 12 12 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
11 11 11 12
T
12 12 12 12
11 11 12 12
11 11 11 11
R
U
13 13 13 13
12 12 12 12
11 11 11 12
N
14
13 13 13 13
12 12 13 13
11 11 12 12
L
14 14 14 14
13 13 13 13
12 12 12 12
K
P
14 15 14
12 13 13 13
11 12 12 12
11 11 11 11
15 15
14 14 14 14
14 14 14 13
11 11 11 12
15
14 14 14 14
12 12 12 12
J
15 15 15 15
14 14 14 14
14 14 14 14
11 11
AC
15 15 15 15
14 14 14 14
H
15 15 15 15 M
14 14 14 14
11 11 12 12
AA
16 16
15 15 15
15 15 15 15
15 15 15 15
U
F
G
16 16 16 16
15 15 15 15
15 15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
A
D
16 16 16
16 16 16 16
17 17 16 16
J
16 16
16 16 16 16
17 16 16 16
17 17 17 17
16
16 16 16 16
16 16 16 16
17 17 17 16
K
R
16 16 16 16
17 17 16 16
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_43_052311
Figure 3-39:
FFG901 Package—XC7K420T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
83
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-40
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
A
16
18
B
16
C
C
17
D
17
E
16
18
F
18
F
16
G
G
17
H
17
J
0
K
H
16
18
J
16
0
K
17
L
15
L
15
M
M
15
N
N
15
P
15
R
15
14
T
T
14
U
14
V
14
V
14
W
W
13
Y
Y
12
AA
11
AA
13
11
AB
13
AC
AC
12
AD
13 AD
12
AE
11
AF
AE
13
11
AF
12
AG
AG
12
AH
11
AJ
13
11
AK
12
2
3
4
5
6
7
8
9
AH
AJ
AK
12
1
P
R
14
U
AB
D
E
16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_44_052311
Figure 3-40:
84
FFG901 Package—XC7K420T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG901 Package—XC7K480T
X-Ref Target - Figure 3-41
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
A
V
B
V
V
C
E
V
C
E
D
E
B
V
E
E
D
V
E
s
V
F
G
F
V
G
E
Y
H
E
J
V
L
K
C
s
H
O
V
V
K
I
M
E
s
s
J
B
K
s
L
B
M
G
B
V
E
N
V
P
N
r
V
R
M
E
T
E
U
r
s
S
S
U
S
S
B
L
J
P
B
B
s
T
U
V
V
B
V
W
E
s
V
Y
P
V
V
W
s
Y
AA
V
AB
AC
B
s
s
V
E
AA
E
D
2
1
0
s
AB
s
AC
AD
AD
E
AE
s
AE
V
AF
AG
AF
V
E
AG
V
E
AH
V
AJ
1
2
3
5
AH
E
AK
AJ
V
4
E
V
V
AK
6
7
User I/O Pins
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Transceiver Pins
Dedicated Pins
Other Pins
IO_LXXY_#
E
MGTAVCC_G#
C
CCLK_0
S
VP_0
GND
IO_XX_#
V
MGTAVTT_G#
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
V
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
s
R
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
Multi−Function Pins
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_45_090511
Figure 3-41:
FFG901 Package—XC7K480T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
85
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-42
1
2
A
3
4
5
6
116 116
B 116 116
C
D 116 116
116 116
J
117 117
18 18
18 17 17 17
18 18 18 18
18
17 17
115 115
15
114 114
T 114 114
114 114
V 114 114
14 14
113 113
114 114
113 113
Y 113 113
14
113 113
113 113
AB 113 113
AC
11 11
113 113
112 112
AD 113 113
AE
AF 113 113
111 111
112 112
112 112
AH 112 112
AJ
112 112
AK 112 112
2
4
5
6
111 111
11 11
7
8
9
11
11 11 11
14 14
13 13 13
Y
13 AA
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
13 13 13 13 AG
12 12 12 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
11 11 11 12
T
12 12 12 12
11 11 12 12
11 11 11 11
R
U
13 13 13 13
12 12 12 12
11 11 11 12
11 11 11 11
111 111
111 111
11 11 12 12
11 11 11 11
111 111
111 111
112 112
3
11 11 11
N
14
13 13 13 13
12 12 12 12
L
14 14 14 14
13 13 13 13
12 12 13 13
11 12 12 12
K
P
14 15 14
12 13 13 13
12 12 12 12
11 11 11 11
111 111
111 111
111 111
112 112
1
11
15 15
14 14 14 14
14 14 14 13
11 11 11 12
11 11 11 11
112 112
112 112
AG
11 11
111 111
15
14 14 14 14
14 14 14 14
11 11 12 12
113 113
J
15 15 15 15
14 14 14 14
14 14 14 14
14 14 14
H
15 15 15 15 M
15 15 15 15
14 14 14 14
14 14 14 14
16 16
15 15 15
15 15 15 15
15 15 15 15
14 14 14 14
114 114
114 114
F
G
16 16 16 16
15 15 15 15
15 15 15 15
15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
17 17 17 17
A
D
16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
16 16
16 16 16 16
17 16 16 16
17 17 17 17
16
16 16 16 16
16 16 16 16
17 17 17 16
17 17 17 17
18 18 18 17
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
18 18 18
115 115
114 114
AA
18
117 117
115 115
114 114
W
18 18 18 18
115 115
P 114 114
U
117 117
17 17 17 17
18 17 17 17
115 115
115 115
R
117 117
116 116
M 115 115
N
18 18 18 18 17
18 18
117 117
115 115
K 115 115
L
117 117
117 117
116 116
H 115 115
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
117 117
116 116
F 115 115
9
117 117
116 116
G
8
116 116
116 116
E
7
117 117
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ug475_c3_46_052311
Figure 3-42:
86
FFG901 Package—XC7K480T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-43
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
18 18 18 18 17
B
18 18
C
18 18 18 18
D
18
E
18 18 18
F
17 17 17 17
18 17 17 17
17 17 17 17
18 18 17 17
G
18 18
H
18 18 18 18
J
18
18 17 17 17
L
17 17
M
15 15 15 15
N
15
P
15 15 15
R
14 14 14 14
T
14 14
14 14 14 14
V
14
W
14 14 14
Y
AB
11 11
11 11 11 11
AD
11
AE
11 11 11
AF
11 11 11 11
AG
11 11
AH
11 11 11 11
AJ
11
AK
11 11 11
1
2
3
4
5
6
7
8
9
T
Y
13 AA
13 13 AC
AD
12 13 13 13
13 13 13 AE
13 AF
12 12 13 13
13 13 13 13 AG
12 12 12 13
12 12 12 12
V
W
13 13 13 13 AB
12 12 12 12
11 11 11 12
14 14
13 13 13
12 12 12 12
11 11 12 12
11 11 11 11
R
U
13 13 13 13
12 12 12 12
11 11 11 12
N
14
13 13 13 13
12 12 13 13
11 11 12 12
L
14 14 14 14
13 13 13 13
12 12 12 12
K
P
14 15 14
12 13 13 13
11 12 12 12
11 11 11 11
15 15
14 14 14 14
14 14 14 13
11 11 11 12
15
14 14 14 14
12 12 12 12
J
15 15 15 15
14 14 14 14
14 14 14 14
11 11
AC
15 15 15 15
14 14 14 14
H
15 15 15 15 M
14 14 14 14
11 11 12 12
AA
16 16
15 15 15
15 15 15 15
15 15 15 15
U
F
G
16 16 16 16
15 15 15 15
15 15 15 15
E
16 16 16 16
17 15 15 15
15 15 15 15
B
C
16
16 16 16 16
17 17 17 16
17 17 17 17
A
D
16 16 16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 17 17
K
16 16
16 16 16 16
17 16 16 16
17 17 17 17
16
16 16 16 16
16 16 16 16
17 17 17 16
17 17 17 17
18 18 18 17
16 16 16 16
17 17 16 16
13 13 AH
12 13 13 13
12 12 12 12
AJ
13 13 13 AK
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_47_052311
Figure 3-43:
FFG901 Package—XC7K480T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
87
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-44
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
17
B
A
16
18
B
16
C
C
17
D
17
E
16
18
F
18
F
16
G
G
17
H
17
J
0
K
H
16
18
J
16
0
K
17
L
15
L
15
M
M
15
N
N
15
P
15
R
15
14
T
T
14
U
14
V
14
V
14
W
W
13
Y
Y
12
AA
11
AB
AA
13
11
AB
13
AC
AC
12
AD
13 AD
12
AE
11
AF
AE
13
11
AF
12
AG
AG
12
AH
11
AJ
13
11
12
AK
2
3
4
5
6
7
8
9
AH
AJ
AK
12
1
P
R
14
U
D
E
16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_48_052311
Figure 3-44:
88
FFG901 Package—XC7K480T Power and GND Placement
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG1156 Package—XC7K420T
X-Ref Target - Figure 3-45
1
2
3
4
5
6
A
7
8
n
n
B
V
C
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
n
n
n
V
n
n
V
V
n
n
V
V
D
9
n
E
n
F
V
G
E
n
n
n
n
E
n
C
n
n
E
O
n
n
n
n
n
n
n
n
n
n
n
K
n
I
n
E
V
H
n
n
E
M
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
B
n
n
C
n
n
n
n
n
n
n
n
n
A
n
D
n
E
n
F
n
n
G
n
s
H
E
J
s
J
K
K
V
E
s
V
L
V
E
N
s
L
B
M
V
M
N
P
P
V
R
E
G
s
V
V
T
E
U
V
V
W
S
S
S
S
L
J
E
s
B
B
E
s
B
E
s
V
V
s
s
B
AA
AB
AC
s
AD
AE
AF
AF
V
AG
E
V
AH
E
AJ
E
Y
s
D
1
2
0
s
AG
AH
AJ
E
AK
V
AL
V
AK
V
AL
V
AM
E
V
AN
P
AM
V
AN
E
AP
2
3
4
5
6
7
8
User I/O Pins
9
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
1
s
V
s
V
E
AE
T
Y
B
U
V
R
W
AB
AD
B
B
AA
AC
r
U
V
Y
r
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_49_090511
Figure 3-45:
FFG1156 Package—XC7K420T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
89
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-46
1
2
A
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
117 117
B 117 117
17 17 17
117 117
117 117
C
D 117 117
E
17 17
117 117
G
17
117 117
117 117
H 116 116
117 117
116 116
116 116
J
K 116 116
116 116
L
17 17 17
116 116
M 116 116
17
116 116
P 115 115
15 15
115 115
115 115
R
T 115 115
115 115
115 115
U
V 114 114
AB 114 114
14
113 113
14 14
AD 113 113
113 113
AF 113 113
AG
12
113 113
113 113
AH 113 113
112 112
112 112
AJ
AK 113 113
111 111
112 112
AL
AN
AP 112 112
2
4
5
6
111 111
8
9
11
11 11 11 11
11 11
11 11 11 11
13 13 AF
13 13 13 AH
12 13 13 13
13 AJ
13 13 13 13 AK
12 13 13 13
12 12 12 12
AG
13 13 13 13
12 12 12 13
13 13 AL
AM
13 13 13 13
12 12 13 13
12 12 12 12
13 AD
13 13 13 13 AE
12 12 12 12
11 12 12 12
AB
13 13 13 AC
12 12 13 13
11 12 12 12
11 11 11 12
11 11 11 11
Y
14 14 AA
12 13 13 13
12 12 12 12
11 11 11 12
V
14 W
14 14 14 14
12 12 12 12
T
U
14 14 14 14
12 12 12 12
11 11 12 12
11 11 11 11
11 11 11
111 111
111 111
7
11 11
11 11 11 11
111 111
111 111
112 112
3
111 111
111 111
11 11 11 11
11 11 11 11
111 111
112 112
112 112
1
111 111
112 112
AM 112 112
11 11 11 11
15 15
14 14 14
14 14 14 13
12 12 12
112 112
R
14 14 14 14
12 12 14 14
113 113
AE
P
15 15 15 15
14 14 14 14
14 14 14 14
N
15
15 15 15 15
14 14 14 14
14 14 14
L
M
15 15 15
14 14 14 14
114 114
16 16
15 15 15 15
14 14 14 14
114 114
113 113
AC
15 14
114 114
114 114
J
K
15 15 15 15
15 15 15 15
H
16
15 15 15 15
15 15 15 15
114 114
16 16 16
15 15 15 15
15 15 15
114 114
Y 114 114
AA
115 115
115 115
114 114
W
15
F
G
16 16 16 16
17 17 16 16
15 15 15 15
115 115
E
16 16
16 16 16 16
17 17 17 15
115 115
N
D
16 16 16 16
17 17 17 17
17 17 17
115 115
16
17 17 16 16
17 17 17 17
116 116
C
16 16 16 16
17 16 16 16
17 17 17 17
B
16 16 16
16 16 16 16
17 17 17 16
17 17 17
A
16
16 16 16 16
17 17 16 16
17 17 17 17
117 117
F 116 116
17 16 16 16
17 17 17 17
13
13 AN
AP
13 13 13 13 13
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ug475_c3_50_052311
Figure 3-46:
90
FFG1156 Package—XC7K420T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-47
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
17 17 17
B
17 16 16 16
17 17 17 17
C
17 17
D
17 17 17 17
E
17
F
17 17 17
G
17 17 16 16
17 17 17
17 17 17 17
17
L
17 17 17
M
15 15
15 15 15 15
R
15
T
15 15 15
V
15 14
14 14 14 14
Y
14
AD
12 12 14 14
AE
12
AH
11 11 11 11
AJ
11 11
AK
11 11 11 11
AL
11
AM
11 11 11
AN
11 11 11 11
11 11 11 11
AP
11 11
1
2
3
4
5
6
7
8
9
11 11 11 11
13 AD
13 13 AF
AG
13 13 13 13
13 13 13 AH
13 AJ
12 13 13 13
13 13 13 13 AK
13 13 AL
12 13 13 13
AM
13 13 13 13
12 12 13 13
12 12 12 12
AB
13 13 13 13 AE
12 12 12 12
11 12 12 12
Y
13 13 13 AC
12 12 12 13
12 12 12 12
V
14 W
14 14 AA
12 12 13 13
11 12 12 12
T
U
14 14 14
12 13 13 13
12 12 12 12
11 11 11 12
15 15
14 14 14 14
12 12 12 12
11 11 11 12
R
14 14 14 14
12 12 12 12
11 11 12 12
11 11 11 11
P
15 15 15 15
14 14 14 13
12 12 12
N
15
14 14 14 14
14 14 14 14
11 11 11 11
15 15 15
14 14 14 14
14 14
L
M
15 15 15 15
14 14 14 14
AC
11 11 11 11
16 16
15 15 15 15
14 14 14 14
14 14 14
AF
J
K
15 15 15 15
W
H
16
15 15 15 15
15 15 15 15
AG
16 16 16
15 15 15 15
15 15 15 15
F
G
16 16 16 16
17 17 16 16
P
AB
E
16 16
16 16 16 16
17 17 17 17
N
AA
D
16 16 16 16
17 17 17 15
U
16
17 17 16 16
J
C
16 16 16 16
17 16 16 16
K
B
16 16 16
16 16 16 16
17 17 17 16
17 17 17 17
H
A
16
16 16 16 16
13
13 AN
13 13 13 13 13
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_51_052311
Figure 3-47:
FFG1156 Package—XC7K420T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
91
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-48
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
18
B
C
B
16
18
C
17
D
18
E
F
17
0
H
E
16
18
G
D
16
18
F
A
16
18
17
0
16
18
H
16
J
J
17
K
K
17
L
L
16
M
M
17
N
N
15
P
P
15
R
R
15
T
T
15
U
15
15
V
W
14
Y
14
AA
AA
14
AB
AB
14
AC
AC
14
AD
AD
13
AE
AE
13
AF
AF
12
AG
13 AG
12
AH
11
AJ
AJ
12
11
AK
12
AL
11
AM
AM
13
11
12
AP
AL
13
11
AN
AH
13
11
AK
AN
13
AP
12
1
2
3
4
5
6
7
8
9
U
V
14
W
Y
G
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_52_052311
Figure 3-48: FFG1156 Package—XC7K420T Power and GND Placement
92
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
FFG1156 Package—XC7K480T
X-Ref Target - Figure 3-49
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
E
B
V
C
V
V
V
V
V
D
E
E
V
E
C
O
E
K
I
V
H
D
E
E
F
G
B
C
F
s
G
M
s
s
H
E
J
s
J
K
K
V
E
s
V
L
V
E
N
s
L
B
M
V
M
N
P
P
V
R
E
G
s
V
V
T
E
U
V
V
W
E
S
S
S
S
L
J
s
B
B
T
B
V
W
E
s
E
s
U
V
V
V
s
s
B
AA
AB
s
AC
s
AD
V
E
AE
Y
B
AB
AD
B
R
B
AA
AC
r
U
V
Y
r
AE
AF
AF
AG
V
AH
E
V
E
AJ
E
AK
s
D
1
2
0
AG
s
AH
AJ
AK
E
V
AL
V
V
AL
V
AM
E
V
AN
P
AM
V
AN
E
AP
2
3
4
5
6
7
8
User I/O Pins
9
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
C
Other Pins
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Dedicated Pins
CCLK_0
V
1
s
Y
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_53_090511
Figure 3-49:
FFG1156 Package—XC7K480T Pinout Diagram
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
93
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-50
1
2
A
3
4
5
6
117 117
B 117 117
C
D 117 117
117 117
J
L
18 18 18 18
18 18 18 18
18 18
118 118
118 118
18 18 18
118 118
18 18 18 18
18 18 18 18
116 116
17
116 116
R
15 15
115 115
115 115
T 115 115
U
115 115
115 115
V 114 114
W
AB 114 114
14
113 113
14 14
AD 113 113
113 113
AF 113 113
AG
12
113 113
113 113
AH 113 113
AJ
112 112
112 112
AK 113 113
AL
111 111
112 112
AN
AP 112 112
2
4
5
6
111 111
8
9
11
11 11 11 11
11 11
11 11 11 11
13 13 AF
13 13 13 AH
13 AJ
12 13 13 13
13 13 13 13 AK
13 13 AL
12 13 13 13
12 12 12 12
AG
13 13 13 13
12 12 12 13
AM
13 13 13 13
12 12 13 13
12 12 12 12
13 AD
13 13 13 13 AE
12 12 12 12
11 12 12 12
AB
13 13 13 AC
12 12 13 13
11 12 12 12
11 11 11 12
11 11 11 11
Y
14 14 AA
12 13 13 13
12 12 12 12
11 11 11 12
V
14 W
14 14 14 14
12 12 12 12
T
U
14 14 14 14
12 12 12 12
11 11 12 12
11 11 11 11
11 11 11
111 111
111 111
7
11 11
11 11 11 11
111 111
111 111
112 112
3
111 111
111 111
11 11 11 11
11 11 11 11
111 111
112 112
112 112
1
111 111
112 112
AM 112 112
11 11 11 11
15 15
14 14 14
14 14 14 13
12 12 12
112 112
R
14 14 14 14
12 12 14 14
113 113
P
15 15 15 15
14 14 14 14
14 14 14 14
N
15
15 15 15 15
14 14 14 14
14 14 14
L
M
15 15 15
14 14 14 14
114 114
16 16
15 15 15 15
14 14 14 14
114 114
113 113
AE
15 14
114 114
114 114
J
K
15 15 15 15
15 15 15 15
H
16
15 15 15 15
15 15 15 15
114 114
16 16 16
15 15 15 15
15 15 15
114 114
Y 114 114
AC
115 115
115 115
114 114
AA
15
F
G
16 16 16 16
17 17 16 16
15 15 15 15
115 115
E
16 16
16 16 16 16
17 17 17 15
115 115
P 115 115
D
16 16 16 16
17 17 17 17
17 17 17
115 115
16
17 17 16 16
17 17 17 17
C
16 16 16 16
17 16 16 16
17 17 17 17
18 17 17 17
116 116
B
16 16 16
16 16 16 16
17 17 17 16
18 17 17 17
A
16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 18 17
18 18 18 18
17 16 16 16
17 17 17 17
18 18 17 17
18 18 18 18
18 18 18 18
18
18 17 17 17
18 18 18 18
116 116
M 116 116
N
118 118
118 118
116 116
18
18 18 18
117 117
116 116
K 116 116
118 118
118 118
117 117
H 116 116
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
118 118
117 117
F 116 116
9
118 118
117 117
G
8
117 117
117 117
E
7
118 118
13
13 AN
AP
13 13 13 13 13
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ug475_c3_54_052311
Figure 3-50:
94
FFG1156 Package—XC7K480T I/O Banks
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Kintex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-51
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
18
B
18 18 18
C
18 18 18 18
18 18 18 18
D
18 18
E
18 18 18 18
F
18
G
18 18 18
H
18 17 17 17
18 18 18 18
18 18 17 17
18 18 18 18
18 18 18 18
18 18 18 18
17 17 17 17
18 17 17 17
17 17 17 17
17
L
17 17 17
15 15
15 15 15 15
R
15
T
15 15 15
14 14 14 14
Y
14
AD
12 12 14 14
AE
12
AH
11 11 11 11
AJ
11 11
AK
11 11 11 11
AL
11
AM
11 11 11
AN
11 11 11 11
11 11 11 11
11 11 11 11
AP
11 11
1
2
3
4
5
6
7
8
9
11 11 11 11
13 13 AF
13 13 13 AH
12 12 12 13
13 13 13 13 AK
13 13 AL
12 13 13 13
AM
13 13 13 13
12 12 13 13
12 12 12 12
13 AJ
12 13 13 13
12 12 12 12
AG
13 13 13 13
12 12 12 12
11 12 12 12
13 AD
13 13 13 13 AE
12 12 13 13
11 12 12 12
11 11 11 12
AB
13 13 13 AC
12 13 13 13
12 12 12 12
11 11 11 12
Y
14 14 AA
14 14 14 14
12 12 12 12
V
14 W
14 14 14 14
12 12 12 12
11 11 12 12
U
14 14 14
14 14 14 13
12 12 12
11 11 11 11
T
15 15
14 14 14 14
14 14 14 14
11 11 11 11
R
14 14 14 14
14 14
AF
P
15 15 15 15
15 15 15 15
14 14 14 14
AC
N
15
14 14 14 14
14 14 14
M
15 15 15
15 15 15 15
15 14
L
16 16
15 15 15 15
15 15 15 15
V
AG
J
K
15 15 15 15
15 15 15 15
AB
16
15 15 15 15
W
H
16 16 16
17 17 16 16
P
F
G
16 16 16 16
16 16 16 16
17 17 17 17
N
AA
E
16 16
16 16 16 16
17 17 17 15
U
D
17 17 16 16
J
M
16
16 16 16 16
17 16 16 16
K
B
C
16 16 16
16 16 16 16
17 17 17 16
18 17 17 17
A
16
16 16 16 16
17 17 16 16
17 17 17 17
18 18 18 17
18 18 18 18
17 16 16 16
17 17 17 17
13
13 AN
13 13 13 13 13
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_55_052311
Figure 3-51:
FFG1156 Package—XC7K480T Memory Groupings
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
95
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-52
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
18
B
C
B
16
18
C
17
D
18
E
F
17
0
H
E
16
18
G
D
16
18
F
A
16
18
17
0
16
18
H
16
J
J
17
K
K
17
L
L
16
M
M
17
N
N
15
P
P
15
R
R
15
T
T
15
U
15
15
V
W
14
Y
14
AA
AA
14
AB
AB
14
AC
AC
14
AD
AD
13
AE
AE
13
AF
AF
12
AG
13 AG
12
AH
11
AJ
AJ
12
11
AK
12
AL
11
AM
AM
13
11
12
AP
AL
13
11
AN
AH
13
11
AK
AN
13
AP
12
1
2
3
4
5
6
7
8
9
U
V
14
W
Y
G
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_56_052311
Figure 3-52: FFG1156 Package—XC7K480T Power and GND Placement
96
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
Virtex-7 FPGAs Device Diagrams
Table 3-3:
Virtex-7 FPGAs Device Diagrams Cross Reference
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FF(G)
FL(G)
FL(G)
FL(G)
FL(G)
FH(G)
1157
1158
1761
1926
1927
1928
1930
1761
1925
1928
1930
1761
Device
XC7V585T
page 98
page 102
XC7V1500T
FL1761/
FLG1761
XC7V2000T
page 106
XC7VX330T
FF1157/
FFG1157
XC7VX415T
FF1157/ FF1158/
FFG1157 FFG1158
FF1927/
FFG1927
XC7VX485T
page 114 page 118 page 122
page 126
XC7VX550T
FF1158/
FFG1158
FF1927/
FFG1927
XC7VX690T
page 110
FF1761/
FFG1761
page 130
FF1157/ FF1158/ FF1761/ FF1926/ FF1927/
FFG1157 FFG1158 FFG1761 FFG1926 FFG1927
XC7VX980T
FF1926/
FFG1926
FF1930/
FFG1930
FF1928/ FF1930/
FFG1928 FFG1930
XC7VX1140T
FL1928/ FL1930/
FLG1928 FLG1930
Note: The available files are listed in Table 3-3 are linked. Figures for some Virtex-7 FPGAs are in
development.
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
97
Chapter 3: Device Diagrams
FFG1157 Package—XC7V585T
X-Ref Target - Figure 3-53
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
V
C
E
C
V
D
D
E
E
E
E
G
F
F
V
G
V
H
H
E
J
J
K
K
V
L
E
V
M
V
N
I
L
K
M
O
M
N
P
P
V
V
R
n
V
T
Y
E
U
V
V
W
n
C
T
P
S
S
D
S
S
V
L
J
W
E
V
Y
R
U
2
Y
E
AA
AA
1
AB
V
AC
E
AB
0
V
AD
r
B
r
B
B
AC
AD
E
AE
AE
AF
AF
V
AG
E
B
AG
V
AH
AH
E
AJ
U
B
AJ
AK
AK
V
AL
E
B
V
AM
AM
E
AN
G
B
2
3
4
5
6
7
8
User I/O Pins
9
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Multi−Function Pins
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
1
AN
B
V
AP
s
AL
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_170_090511
Figure 3-53:
98
FF(G)1157 Package—XC7V585T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-54
1
2
3
4
5
6
7
118 118
A
B 118 118
118 118
D 118 118
118 118
F 117 117
J
39
118 118
39 39 39
117 117
39 39
117 117
K 117 117
L
N
37 37 37 37
38 38 38 37
R
17 17 17
117 117
T 116 116
U
17 17
116 116
V 116 116
17
116 116
16 16 16
116 116
W
16
116 116
AB 115 115
115 115
AD 115 115
115 115
AF 115 115
AG
34 34
115 115
34
34 34 34
114 114
34 34
114 114
AJ
AK 114 114
114 114
AL
AM 114 114
AP 114 114
1
2
34 34
114 114 115
3
4
5
6
7
34 34 34 34
8
9
35 36 36 36
35 35 35 35
34 34 35 35
35 35 35 35
36 36 36 36
15 15 AF
15 15 15 AH
14 14 15 15
15 AJ
14 14 14 14 AK
14 14 14 14
14 14 14 14
AG
15 15 15 15
15 15 15 15
14 14 AL
14 14 14 14
14 14 14 14
36 14 14 14
15 AD
15 15 15 15 AE
14 14 14 14
36 36 36 14
AB
16 16 16 AC
15 15 15 15
36 36 14 14
36 36 36 36
35 35 36 36
Y
16 16 AA
15 15 15 15
36 14 14 14
36 36 36 36
V
16 W
16 16 16 16
14 15 15 15
T
U
16 16 16 16
15 15 15 15
36 36 14 14
36 36 36 36
35 35 35 36
34 35 35 35
34 34 34 34
115
35 35 35 36
17 17
16 16 16
15 15 15 15
36 14 14 15
36 36 36 36
R
16 16 16 16
15 15 15 15
36 36 15 15
35 36 36 36
35 35 35 35
34 34 34 35
34 34 34 34
114 114
114 114
AN
36 36 36 36
35 35 35 35
34 34 35 35
34 34 34 34
36 15 15 15
35 35 35 36
35 35 35 35
34 34 34 35
114 114
35 36 36
35 35 35 35
34 34 35 35
34 34 34 34
115 115
AH 115 115
35
34 34 34 34
115 115
AE
34
P
17 17 17 17
16 16 16 16
16 16 16 16
34 34
N
17
16 17 17 17
16 16 16 16
L
M
17 17 17
16 16 16 16
16 16 16 16
115 115
AC
18 18
17 17 17 17
16 16 16 16
Y 116 116
AA
J
K
17 17 17 17
17 17 17 17
H
18
17 17 17 17
17 17 17
116 116
18 18 18
17 17 17 17
17 17 17 17
F
G
18 18 18 18
18 18 18 18
17 17 17 17
116 116
E
18 18
18 18 18 18
18 18 18 18
117 117
P 116 116
D
18 18 18 18
18 18 18 18
18 18 18 18
37
19
18 18 18 18
19 19 19 18
37 37 18 18
B
C
19 18 18 18
19 18 18 18
19 19 19 18
37 37 19 19
37 37 37 37
38 38 37 37
39 38 38 38
39 39 39 39
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 38
39 39 39
117 117
38 38 38 38
39 39 38 38
39 39 39 39
117 117
M 117 117
39 39 39 38
A
19 19 19
19 19 19 19
19 19 19 19
37 19 19 19
19
19 19 19 19 19
19 19 19 19
37 19 19 19
37 37 37 19
38 37 37 37
19 19 19 19
19 19 19 19
37 37 37 19
37 37 37 37
38 38 38 37
38 38 38 38
37 37 19 19
37 37 37 37
38 38 37 37
38 38 38 38
39 39 38 38
39 39 39 39
38 37 37 37
38 38 38 38
39 38 38 38
39 39 39 39
118 118
H 117 117
38 38 38 38
39 39 39 38
39 39
118 118
G
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
39 39 39
118 118
E
9
39
118 118
C
8
39 39 39 39
AM
14 14 14 AN
14 14 14 14 14
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ug475_c3_7V585TFFG1157_061011
Figure 3-54:
FF(G)1157 Package—XC7V585T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
99
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-55
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
39 39 39 39
B
39
C
39 39 39
D
38 38 38 38
39 39 39 38
39 38 38 38
39 39 39 39
E
39 39
F
39 39 39 39
G
39
H
39 39 39
J
39 39 39 38
39 39
L
39 39 38 38
37 37 37 37
38 38 38 37
17 17 17
P
17 17
T
17
V
16 16 16
W
Y
16
AB
AD
34
35
34 34 34 34
AE
34 34
AF
34 34 34 34
34
AH
34 34 34
AJ
35 35 35 35
34 34 35 35
AG
34 34 34 34
34 34
AL
34 34 34 34
34 34
AP
2
3
4
5
6
7
8
9
35 36 36 36
35 35 35 35
34 34 35 35
35 35 36 36
35 35 35 35
36 36 36 36
15 15 AF
15 15 15 AH
15 AJ
14 14 15 15
14 14 14 14 AK
14 14 14 14
14 14 AL
AM
14 14 14 14
14 14 14 14
36 14 14 14
AG
15 15 15 15
14 14 14 14
36 36 36 14
15 AD
15 15 15 15 AE
15 15 15 15
14 14 14 14
AB
16 16 16 AC
15 15 15 15
36 36 14 14
36 36 36 36
Y
16 16 AA
15 15 15 15
36 14 14 14
36 36 36 36
V
16 W
16 16 16 16
14 15 15 15
T
U
16 16 16 16
15 15 15 15
36 36 14 14
36 36 36 36
35 35 35 36
34 35 35 35
34 34 34 34
1
35 35 35 36
17 17
16 16 16
15 15 15 15
36 14 14 15
36 36 36 36
R
16 16 16 16
15 15 15 15
36 36 15 15
35 36 36 36
35 35 35 35
34 34 34 35
34 34 34 34
AN
36 36 36 36
35 35 35 35
34 34 35 35
AK
36 15 15 15
35 35 35 36
35 35 35 35
34 34 34 35
AM
35 36 36
P
17 17 17 17
16 16 16 16
16 16 16 16
34 34
N
17
16 17 17 17
16 16 16 16
L
M
17 17 17
16 16 16 16
16 16 16 16
AC
18 18
17 17 17 17
16 16 16 16
AA
J
K
17 17 17 17
17 17 17 17
H
18
17 17 17 17
17 17 17
U
18 18 18
17 17 17 17
17 17 17 17
F
G
18 18 18 18
18 18 18 18
17 17 17 17
R
E
18 18
18 18 18 18
18 18 18 18
N
D
18 18 18 18
18 18 18 18
18 18 18 18
37
19
18 18 18 18
19 19 19 18
37 37 18 18
B
C
19 18 18 18
19 18 18 18
19 19 19 18
37 37 19 19
37 37 37 37
38 38 37 37
39 38 38 38
39 39 39 39
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 38
39 39 39
M
38 38 38 38
19 19 19
19 19 19 19
19 19 19 19
37 19 19 19
A
19
19 19 19 19 19
19 19 19 19
37 19 19 19
37 37 37 19
38 37 37 37
19 19 19 19
19 19 19 19
37 37 37 19
37 37 37 37
38 38 38 37
38 38 38 38
37 37 19 19
37 37 37 37
38 38 37 37
38 38 38 38
39 39 38 38
39 39 39 39
K
38 37 37 37
38 38 38 38
14 14 14 AN
AP
14 14 14 14 14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_7V585TFFG1157_061011
Figure 3-55: FF(G)1157 Package—XC7V585T Memory Groupings
100
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-56
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
38
B
37
39
C
11
D
11
37
39
H
11
11
19
39
J
11
L
11
N
J
18
K
18
39
18
39
11
M
18
3
1
N
17
17
R
10
T
L
18
37
P
10
3
1
10
3
1
2
0
2
0
P
17
R
17
10
T
17
U
16
17
V
10
Y
10
0
Y
16
10
AB
10
AD
2
10
35
0
15
34
AH
36
34
AL
10
10
36
34
3
4
5
6
7
8
9
AN
14
34
2
AM
14
35
AP
AL
14
36
10
1
AK
36
34
10
AJ
14
35
AN
AH
15
35
AK
AM
15 AG
14
34
10
AF
15
35
10
AJ
AE
15
35
10
AD
15
36
AF
10
AC
15
34
10
AG
AB
16
10
AE
AA
16
0
AC
W
16
10
AA
U
V
16
W
G
H
18
37
11
11
18
37
39
38
M
F
19
38
K
E
19
38
11
D
19
37
F
G
C
19
38
11
B
19
38
11
E
A
19
37
14 AP
36
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_7V585TFFG1157_080911
Figure 3-56:
FF(G)1157 Package—XC7V585T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
101
Chapter 3: Device Diagrams
FFG1761 Package—XC7V585T
X-Ref Target - Figure 3-57
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
V
A
B
V
C
B
G
V
C
E
D
D
V
E
V
F
E
E
E
G
F
V
G
V
H
H
V
J
V
J
E
K
K
L
V
L
E
M
M
V
N
V
P
K
V
R
V
N
C
V
P
M
R
O
T
T
I
V
U
U
V
V
W
V
E
V
E
V
E
V
E
n
W
n
Y
Y
AA
AB
AC
n
n
AA
S
S
S
S
AB
L
J
AC
AD
AD
AE
AE
AF
AF
n
AG
AG
Y
AH
AH
n
AJ
V
E
2
AK
AJ
P
AK
1
AL
V
E
AM
0
D
V
AN
B
V
E
AP
s
V
AR
U
E
V
E
AL
B
AM
AN
B
s
V
B
AP
B
AR
s
AT
AT
s
AU
AV
AU
AV
V
AW
V
E
AY
r
V
BA
V
E
3
4
5
6
7
8
9
User I/O Pins
Transceiver Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
Dedicated Pins
BA
B
BB
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
s
B
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
V
2
AW
AY
BB
1
r
B
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_174_090511
Figure 3-57:
102
FF(G)1761 Package—XC7V585T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-58
1
2
3
4
A
5
6
7
8
119 119
B
119 119
C 119 119
D
119 119
F
L 117 117
116 116
115 115
115 115
115 115
AE 115 115
114 114
AG 114 114
AJ 114 114
114 114
113 113
AN 113 113
AU 112 112
112 112
112 112
AW 111 111
111 111
112 112
111 111
111 111
4
31 31 31
6
7
8
31 32 32 32
31 31 31 31
111 111
111 111
5
31 31
31
31 31 31
9
32 33 33 33
32 32 32 32
31 31 32 32
12 12 12 13
33 33 12 12
33 33 33 33
12 12 12 12
15 15 AU
AV
15 15 15 15
15 15 15 AW
13 13 15 15
15 AY
15 15 15 15
13 13 13 15
13 13 13 13
15 AR
15 15 15 15 AT
13 15 15 15
13 13 13 13
12 13 13 13
AN
15 15 15 AP
15 15 15 15
13 13 13 13
13 13 13 13
15 15 AM
15 15 15 15
13 13 13 15
13 13 13 13
12 12 13 13
12 12 12 12
33 33 33 33
32 32 33 33
32 32 32 32
12 12 12 12
33 33 12 12
17 AK
17 17 17 17 AL
14 14 14 15
13 13 13 13
AH
17 17 17 AJ
14 14 15 15
14 14 14 14
12 13 13 13
17 17 AG
14 17 17 17
14 14 14 14
13 13 13 13
12 12 12 13
33 12 12 12
33 33 33 33
32 32 32 33
12 12 13 13
17 AE
17 17 17 17
14 14 14 17
14 14 14 14
AC
17 17 17 17 AF
16 17 17 17
14 14 14 14
Y
17 17 AB
16 17 17 17
16 16 16 16
14 14 14 14
12 12 12 12
33 33 33 12
32 32 33 33
32 32 32 32
12 14 14 14
17
17 17 17 AD
16 16 16 17
14 14 14 14
12 12 12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 32 32
31 31 31 32
111 111
111 111
3
31
112 112
111 111
BA 111 111
2
31 31 31 31
112 112
14
33 12 12 12
33 33 33 33
32 32 33 33
31 32 32 32
12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 31 32
31 31 31
112 112
112 112
1
31
112 112
33 33 33 33
32 32 32 33
31 31 31 32
31 31 31 31
113 113
AR 112 112
BB
31
113 113
113 113
31 31 32 32
31 31 31 31
113 113
113 113
AY
31 31
V
17 17 17 17
14 14 14 16
T
U
17 17 17 17 AA
16 16 17 17
14 14 14 16
P
R
17 18 18 W
16 17 17 17
16 16 16 16
14 14 14 14
113 113
AL 113 113
AV
14
113 113
18 18
18 18 18 18
16 16 16 16
14 14 16 16
114 114
114 114
AT
16 16
114 114
19
18 18 18 18
16 16 16 16
16 16 16 16
N
19 19 19
18 18 18 18
16 16 16 16
16 16 16
114 114
114 114
AP
16
L
19 19 M
18 18 18 18
16 16 16 16
16 16 16 16
115 115
114 114
AK
34 34
J
19 19 19 19
18 18 18 19
18 18 18 18
34 34 18 18
H
19 19 19 19
18 18 18 18
34 18 18 18
34 34 34
115 115
AC 115 115
AM
34 34 34 18
34 34
F
G
K
18 18 18 18
18 18 18 18
E
19
19 19 19 19
18 18 18 19
34 34 18 18
34 34 34
116 116
115 115
AH
34
116 116
AA 115 115
AF
34 34 34 34
36 36
116 116
116 116
AD
36 36 36 36
38 36 36 36
116 116
W 115 115
AB
38 38 38 36
38 38
D
19 19 19
19 19 19 19
34 34 19 19
34 34 34 34
19 19
35 19 19 19
34 35 35 35
34 34 34 34
34 34 34 34
36 36 34 34
116 116
U 116 116
Y
39 39 39 39
117 117
36 36 36 36
36 36 36 36
35 34 34 35
34 34 34 34
36 36 34 34
19
35 19 19 19
35 35 35 19
B
C
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
39 39 39 38
39 39 39 39
117 117
R 116 116
V
39 39
36 36 36 36
38 38 38 36
39 39 38 38
39 39 39 39
117 117
116 116
T
39 39 39 39
39 39 39
117 117
117 117
N 117 117
39 38 38 38
37 37 37 35
19 19
35 35 19 19
35 35 35 35
35 35 35 35
A
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 38 38
39 39 39
118 118
117 117
P
118 118
117 117
117 117
M
39
38 38 38 37
39 38 38 38
39 39 39 39
118 118
118 118
J 118 118
K
39
39 39
118 118
118 118
39 38 38 38
39 39 39 39
119 119
118 118
H
115
115
119 119
118 118
G 118 118
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
119 119
119 119
E 119 119
9
119 119
15 15 15 15 BA
13 15 15 15
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
ug475_c3_175_080911
Figure 3-58:
FF(G)1761 Package—XC7V585T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
103
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-59
39 38 38 38
39
39 39 39 39
39 39
39 39 39
39 38 38 38
39 39 39 39
39 39
39 39 38 38
39 39 39 39
39 39
36 36 36 36
38 38 38 36
38 38
36 36 36 36
36 36 34 34
36 36 36 36
38 36 36 36
34 34 34 34
36 36
34
34 34 34 18
34 34
34 34
16
14 14 16 16
14
31 31
31 31 32 32
31 31 31 31
31
31 31 31 32
31 31 31 31
31
31
31 31 32 32
31 31 31
32 32 32 32
31 31 31 32
31 31
31
32 32 32 32
33 33 33 33
12 12 12 12
15 15 15
15 15 15 15
13 13 13 15
13 13 13 13
15 15
15 15 15 15
13 13 15 15
13 13 13 13
12 13 13 13
15
15 15 15 15
13 15 15 15
13 13 13 13
13 13 13 13
12 12 12 13
33 33 12 12
15 15 15
15 15 15 15
13 13 13 15
13 13 13 13
12 12 13 13
12 12 12 12
33 33 33 33
32 32 33 33
12 13 13 13
12 12 12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 32 32
31 31 31
33 33 33 33
32 32 32 33
31 32 32 32
31 31 31 31
33 12 12 12
15 15
15 15 15 15
14 14 14 15
13 13 13 13
17
17 17 17 17
14 14 15 15
14 14 14 14
13 13 13 13
12 12 12 13
17 17 17
14 17 17 17
14 14 14 14
14 14 14 14
12 12 13 13
12 12 12 12
33 33 33 12
32 32 33 33
14 14 14 14
17 17
17 17 17 17
14 14 14 17
14 14 14 14
17
17 17 17 17
16 17 17 17
14 14 14 16
14 14 14 14
12 12 12 12
33 33 12 12
32 33 33 33
32 32 32 32
14
12 14 14 14
33 12 12 12
33 33 33 33
32 32 33 33
31 32 32 32
31 31 31 31
12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 31 32
31 31 31
33 33 33 33
32 32 32 33
17 17 17
16 17 17 17
16 16 16 16
14 14 14 16
14 14 14 14
17 17
17 17 17 17
16 16 16 17
16 16 16 16
17
17 17 17 17
16 16 17 17
16 16 16 16
16 16 16 16
16 16
17 18 18
16 17 17 17
16 16 16 16
16 16 16 16
16 16 16
18 18
18 18 18 18
18 18 18 18
16 16 16 16
16 16 16 16
19
18 18 18 18
18 18 18 18
18 18 18 18
34 34 18 18
19 19 19
18 18 18 19
18 18 18 18
34 18 18 18
34 34 34
19 19
19 19 19 19
18 18 18 18
18 18 18 18
19
19 19 19 19
19 19 19 19
18 18 18 19
34 34 18 18
34 34 34
19 19 19
19 19 19 19
34 34 19 19
34 34 34 34
34 34 34 34
19 19
35 19 19 19
34 35 35 35
34 34 34 34
19
35 19 19 19
35 35 35 19
35 34 34 35
34 34 34 34
36 36 34 34
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
39 39 39 39
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
39 39 39 38
39 39 39
36 36 36 36
38 38 38 36
19 19
35 35 19 19
35 35 35 35
35 35 35 35
37 37 37 35
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 38 38
39 39 39 39
39
38 38 38 37
39 38 38 38
15
15 15 15 15
13 15 15 15
15
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_176_080911
Figure 3-59: FF(G)1761 Package—XC7V585T Memory Groupings
104
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-60
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
37
B
11
C
11
11
D
G
11
H
34
38
L
11
11
39
11
36
11
P
R
0
2
5
10
5
10
10
4
10
10
4
10
10
4
10
10
3
34
2
34
18
18
1
16
AB
17
1
AC
AD
16
16
3
AG
AA
17
AD
AF
Y
16
16
AB
AF
17
3
AG
16
17 AH
14
AJ
10
10
32
AK
14
31
AL
10
10
AM
31
33
10
AP
10
10
10
13
32
AV
AY
BA
12
32
10
10
31
3
4
5
6
7
8
9
AY
13
33
32
2
AW
15
12
BB
1
15 AV
13
32
10
AU
13
33
10
AT
15
12
31
10
AR
15
12
31
10
AW
AP
13
33
AT
AU
AN
14
33
31
AM
15
12
31
10
AL
14
14
32
10
AR
AK
14
33
10
AJ
17
12
10
AN
AE
17
14
AH
BA
13
13
V
W
18
1
AE
U
34
Y
AC
T
18
2
AA
R
19
18
V
W
P
18
5
T
U
N
19
36
10
M
19
36
39
10
L
34
34
38
11
K
35
38
H
J
19
36
0
N
19
36
39
M
G
35
36
11
F
35
36
39
11
K
E
19
37
39
11
J
35
38
11
D
35
37
11
C
35
37
11
B
19
37
39
11
F
37
38
11
E
A
35
38
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
#
VCCO_#
VCCINT
MGTVCCAUX
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
VCCAUX_IO_G#
MGTAVCC
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_177_080911
Figure 3-60:
FF(G)1761 Package—XC7V585T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
105
Chapter 3: Device Diagrams
FLG1925 Package—XC7V2000T
X-Ref Target - Figure 3-61
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
T
T
U
U
V
V
W
W
Y
Y
AA
AA
AB
C
Y
I
K
M
O
P
AC
AD
E
AE
D
S
S
S
S
B
L
J
B
AC
r
r
U
V
V
E
G
AG
2
AH
E
AJ
B AD
AE
B
AF
B
V
AF
AB
B
1
B
B
AH
0
AJ
V
V
E
AK
V
AK
AG
AM
AL
AL
AM
AN
AN
V
V
AP
V
AP
AR
AR
AT
AT
E
AU
AU
V
AV
V
AV
E
AW
AW
AY
AY
E
BA
BA
V
V
G
E
BB
V
BB
BC
BC
BD
BD
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
User I/O Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
Dedicated Pins
C
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
M
r
Other Pins
V
s
Transceiver Pins
V
1
VCCO_#
GNDADC_0
RS0−RS1
MGTHRXN
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_200_090511
Figure 3-61:
106
FLG1925 Package—XC7V2000T Pinout Diagram
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-62
1
2
A
3
4
B
39
6
39 39 39 39
D
39
E
39 39 39
F
39 39 39 39
39 39
H
39 39 39 39
J
38
K
38 38 38
38
R
38 38 38
38 38 38 38
38 38 38 37
37 37 37 37
37 37
V
37 37 37 37
W 37
41 40 40 40
42 41 41 41
38 42 42 42
37 37 37 37
37 37 37 37
41 41 40 40
42 42 41 41
17 17 17 17
40 40 40 17
40 17 17 17
40 40 40 40
18 18 18 19
17 17 18 18
18 18 20 20
37 37
16
37
16 16 16 16
37 37 37 37
15 15
AB
15 15 15 15 15
AC
15
AD 115 115
AE
115 115
115 115
AF 115 115
AG
115 115
115 115
AH 114 114
AJ
115 115
114 114
114 114
114 114
AT 113 113
114 114
113 113
113 113
113 113
112 112
BB 112 112
31 31
112 112
31
112 112
BD
2
3
4
5
6
31 31
7
8
9
31 32 32 32
34 34 34 34
33 33 33 34
32 32 33 33
35 36 36 36
35 35 35 35
34 34 34 35
36 11 11 11
35 35 36 36
AY
11 11 11 BA
11 11 11 11
11 11 11 11
36 11 11 11
11 11 AW
11 11 11 11
11 11 11 11
11 11 11 11
12 AU
12 12 12 12 AV
11 11 11 11
11 11 11 11
36 36 36 11
AR
12 12 12 AT
12 12 12 12
12 12 12 12
36 36 11 11
12 12 AP
12 12 12 12
12 12 12 12
12 12 12 12
36 36 36 36
35 35 35 36
34 34 35 35
33 34 34 34
33 33 33 33
35 35 36 36
34 35 35 35
13 AM
12 13 13 13 AN
12 12 12 12
12 12 12 12
36 36 36 12
AK
13 13 13 AL
13 13 13 13
12 12 12 12
36 36 12 12
35 36 36 36
35 35 35 35
34 34 34 35
33 33 34 34
32 33 33 33
32 32 32 32
31 31 31 32
112 112
1
31 32 32 32
31 31 31
112 112
33 33 33 33
32 32 32 33
35 35 35 36
34 34 35 35
33 34 34 34
36 36 36 36
13 13 AJ
13 13 13 13
13 13 13 13
36 12 12 12
14 AG
14 14 13 13 AH
13 13 13 13
13 13 13 13
AE
14 14 14 AF
14 14 14 14
13 13 13 13
36 36 36 12
35 36 36 36
34 35 35 35
34 34 34 34
33 33 33 34
32 32 33 33
31 32 32 32
31 31 31 31
33 33 34 34
32 33 33 33
32 32 32 32
31 31 31 32
112 112
112 112
32 32 32 33
31 31 32 32
31 31 31
112 112
112 112
BC
31
113 113
AY 112 112
BA
31 31 31 31
35 35 35 36
34 34 35 35
14 14 AD
14 14 14 14
13 13 13 14
36 13 13 13
36 36 36 36
15 AB
15 15 15 15 AC
14 14 14 14
13 13 13 13
36 36 36 13
35 35 36 36
34 35 35 35
34 34 34 34
33 33 33 33
14 14 14 13
35 35 35 35
34 34 34 35
33 33 34 34
32 32 33 33
31 32 32 32
34 34 35 35
33 34 34 34
33 33 33 33
32 32 32 32
31 31 31 32
31 31
33 33 33 34
32 32 33 33
31 31 32 32
31 31 31
113 113
AV 113 113
AW
31
113 113
113 113
31 32 32 32
31 31 31 31
114 114
AP 113 113
AU
31 31
Y
15 15 15 AA
15 15 15 14
14 14 14 14
14 13 13 13
V
16 16 W
15 15 15 15
15 15 15 15
14 14 14 14
14 14 14 14
14 14
114 114
AM 114 114
AR
14 14
115 115
114 114
AN
115 115
16 16 16 16
16 16 16 16
14 14 14 14
T
U
15 15 15 15
15 15 15 15
14 14 14 14
115 115
AK 114 114
AL
15 15 15
115 115
P
20
16 16 16 16
15 15 15 15
15 15 15 15
N
R
20 20 20
16 16 16 16
16 16 16 16
15 15 15 15
20 20
20 20 20 20
16 16 16 16
16 16 16 16
L
21 M
20 20 20 20
20 20 20 20
J
K
21 21 21
20 20 20 20
16 16 16 16
16 16 16 16
16 16 16
H
21 21
20 20 20 21
20 20 20 20
20 20 20 20
16 16 16 16
37 37 37
37 37 37 37
37 37 37 37
20 20 20 20
21 21 21 21
21 21 21 21
20 20 20 20
20 20 20 20
F
G
21 21 21 21
21 21 21 21
19 19 19 20
18 19 20 20
18 18 18 18
17 17 17 18
19 19 21 21
19 19 19 19
37 37 37 37 37
37 37 37 37
37 37 37
AA
42 42 42 41
38 38 38 42
18 18 19 19
17 18 18 18
D
21
21 21 21 21
21 21 21 21
C
E
22 22 22
21 21 21 21
21 21 21 21
19 21 21 21
19 19 19 19
22 22
22 22 22 22
22 22 22 22
21 21 21 21
19 19 19 21
18 19 19 19
18 18 18 18
17 17 17 18
40 40 17 17
18 19 19 19
18 18 18 19
17 17 18 18
40 17 17 17
40 40 40 40
41 41 41 40
17 17 18 18
17 17 17 17
40 40 40 17
41 41 40 40
42 42 41 41
38 38 42 42
40 40 40 17
41 41 40 40
42 41 41 41
42 42 42 42
38 38 38 38
38 38 38 38
U
42 42 42 41
39 42 42 42
38 38 38 38
41 41 41 41
B
22 22 22 22
22 22 22 22
22 22 22 22
19 19 22 22
A
22
22 22 22 22
22 22 22 22
19 22 22 22
19 19 19 19
18 18 18 19
22 22 22 22
22 22 22 22
19 19 19 22
18 18 19 19
17 18 18 18
17 17 17 17
19 19 22 22
19 19 19 19
18 18 18 19
17 17 17 18
40 40 17 17
41 40 40 40
18 18 19 19
17 18 18 18
40 17 17 17
40 40 40 40
41 41 41 40
42 41 41 41
17 17 17 18
40 40 40 17
41 41 40 40
41 41 41 41
42 42 42 42
39 39 39 42
38 38 38 38
38 38 38 38
42 42 41 41
39 39 42 42
41 40 40 40
41 41 41 41
42 42 42 41
38 38 38 38
P
42 41 41 41
39 42 42 42
38 38 38 39
N
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
42 42 42 42
39 39 39 39
M 38 38
9
39 39 39 39
G
T
8
39 39 39 42
39 39 39 39
L
7
39 42 42 42
39 39 39 39
C
Y
5
39 39 39
11 BB
11 11 11
11 11 11 11
BC
BD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ug475_c3_201_052311
Figure 3-62: FLG1925 Package—XC7V2000T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
107
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-63
1
2
A
3
4
B
39
6
39 39 39 39
D
39
E
39 39 39
F
39 39 39 39
39 39
H
39 39 39 39
J
38
K
38 38 38
38
R
38 38 38
38 38 38 38
38 38 38 37
37 37 37 37
37 37
V
37 37 37 37
W 37
41 40 40 40
42 41 41 41
38 42 42 42
37 37 37 37
37 37 37 37
41 41 40 40
42 42 41 41
17 17 17 17
40 40 40 17
40 17 17 17
40 40 40 40
18 18 18 19
17 17 18 18
18 18 18 18
17 17 17 18
16
37 37 37
16 16 16 16
16 16 16
37
16 16 16 16
37 37 37 37
15 15
AB
15 15 15 15 15
AC
15
AD
15 15 15
AE
AF
14 14
AG
14 14
AJ
31 31
AK
31 31 31 31
AL
31
AM
31 31 31
AN
31 32 32 32
31 31 32 32
31 31 31 32
31 31
AR
31 31 31 31
AT
31
AU
31 31 31
32 32 32 33
31 31 32 32
32 32 32 32
31 31 31 32
AW
31 31
AY
31 31 31 31
BA
31
BB
31 31 31
BC
31 32 32 32
31 32 32 32
31 31
1
2
3
4
5
6
7
8
9
33 33 33 33
32 32 32 33
32 32 32 32
31 32 32 32
34 34 34 34
33 33 33 34
32 32 33 33
35 36 36 36
35 35 35 35
34 34 34 35
36 11 11 11
35 35 36 36
AY
11 11 11 BA
11 11 11 11
11 11 11 11
36 11 11 11
11 11 AW
11 11 11 11
11 11 11 11
11 11 11 11
12 AU
12 12 12 12 AV
11 11 11 11
11 11 11 11
36 36 36 11
AR
12 12 12 AT
12 12 12 12
12 12 12 12
36 36 11 11
12 12 AP
12 12 12 12
12 12 12 12
12 12 12 12
36 36 36 36
35 35 35 36
34 34 35 35
33 34 34 34
33 33 33 33
35 35 36 36
34 35 35 35
13 AM
12 13 13 13 AN
12 12 12 12
12 12 12 12
36 36 36 12
AK
13 13 13 AL
13 13 13 13
12 12 12 12
36 36 12 12
35 36 36 36
35 35 35 35
34 34 34 35
33 33 34 34
32 33 33 33
35 35 35 36
34 34 35 35
33 34 34 34
36 36 36 36
13 13 AJ
13 13 13 13
13 13 13 13
36 12 12 12
14 AG
14 14 13 13 AH
13 13 13 13
13 13 13 13
AE
14 14 14 AF
14 14 14 14
13 13 13 13
36 36 36 12
35 36 36 36
34 35 35 35
34 34 34 34
33 33 33 34
32 32 33 33
31 31 31 32
BD
33 33 34 34
32 33 33 33
35 35 35 36
34 34 35 35
14 14 AD
14 14 14 14
13 13 13 14
36 13 13 13
36 36 36 36
15 AB
15 15 15 15 AC
14 14 14 14
13 13 13 13
36 36 36 13
35 35 36 36
34 35 35 35
34 34 34 34
33 33 33 33
14 14 14 13
35 35 35 35
34 34 34 35
33 33 34 34
32 32 33 33
31 32 32 32
34 34 35 35
33 34 34 34
33 33 33 33
32 32 32 32
AP
AV
33 33 33 34
32 32 33 33
Y
15 15 15 AA
15 15 15 14
14 14 14 14
14 13 13 13
V
16 16 W
15 15 15 15
14 14 14 14
14 14 14 14
14 14 14 14
AH
16 16 16 16
16 16 16 16
15 15 15 15
15 15 15 15
14 14 14 14
U
15 15 15 15
15 15 15 15
15 15 15 15
T
20
16 16 16 16
16 16 16 16
15 15 15 15
P
R
20 20 20
16 16 16 16
16 16 16 16
16 16 16 16
N
20 20
20 20 20 20
20 20 20 20
16 16 16 16
L
21 M
20 20 20 20
20 20 20 20
20 20 20 20
20 20 20 20
16 16 16 16
J
K
21 21 21
20 20 20 21
20 20 20 20
20 20 20 20
20 20 20 20
18 18 20 20
37 37
37 37 37 37
37 37 37 37
19 19 19 20
18 19 20 20
H
21 21
21 21 21 21
21 21 21 21
21 21 21 21
F
21 G
21 21 21 21
21 21 21 21
21 21 21 21
19 19 21 21
19 19 19 19
37 37 37 37 37
37 37 37 37
37 37 37
AA
42 42 42 41
38 38 38 42
18 18 19 19
17 18 18 18
E
22 22 22
21 21 21 21
21 21 21 21
19 21 21 21
19 19 19 19
D
22 22
22 22 22 22
22 22 22 22
21 21 21 21
19 19 19 21
18 19 19 19
18 18 18 18
17 17 17 18
40 40 17 17
18 19 19 19
18 18 18 19
17 17 18 18
40 17 17 17
40 40 40 40
41 41 41 40
17 17 18 18
17 17 17 17
40 40 40 17
41 41 40 40
42 42 41 41
38 38 42 42
40 40 40 17
41 41 40 40
42 41 41 41
42 42 42 42
38 38 38 38
38 38 38 38
U
42 42 42 41
39 42 42 42
38 38 38 38
41 41 41 41
B
C
22 22 22 22
22 22 22 22
22 22 22 22
19 19 22 22
A
22
22 22 22 22
22 22 22 22
19 22 22 22
19 19 19 19
18 18 18 19
22 22 22 22
22 22 22 22
19 19 19 22
18 18 19 19
17 18 18 18
17 17 17 17
19 19 22 22
19 19 19 19
18 18 18 19
17 17 17 18
40 40 17 17
41 40 40 40
18 18 19 19
17 18 18 18
40 17 17 17
40 40 40 40
41 41 41 40
42 41 41 41
17 17 17 18
40 40 40 17
41 41 40 40
41 41 41 41
42 42 42 42
39 39 39 42
38 38 38 38
38 38 38 38
42 42 41 41
39 39 42 42
41 40 40 40
41 41 41 41
42 42 42 41
38 38 38 38
P
42 41 41 41
39 42 42 42
38 38 38 39
N
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
42 42 42 42
39 39 39 39
M 38 38
9
39 39 39 39
G
T
8
39 39 39 42
39 39 39 39
L
7
39 42 42 42
39 39 39 39
C
Y
5
39 39 39
11 BB
11 11 11
11 11 11 11
BC
BD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_202_052311
Figure 3-63:
108
FLG1925 Package—XC7V2000T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-64
1
2
3
4
5
A
6
7
8
9
B
41
39
39
H
L
N
38
R
40
37
42
V
17
Y
37
3
AB
0
AC
AD
11
AE
11
11
11
AJ
AK
11
AP
10
10
32
AT
10
35
31
AV
10
33
10
AY
36
32
34
10
BB
10
10
35
31
34
2
3
4
5
6
7
8
9
BA
36
11
36
32
1
AY
11
11
33
BD
AW
11
35
31
AV
12
33
BC
AU
36
32
AT
12
12
34
10
12 AR
35
31
BA
AP
12
12
33
AW
AN
12
34
10
AM
13
36
32
AU
AL
13
36
33
AR
AK
13
34
31
AJ
13
35
31
11
AH
13
14
32
11
AN
AG
13
33
AL
AM
AF
14
14
34
11
AD
14 AE
14
0
31
AC
15
0
4
11
AB
15
15
14
0
4
AH
15
1
4
AG
AA
15
1
5
Y
16
15
1
5
11
W
16
16
2
5
V
16
2
6
0
U
16
2
6
35
R
T
20
16
3
6
37
AF
20
7
AA
P
20
3
7
37
N
20
20
20
7
37
W
19
17
37
M
21
18
41
U
L
19
40
38
K
21
17
38
J
21
21
18
42
P
19
19
41
38
H
21
17
40
38
M
G
21
18
42
42
E
F
22
18
41
38
22
19
40
39
J
K
22
40
39
D
22
17
42
C
22
18
41
B
22
19
41
39
G
19
40
39
E
A
22
17
42
D
T
18
41
C
F
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
39
11
BB
BC
BD
11
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_203_052311
Figure 3-64:
FLG1925 Package—XC7V2000T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
109
Chapter 3: Device Diagrams
FHG1761 Package—XC7V2000T
X-Ref Target - Figure 3-65
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
V
A
B
V
C
B
G
V
C
E
D
D
V
E
V
F
E
E
E
G
F
V
G
V
H
H
V
J
V
J
E
K
K
L
V
L
E
M
M
V
N
V
P
K
V
R
V
N
C
V
P
M
R
O
T
T
I
V
U
U
V
V
V
E
V
E
V
E
V
E
G
W
V
W
Y
Y
AA
AB
G
V
AC
AA
S
S
S
S
AB
L
J
AC
AD
AD
AE
AE
AF
AF
AG
AG
Y
AH
AH
AJ
V
E
2
AK
AJ
P
AK
1
AL
V
E
AM
0
D
V
AN
B
V
E
AP
U
AL
B
AM
AN
B
V
AR
B
AP
B
V
E
AR
V
E
AU
AT
AT
AU
AV
AV
V
AW
V
E
AY
r
V
BA
V
E
3
4
5
6
7
8
9
User I/O Pins
Transceiver Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
Dedicated Pins
C
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
M
r
BA
B
BB
Other Pins
CCLK_0
V
s
B
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
V
2
AW
AY
BB
1
r
B
VCCO_#
GNDADC_0
RS0−RS1
MGTHRXN
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_204_090511
Figure 3-65: FHG1761 Package—XC7V2000T Pinout Diagram
110
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-66
1
2
3
4
A
5
6
7
8
119 119
B
119 119
C 119 119
D
119 119
F
L 117 117
116 116
115 115
115 115
115 115
AE 115 115
114 114
AG 114 114
AJ 114 114
114 114
113 113
AN 113 113
AU 112 112
112 112
112 112
AW 111 111
111 111
112 112
111 111
111 111
4
31 31 31
6
7
8
31 32 32 32
31 31 31 31
111 111
111 111
5
31 31
31
31 31 31
9
12 12 12 13
33 33 12 12
33 33 33 33
12 12 12 12
15 AR
15 15 15 15
15 15 15 15 AT
15 15 AU
13 15 15 15
13 13 13 13
AN
15 15 15 AP
AV
15 15 15 15
15 15 15 AW
13 13 15 15
15 AY
15 15 15 15
13 13 13 15
13 13 13 13
15 15 AM
15 15 15 15
13 13 13 13
12 13 13 13
17 17 17 17 AL
13 13 13 15
13 13 13 13
17 AK
14 17 17 17
14 14 14 15
13 13 13 13
AH
17 17 17 AJ
14 14 15 15
13 13 13 13
12 12 13 13
12 12 12 12
33 33 33 33
32 32 33 33
32 32 32 32
12 12 12 12
17 17 AG
17 17 17 17
14 14 14 14
12 13 13 13
17 AE
17 17 17 17 AF
14 14 14 14
13 13 13 13
12 12 12 13
33 33 12 12
32 33 33 33
32 32 32 32
31 31 32 32
12 12 13 13
33 12 12 12
33 33 33 33
32 32 32 33
14 14 14 14
AC
17 17 17 AD
14 14 14 17
14 14 14 14
Y
17 17 AB
16 17 17 17
14 14 14 16
14 14 14 14
12 12 12 12
33 33 33 12
32 32 33 33
32 32 32 32
12 14 14 14
17
16 17 17 17
16 16 16 16
14 14 14 14
12 12 12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 32 32
31 31 31 32
111 111
111 111
3
31
112 112
111 111
BA 111 111
2
31 31 31 31
112 112
14
33 12 12 12
33 33 33 33
32 32 33 33
31 32 32 32
12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 31 32
31 31 31
112 112
112 112
1
31
112 112
33 33 33 33
32 32 32 33
31 31 31 32
31 31 31 31
113 113
AR 112 112
BB
31
113 113
113 113
31 31 32 32
31 31 31 31
113 113
113 113
AY
31 31
V
17 17 17 17
16 16 16 17
14 14 14 16
14 14 14 14
113 113
AL 113 113
AV
14
113 113
T
U
17 17 17 17 AA
16 16 17 17
16 16 16 16
P
R
17 18 18 W
16 17 17 17
16 16 16 16
14 14 16 16
114 114
114 114
AT
16 16
114 114
18 18
18 18 18 18
16 16 16 16
16 16 16 16
19
18 18 18 18
18 18 18 18
16 16 16 16
16 16 16
114 114
114 114
AP
16
118 118
N
19 19 19
18 18 18 18
16 16 16 16
16 16 16 16
115 115
114 114
AK
34 34
L
19 19 M
18 18 18 19
18 18 18 18
34 34 18 18
J
19 19 19 19
19 19 19 19
18 18 18 18
34 18 18 18
34 34 34
112 112
115 115
AC 115 115
AM
34 34 34 18
F
G
K
18 18 18 18
18 18 18 18
E
19
19 19 19 19
18 18 18 19
34 34 18 18
34 34
116 116
115 115
AH
34
34 34 34
116 116
AA 115 115
AF
34 34 34 34
36 36
116 116
116 116
AD
36 36 36 36
38 36 36 36
116 116
W 115 115
AB
38 38 38 36
38 38
D
H
19 19 19
19 19 19 19
34 34 19 19
34 34 34 34
19 19
35 19 19 19
34 35 35 35
34 34 34 34
34 34 34 34
36 36 34 34
116 116
U 116 116
Y
39 39 39 39
117 117
36 36 36 36
36 36 36 36
35 34 34 35
34 34 34 34
36 36 34 34
19
35 19 19 19
35 35 35 19
B
C
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
39 39 39 38
39 39 39 39
117 117
R 116 116
V
39 39
36 36 36 36
38 38 38 36
39 39 38 38
39 39 39 39
117 117
116 116
T
39 39 39 39
39 39 39
117 117
117 117
N 117 117
39 38 38 38
37 37 37 35
19 19
35 35 19 19
35 35 35 35
35 35 35 35
A
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 38 38
39 39 39
118 118
117 117
P
118 118
117 117
117 117
M
39
38 38 38 37
39 38 38 38
39 39 39 39
118 118
118 118
J 118 118
K
39
39 39
118 118
118 118
39 38 38 38
39 39 39 39
119 119
118 118
H
115
115
119 119
118 118
G 118 118
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
119 119
119 119
E 119 119
9
119 119
15 15 15 15 BA
13 15 15 15
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
ug475_c3_205_052311
Figure 3-66:
FHG1761 Package—XC7V2000T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
111
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-67
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
39 38 38 38
B
39
C
39 39 39 39
D
39 39
E
39 39 39 39
F
39
G
39 39 39
H
39 39 38 38
39 38 38 38
39 39 39
38 38 38 36
39 39 38 38
39 39 39 39
L
39 39
M
39 39 39 39
N
36 36 36 36
39 39 39 38
39 39 39 39
38 38 38 36
P
38 38
36 36 36 36
36 36 36 36
36 36 36 36
38 36 36 36
34 34 34 34
36 36 34 34
34
R
T
34 34 34 18
U
34 34
V
Y
34 34
AB
16
AC
16 16 16
AD
16 16
14 14 16 16
AG
14
AH
AJ
31 31
AK
31 31 32 32
31 31 31 31
AL
31
32 32 32 33
31 31 31 32
AM
31 31 31 31
AN
31
AP
31 31 31
AR
31 31 31 31
AT
31
AU
31 31 31
AW
31 31
AY
31 31 31 31
BA
31
BB
31 32 32 32
31 31 31
1
2
3
4
5
6
7
8
9
32 33 33 33
32 32 32 32
31 31 32 32
12 12 12 13
33 33 12 12
33 33 33 33
12 12 12 12
15 15 AU
AV
15 15 15 15
15 15 15 AW
13 13 15 15
15 AY
15 15 15 15
13 13 13 15
13 13 13 13
15 AR
15 15 15 15 AT
13 15 15 15
13 13 13 13
12 13 13 13
AN
15 15 15 AP
15 15 15 15
13 13 13 13
13 13 13 13
15 15 AM
15 15 15 15
13 13 13 15
13 13 13 13
12 12 13 13
12 12 12 12
33 33 33 33
32 32 33 33
32 32 32 32
12 12 12 12
33 33 12 12
17 AK
17 17 17 17 AL
14 14 14 15
13 13 13 13
AH
17 17 17 AJ
14 14 15 15
14 14 14 14
12 13 13 13
17 17 AG
14 17 17 17
14 14 14 14
13 13 13 13
12 12 12 13
33 12 12 12
33 33 33 33
32 32 32 33
12 12 13 13
17 AE
17 17 17 17
14 14 14 17
14 14 14 14
AC
17 17 17 17 AF
16 17 17 17
14 14 14 14
Y
17 17 AB
16 17 17 17
16 16 16 16
14 14 14 14
12 12 12 12
33 33 33 12
32 32 33 33
32 32 32 32
31 31 31 32
12 14 14 14
17
17 17 17 AD
16 16 16 17
14 14 14 14
12 12 12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 32 32
14
33 12 12 12
33 33 33 33
32 32 33 33
31 32 32 32
12 12
33 33 12 12
32 33 33 33
32 32 32 32
31 31 31 32
AV
33 33 33 33
V
17 17 17 17
14 14 14 16
T
U
17 17 17 17 AA
16 16 17 17
14 14 14 16
P
R
17 18 18 W
16 17 17 17
16 16 16 16
14 14 14 14
18 18
18 18 18 18
16 16 16 16
AF
19
18 18 18 18
16 16 16 16
16 16 16 16
N
19 19 19
18 18 18 18
16 16 16 16
AE
L
19 19 M
18 18 18 18
16 16 16 16
16 16 16 16
19 19 19 19
18 18 18 19
18 18 18 18
34 34 18 18
AA
K
19 19 19 19
18 18 18 18
J
19
18 18 18 18
34 18 18 18
34 34 34
W
19 19 19
19 19 19 19
18 18 18 18
H
35 19 19 19
18 18 18 19
34 34 18 18
34 34 34
F
19 19 G
19 19 19 19
34 34 19 19
34 34 34 34
34 34 34 34
36 36
E
35 19 19 19
34 35 35 35
34 34 34 34
D
19
35 35 35 19
35 34 34 35
34 34 34 34
36 36 34 34
B
C
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
37 37 37 35
19 19
35 35 19 19
35 35 35 35
35 35 35 35
A
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 39
J
K
38 38 38 37
39 38 38 38
15 15 15 15 BA
13 15 15 15
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_206_052311
Figure 3-67:
112
FHG1761 Package—XC7V2000T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-68
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
37
B
11
C
11
11
D
G
11
H
34
38
L
11
11
39
11
36
11
P
R
0
2
5
10
5
10
10
4
10
10
4
10
10
4
10
10
3
34
2
34
18
18
1
16
0
14
AL
10
10
31
33
10
AP
10
10
10
AV
10
AY
10
31
2
3
4
5
6
7
8
9
AW
15
AY
13
33
32
1
15 AV
13
12
BB
AU
12
32
10
AT
15
13
32
10
BA
12
33
10
AR
15
12
31
10
AP
13
32
AW
AN
13
33
31
AM
15
14
33
31
AT
AU
AL
14
12
31
10
AK
14
32
10
AR
AJ
17
14
33
10
17 AH
14
12
10
AN
AG
14
31
AM
AF
17
0
32
AK
AE
17
16
AH
10
AD
16
3
10
AC
16
3
AJ
AB
17
1
AG
AA
17
AD
AF
Y
16
16
AB
BA
13
13
V
W
18
1
AE
U
34
Y
AC
T
18
2
AA
R
19
18
V
W
P
18
5
T
U
N
19
36
10
M
19
36
39
10
L
34
34
38
11
K
35
38
H
J
19
36
0
N
19
36
39
M
G
35
36
11
F
35
36
39
11
K
E
19
37
39
11
J
35
38
11
D
35
37
11
C
35
37
11
B
19
37
39
11
F
37
38
11
E
A
35
38
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_207_052311
Figure 3-68:
FHG1761 Package—XC7V2000T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
113
Chapter 3: Device Diagrams
FFG1157 Package—XC7VX485T
X-Ref Target - Figure 3-69
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
A
B
B
V
C
E
C
V
D
D
E
E
E
E
G
F
F
V
G
V
H
H
E
J
J
K
K
V
L
E
V
M
V
N
I
L
K
M
O
M
N
P
P
V
V
R
n
V
T
Y
E
U
V
V
W
R
C
T
P
S
S
U
D
S
S
V
L
J
W
E
V
Y
n
2
Y
E
AA
AA
1
AB
V
AC
E
AB
0
V
AD
r
B
r
B
B
AC
AD
E
AE
AE
AF
AF
V
AG
E
B
AG
V
AH
AH
E
AJ
U
B
AJ
AK
AK
V
AL
E
B
AM
E
AN
G
B
2
3
4
5
6
7
8
User I/O Pins
9
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Multi−Function Pins
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
V
1
AN
B
V
AP
s
AL
V
AM
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_100_090511
Figure 3-69: FFG1157 Package—XC7VX485T Pinout Diagram
114
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-70
1
2
3
4
5
6
7
118 118
A
B 118 118
118 118
D 118 118
118 118
F 117 117
J
39
118 118
39 39 39
117 117
39 39
117 117
K 117 117
L
N
37 37 37 37
38 38 38 37
R
17 17 17
117 117
T 116 116
U
17 17
116 116
V 116 116
17
116 116
16 16 16
116 116
W
16
116 116
AB 115 115
115 115
AD 115 115
115 115
AF 115 115
AG
34 34
115 115
AJ
34
34 34 34
114 114
34 34
114 114
AK 114 114
AL
114 114
AM 114 114
AP 114 114
1
2
34 34
114 114 115
3
4
5
6
7
34 34 34 34
8
9
35 36 36 36
35 35 35 35
34 34 35 35
35 35 35 35
36 36 36 36
15 15 AF
15 15 15 AH
15 AJ
14 14 15 15
14 14 14 14 AK
14 14 14 14
14 14 14 14
AG
15 15 15 15
15 15 15 15
14 14 AL
14 14 14 14
14 14 14 14
36 14 14 14
15 AD
15 15 15 15 AE
14 14 14 14
36 36 36 14
AB
16 16 16 AC
15 15 15 15
36 36 14 14
36 36 36 36
35 35 36 36
Y
16 16 AA
15 15 15 15
36 14 14 14
36 36 36 36
V
16 W
16 16 16 16
14 15 15 15
T
U
16 16 16 16
15 15 15 15
36 36 14 14
36 36 36 36
35 35 35 36
34 35 35 35
34 34 34 34
115
35 35 35 36
17 17
16 16 16
15 15 15 15
36 14 14 15
36 36 36 36
R
16 16 16 16
15 15 15 15
36 36 15 15
35 36 36 36
35 35 35 35
34 34 34 35
34 34 34 34
114 114
114 114
AN
36 36 36 36
35 35 35 35
34 34 35 35
34 34 34 34
36 15 15 15
35 35 35 36
35 35 35 35
34 34 34 35
114 114
35 36 36
35 35 35 35
34 34 35 35
34 34 34 34
115 115
AH 115 115
35
34 34 34 34
115 115
AE
34
P
17 17 17 17
16 16 16 16
16 16 16 16
34 34
N
17
16 17 17 17
16 16 16 16
L
M
17 17 17
16 16 16 16
16 16 16 16
115 115
AC
18 18
17 17 17 17
16 16 16 16
Y 116 116
AA
J
K
17 17 17 17
17 17 17 17
H
18
17 17 17 17
17 17 17
116 116
18 18 18
17 17 17 17
17 17 17 17
F
G
18 18 18 18
18 18 18 18
17 17 17 17
116 116
E
18 18
18 18 18 18
18 18 18 18
117 117
P 116 116
D
18 18 18 18
18 18 18 18
18 18 18 18
37
19
18 18 18 18
19 19 19 18
37 37 18 18
B
C
19 18 18 18
19 18 18 18
19 19 19 18
37 37 19 19
37 37 37 37
38 38 37 37
39 38 38 38
39 39 39 39
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 38
39 39 39
117 117
38 38 38 38
39 39 38 38
39 39 39 39
117 117
M 117 117
39 39 39 38
A
19 19 19
19 19 19 19
19 19 19 19
37 19 19 19
19
19 19 19 19 19
19 19 19 19
37 19 19 19
37 37 37 19
38 37 37 37
19 19 19 19
19 19 19 19
37 37 37 19
37 37 37 37
38 38 38 37
38 38 38 38
37 37 19 19
37 37 37 37
38 38 37 37
38 38 38 38
39 39 38 38
39 39 39 39
38 37 37 37
38 38 38 38
39 38 38 38
39 39 39 39
118 118
H 117 117
38 38 38 38
39 39 39 38
39 39
118 118
G
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
39 39 39
118 118
E
9
39
118 118
C
8
39 39 39 39
AM
14 14 14 AN
14 14 14 14 14
AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ug475_c3_101_052311
Figure 3-70:
FFG1157 Package—XC7VX485T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
115
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-71
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
39 39 39 39
B
39
C
39 39 39
D
38 38 38 38
39 39 39 38
39 38 38 38
39 39 39 39
E
39 39
F
39 39 39 39
G
39
H
39 39 39
J
39 39 39 38
39 39
L
39 39 38 38
37 37 37 37
38 38 38 37
17 17 17
P
17 17
T
17
V
16 16 16
W
Y
16
AB
AD
34
35
34 34 34 34
AE
34 34
AF
34 34 34 34
34
AH
34 34 34
AJ
35 35 35 35
34 34 35 35
AG
34 34 34 34
34 34
AL
34 34 34 34
34 34
AP
2
3
4
5
6
7
8
9
35 36 36 36
35 35 35 35
34 34 35 35
35 35 36 36
35 35 35 35
36 36 36 36
15 15 AF
15 15 15 AH
15 AJ
14 14 15 15
14 14 14 14 AK
14 14 14 14
14 14 AL
AM
14 14 14 14
14 14 14 14
36 14 14 14
AG
15 15 15 15
14 14 14 14
36 36 36 14
15 AD
15 15 15 15 AE
15 15 15 15
14 14 14 14
AB
16 16 16 AC
15 15 15 15
36 36 14 14
36 36 36 36
Y
16 16 AA
15 15 15 15
36 14 14 14
36 36 36 36
V
16 W
16 16 16 16
14 15 15 15
T
U
16 16 16 16
15 15 15 15
36 36 14 14
36 36 36 36
35 35 35 36
34 35 35 35
34 34 34 34
1
35 35 35 36
17 17
16 16 16
15 15 15 15
36 14 14 15
36 36 36 36
R
16 16 16 16
15 15 15 15
36 36 15 15
35 36 36 36
35 35 35 35
34 34 34 35
34 34 34 34
AN
36 36 36 36
35 35 35 35
34 34 35 35
AK
36 15 15 15
35 35 35 36
35 35 35 35
34 34 34 35
AM
35 36 36
P
17 17 17 17
16 16 16 16
16 16 16 16
34 34
N
17
16 17 17 17
16 16 16 16
L
M
17 17 17
16 16 16 16
16 16 16 16
AC
18 18
17 17 17 17
16 16 16 16
AA
J
K
17 17 17 17
17 17 17 17
H
18
17 17 17 17
17 17 17
U
18 18 18
17 17 17 17
17 17 17 17
F
G
18 18 18 18
18 18 18 18
17 17 17 17
R
E
18 18
18 18 18 18
18 18 18 18
N
D
18 18 18 18
18 18 18 18
18 18 18 18
37
19
18 18 18 18
19 19 19 18
37 37 18 18
B
C
19 18 18 18
19 18 18 18
19 19 19 18
37 37 19 19
37 37 37 37
38 38 37 37
39 38 38 38
39 39 39 39
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 38
39 39 39
M
38 38 38 38
19 19 19
19 19 19 19
19 19 19 19
37 19 19 19
A
19
19 19 19 19 19
19 19 19 19
37 19 19 19
37 37 37 19
38 37 37 37
19 19 19 19
19 19 19 19
37 37 37 19
37 37 37 37
38 38 38 37
38 38 38 38
37 37 19 19
37 37 37 37
38 38 37 37
38 38 38 38
39 39 38 38
39 39 39 39
K
38 37 37 37
38 38 38 38
14 14 14 AN
AP
14 14 14 14 14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_102_052311
Figure 3-71:
116
FFG1157 Package—XC7VX485T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-72
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
38
B
37
39
C
11
D
11
37
39
H
11
11
19
39
J
11
L
11
N
J
18
K
18
39
18
39
11
3
M
18
1
N
17
17
R
10
T
L
18
37
P
10
3
1
10
3
1
2
0
2
0
P
17
R
17
10
T
17
U
16
17
V
10
Y
10
0
Y
16
10
AB
10
AD
2
10
35
0
15
34
AH
36
34
AL
10
10
36
34
3
4
5
6
7
8
9
AN
14
34
2
AM
14
35
AP
AL
14
36
10
1
AK
36
34
10
AJ
14
35
AN
AH
15
35
AK
AM
15 AG
14
34
10
AF
15
35
10
AJ
AE
15
35
10
AD
15
36
AF
10
AC
15
34
10
AG
AB
16
10
AE
AA
16
0
AC
W
16
10
AA
U
V
16
W
G
H
18
37
11
11
18
37
39
38
M
F
19
38
K
E
19
38
11
D
19
37
F
G
C
19
38
11
B
19
38
11
E
A
19
37
36
14 AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_103_052311
Figure 3-72:
FFG1157 Package—XC7VX485T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
117
Chapter 3: Device Diagrams
FFG1158 Package—XC7VX485T
X-Ref Target - Figure 3-73
1
2
3
4
5
6
7
8
A
B
B
B
V
C
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
B
r
A
r
B
E
B
V
D
9
B
E
V
B
V
E
E
C
D
E
E
F
F
G
V
E
V
V
G
V
H
G
E
V
B
E
J
B
G
V
U
H
E
J
K
K
V
L
E
E
V
V
M
L
V
N
E
E
E
E
M
N
P
P
V
R
V
Y
V
V
P
V
V
V
W
V
Y
E
AA
C
2
S
S
M
1
S
S
K
0
L
J
O
D
AB
V
AC
V
V
W
V
Y
E
AA
I
AB
E
E
E
E
E
E
E
E
V
V
AD
T
U
V
U
R
V
T
V
AC
V
AE
AD
AE
AF
AF
V
AG
V
V
AH
AG
V
AJ
AH
AJ
AK
AK
V
AL
E
E
V
V
AM
AL
V
E
AN
AM
E
AN
AP
AP
2
3
4
5
6
7
8
User I/O Pins
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Transceiver Pins
IO_LXXY_#
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Multi−Function Pins
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
s
9
V
1
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_104_090511
Figure 3-73: FFG1158 Package—XC7VX485T Pinout Diagram
118
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-74
1
2
A
3
4
5
6
7
119 119
B 119 119
C
119 119
E
15 15
118 118
118 118
H 118 118
J
115 115
K 118 118
L
117 117
118 118
117 117
117 117
117 117
114 114
36 36 36 36
36 36
36 36 36 36
36
115 115
AL
36 36
114 114
36 36 36 36
114 114
36
114 114
1
2
114 114
3
4
5
6
36 36 34 34
36 36 36 36
36 36 36
36 36 36 36
7
8
9
36 34 34 34
215 215 AH
AJ
215 215
214 214 AK
214 214
35 35 35 35
34 34 35 35
AG
215 215
35 35
AL
214 214
35 35 35
35 35 35 35
215 215 AF
215 215
35 35 35 35
34 35 35 35
34 34 34 34
AE
215 215
35
35 35 35 35
34 34 34 35
34 34 34 34
36 36 36 34
215 215 AD
215 215
35 35 35 35
34 34 35 35
34 34 34 34
AC
216 216
214 214
35 35 35
34 35 35 35
34 34 34 34
36 34 34 34
36 36 36 36
35 35 35 35
34 34 34 35
34 34 34 34
36 36 36 34
36 36 36 36
114 114
AP 114 114
216 216 AB
214 214
34 34 34 34
36 36 34 34
AA
216 216
215 215
115 115
AM 114 114
216 216 Y
215 215
34
W
216 216
216 216
115 115
AK 114 114
216 216 V
216 216
34
U
217 217
216 216
115 115
AH 115 115
217 217 T
216 216
36
R
217 217
217 217
115 115
115 115
AF 115 115
217 217 P
217 217
114 114
N
217 217
217 217
116 116
116 116
AN
14
115 115
AD 115 115
AJ
14
218 218 M
217 217
116 116
116 116
AG
15
L
217 217
218 218
14 14
116 116
AB 116 116
AE
14 14 14 14
17 17 17 14
J
218 218 K
218 218
117 117
116 116
AC
15
16 17 17 17
16 16 16 16
218 218 H
218 218
219 219
14
G
218 218
218 218
116 116
Y 116 116
AA
15 16 16 16
15 15 15
219 219 F
218 218
219 219
14 14 14
17 17 14 14
E
219 219
215 215
117 117
V 116 116
W
15
14
14 14
17 14 14 14
17 17 17 17
16 16 16 17
219 219 D
218 218
14 14 14 14
17 17 17 14
16 16 17 17
16 16 16 16
15 15 15 16
117 117
T 117 117
U
15 15
17 17 17 14
16 17 17 17
16 16 16 16
15 15 16 16
119 119
117 117
16 16 16 17
15 16 16 16
C
219 219
219 219
14 14
14 14 14
219 219 B
219 219
14
14 14 14 14
17 17 14 14
17 17 17 17
A
219 219
14 14 14
17 14 14 14
17 17 17 17
16 16 17 17
15 16 16 16
15 15 15
118 118
P 117 117
R
15
118 118
M 118 118
N
15 15 15 16
14 14 14 14
17 17 17 14
16 17 17 17
16 16 16 16
15 15 15 15
119 119
17 17 17 17
16 16 16 17
15 15 16 16
15 15
118 118
118 118
15 16 16 16
15 15 15 15
15 15 15 15
119 119
G
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
15 15 15
119 119
F 119 119
9
15
119 119
D 119 119
8
15 15 15 15
35 35 35 35
214 214 AM
214 214
35
AN
214 214
214 214
214 214 AP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
ug475_c3_105_052311
Figure 3-74:
FFG1158 Package—XC7VX485T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
119
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-75
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
15 15 15 15
B
15
C
15 15 15
D
15 16 16 16
15 15 15 15
15 15 16 16
15 15 15 15
E
15 15
F
15 15
G
15 15 15 15
H
15
J
15 15 15
15 16 16 16
16 16 16 17
15 16 16 16
L
15 15
M
15 15 15 16
N
15
P
15 15 15
R
15
E
F
G
14 14 14 14
H
J
14 14
K
17 14 14 14
L
14 14 14
14
M
14 14 14 14
N
17 17 14 14
16 17 17 17
16 16 16 16
D
14 14
14
17 17 17 17
16 16 16 17
15 16 16 16
14 14 14 14
14 14 14
17 17 17 14
16 16 17 17
16 16 16 16
C
17 17 17 14
16 17 17 17
16 16 16 16
15 15 16 16
14
17 17 14 14
17 17 17 17
B
14 14 14
17 14 14 14
17 17 17 17
16 16 17 17
A
14 14 14 14
17 17 17 14
16 17 17 17
16 16 16 16
15 15 15 16
K
17 17 17 17
16 16 16 17
17 17 17 14
15
14 14
P
14
R
14
T
T
U
U
V
V
W
W
Y
Y
AA
AA
AB
AB
AC
AC
AD
36
AE
36 36 36 36
AF
36 36
AG
36 36 36 36
AH
36
AJ
36 36
36 36 36 36
36 36 36 36
AM
36
AN
36 36 36
AP
36 36 34 34
36 36 36 36
36 36 36 36
1
2
3
4
5
6
7
8
9
AG
35 35 35 35
AH
36 34 34 34
AK
35 35
AL
35 35 35 35
34 35 35 35
34 34 34 34
AJ
35 35 35 35
35 35 35 35
34 34 34 35
34 34 34 34
36 36 36 34
35
34 34 35 35
34 34 34 34
AF
35 35 35
34 35 35 35
34 34 34 34
36 34 34 34
AE
35 35 35 35
34 34 34 35
34 34 34 34
36 36 36 34
AL
AD
34
34 34 34 34
36 36 34 34
36 36 36 36
AK
34
34 34 35 35
AM
35 35 35
35
AN
35 35 35 35
AP
35 35 35 35
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
ug475_c3_106_052311
Figure 3-75:
120
FFG1158 Package—XC7VX485T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-76
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A
15
B
C
11
D
B
17
11
16
11
14
16
E
A
17
15
11
21
14
15
E
21
F
16
G
11
H
11
16
11
14
15
J
L
11
11
15
14
11
11
T
21
21
16
N
21
P
14
11
21
11
21
11
0
21
R
T
21
U
L
M
21
15
R
J
K
17
P
G
H
21
14
11
N
21
21
17
16
M
21
17
11
K
C
D
21
17
F
21
U
V
V
W
10
Y
10
1
0
20
10
1
0
20
1
0
20
34
20
10
20
Y
20
AA
W
AA
AB
AB
AC
10
AD
10
0
10
20
AD
20
AE
10
0
AF
AE
AF
34
AG
10
AH
10
36
10
35
36
AJ
10
AL
10
10
35
36
35
36
2
3
4
5
6
7
8
9
20
20
34
AP
1
20
34
10
AJ
AK
35
36
10
AG
AH
20
34
AN
20
20
34
AK
AM
20
35
36
AC
20
AL
AM
AN
AP
35
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
ug475_c3_107_052311
Figure 3-76:
FFG1158 Package—XC7VX485T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
121
Chapter 3: Device Diagrams
FFG1761 Package—XC7VX485T
X-Ref Target - Figure 3-77
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
V
A
B
V
C
B
G
V
C
E
D
D
V
E
V
F
E
E
E
G
F
V
G
V
H
H
V
J
V
J
E
K
K
L
V
L
E
M
M
V
N
V
P
K
V
R
V
N
C
V
P
M
R
O
T
T
I
V
U
U
V
V
W
V
E
n
W
n
Y
Y
AA
V
E
AB
AC
V
E
V
E
n
n
AA
S
S
S
S
AB
L
J
AC
AD
AD
AE
AE
AF
AF
AG
AG
Y
AH
AH
AJ
V
E
2
AK
1
AL
V
E
AM
0
V
AP
V
AR n
n
V
AT
n
AU n
n
n
n
AY
n
n
n
1
n
V
n
n
n
3
4
V
n
5
n
n
n
6
n
n
n
n
n
n
n
7
8
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
AJ
AK
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
AM
AN
B
AP
B
AR
n
AT
AU
n
n
n
n
AL
B
n
n
n
B
n
n
n
U
n
n
n
B
n
AV
r
n
r
AW
AY
B
n
B
BA
n
B
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
User I/O Pins
Transceiver Pins
Dedicated Pins
Other Pins
IO_LXXY_#
E
MGTAVCC_G#
C
CCLK_0
S
VP_0
GND
IO_XX_#
V
MGTAVTT_G#
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
V
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
s
n
n
n
9
n
n
n
n
n
n
n
n
E
n
n
n
n
n
E
n
n
n
E
E
n
n
E
n
n
V
2
n
n
V
BB
n
n
V
AV
AW n
n
n
n
D
V
AN
BA
P
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
Multi−Function Pins
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
r
RS0−RS1
MGTHRXN
M
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCO_#
GNDADC_0
VCCBRAM
n
NC
TMS_0
ug475_c3_108_090511
Figure 3-77: FFG1761 Package—XC7VX485T Pinout Diagram
122
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-78
1
2
3
4
A
5
6
7
8
119 119
B
119 119
C 119 119
D
119 119
F
L 117 117
116 116
115 115
16
AE 115 115
114 114
114 114
114 114
AG 114 114
16 16
114 114
114 114
114 114
AJ 114 114
14
113 113
113 113
114 114
AL 113 113
33 33 33 33
113 113
33
113 113
113 113
AN 113 113
33 33
33 33 33
113 113
14
14 14 14
33
113 113
33 33
113 113
33 33
33 33 33
AR
33 33 33
33 33
AU
33 33 33 33
AV
33
AW
33 33 33
AY
33
33 33
BB
33 33
33 33 33 33
1
2
3
4
5
6
7
8
9
13
13
17 17 17 17 AL
15 AR
15 15 15 15 AT
15 15 AU
13 15 15 15
AV
15 15 15 15
15 15 15 AW
13 13 15 15
13 13 13 13
AN
15 15 15 AP
15 15 15 15
13 13 13 15
15 AY
15 15 15 15
13 13 13 15
13 13 13 13
15 15 AM
15 15 15 15
13 13 13 13
13 13 13
17 AK
14 17 17 17
14 14 14 15
13 13 13 13
13 13
AH
17 17 17 AJ
14 14 15 15
13 13 13 13
13 13 13
17 17 AG
17 17 17 17
14 14 14 14
13 13 13 13
33 33 33 33
33 33
13 13
17 AE
17 17 17 17 AF
14 14 14 14
13 13 13 13
AT
BA
14 14 14 14
AC
17 17 17 AD
14 14 14 17
14 14 14 14
Y
17 17 AB
16 17 17 17
14 14 14 16
14 14 14 14
33 33 33 33
17
16 17 17 17
16 16 16 16
14 14 14 14
V
17 17 17 17
16 16 16 17
14 14 14 16
14 14 14 14
T
U
17 17 17 17 AA
16 16 17 17
16 16 16 16
P
R
17 18 18 W
16 17 17 17
16 16 16 16
14 14 16 16
18 18
18 18 18 18
16 16 16 16
16 16 16 16
19
18 18 18 18
18 18 18 18
16 16 16 16
16 16 16
N
19 19 19
18 18 18 18
16 16 16 16
16 16 16 16
115 115
114 114
AP
34 34
L
19 19 M
18 18 18 19
18 18 18 18
34 34 18 18
J
19 19 19 19
19 19 19 19
18 18 18 18
34 18 18 18
34 34 34
115 115
115 115
AK
34 34 34 18
34 34
F
G
K
18 18 18 18
18 18 18 18
E
19
19 19 19 19
18 18 18 19
34 34 18 18
34 34 34
115 115
AC 115 115
AM
34
116 116
115 115
AH
34 34 34 34
116 116
AA 115 115
AF
36 36
116 116
116 116
AD
36 36 36 36
38 36 36 36
116 116
W 115 115
AB
38 38 38 36
38 38
D
H
19 19 19
19 19 19 19
34 34 19 19
34 34 34 34
19 19
35 19 19 19
34 35 35 35
34 34 34 34
34 34 34 34
36 36 34 34
116 116
U 116 116
Y
39 39 39 39
117 117
36 36 36 36
36 36 36 36
35 34 34 35
34 34 34 34
36 36 34 34
19
35 19 19 19
35 35 35 19
B
C
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
39 39 39 38
39 39 39 39
117 117
R 116 116
V
39 39
36 36 36 36
38 38 38 36
39 39 38 38
39 39 39 39
117 117
116 116
T
39 39 39 39
39 39 39
117 117
117 117
N 117 117
39 38 38 38
37 37 37 35
19 19
35 35 19 19
35 35 35 35
35 35 35 35
A
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 38 38
39 39 39
118 118
117 117
P
118 118
117 117
117 117
M
39
38 38 38 37
39 38 38 38
39 39 39 39
118 118
118 118
J 118 118
K
39
39 39
118 118
118 118
39 38 38 38
39 39 39 39
119 119
118 118
H
115
115
119 119
118 118
G 118 118
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
119 119
119 119
E 119 119
9
119 119
15 15 15 15 BA
13 15 15 15
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
ug475_c3_109_052311
Figure 3-78:
FFG1761 Package—XC7VX485T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
123
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-79
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
39 38 38 38
B
39
C
39 39 39 39
D
39 39
E
39 39 39 39
F
39
G
39 39 39
H
39 39 38 38
39 38 38 38
39 39 39
L
39 39
M
39 39 39 39
N
38 38 38 36
39 39 38 38
39 39 39 39
36 36 36 36
39 39 39 38
39 39 39 39
P
38 38 38 36
38 38
36 36 36 36
36 36 36 36
36 36 36 36
38 36 36 36
34 34 34 34
36 36 34 34
36 36
R
34
T
34 34 34 18
U
34 34
V
Y
34 34
AB
16
AC
16 16 16
AD
16 16
14 14 16 16
AG
14
AH
AJ
33 33 33 33
AK
33
AL
33 33 33
AM
14
33 33
14 14 14
33
AN
33 33
AP
33 33
33 33 33
AR
33 33 33
33 33
AU
33 33 33 33
AV
33
AW
33 33 33
AY
33
33 33
BB
33 33
33 33 33 33
1
2
3
4
5
6
7
8
9
13
15 15 AU
AV
15 15 15 15
15 15 15 AW
13 13 15 15
15 AY
15 15 15 15
13 13 13 15
13 13 13 13
15 AR
15 15 15 15 AT
13 15 15 15
13 13 13 13
AN
15 15 15 AP
15 15 15 15
13 13 13 13
13 13 13
15 15 AM
15 15 15 15
13 13 13 15
13 13 13 13
13 13
17 AK
17 17 17 17 AL
14 14 14 15
13 13 13 13
13 13 13
AH
17 17 17 AJ
14 14 15 15
14 14 14 14
13 13 13 13
33 33 33 33
33 33
13
17 17 AG
14 17 17 17
14 14 14 14
13 13 13 13
AT
BA
13 13
17 AE
17 17 17 17
14 14 14 17
14 14 14 14
AC
17 17 17 17 AF
16 17 17 17
14 14 14 14
Y
17 17 AB
16 17 17 17
16 16 16 16
14 14 14 14
33 33 33 33
17
17 17 17 AD
16 16 16 17
14 14 14 14
V
17 17 17 17
14 14 14 16
T
U
17 17 17 17 AA
16 16 17 17
14 14 14 16
P
R
17 18 18 W
16 17 17 17
16 16 16 16
14 14 14 14
18 18
18 18 18 18
16 16 16 16
AF
19
18 18 18 18
16 16 16 16
16 16 16 16
N
19 19 19
18 18 18 18
16 16 16 16
AE
L
19 19 M
18 18 18 18
16 16 16 16
16 16 16 16
19 19 19 19
18 18 18 19
18 18 18 18
34 34 18 18
AA
K
19 19 19 19
18 18 18 18
J
19
18 18 18 18
34 18 18 18
34 34 34
W
19 19 19
19 19 19 19
18 18 18 18
H
35 19 19 19
18 18 18 19
34 34 18 18
34 34 34
F
19 19 G
19 19 19 19
34 34 19 19
34 34 34 34
34 34 34 34
E
35 19 19 19
34 35 35 35
34 34 34 34
D
19
35 35 35 19
35 34 34 35
34 34 34 34
36 36 34 34
B
C
19 19 19
35 35 35 19
35 35 35 35
35 35 35 35
36 36 34 34
36 36 36 36
36 36 36 36
38 38 36 36
39 38 38 38
36 36 36 36
36 36 36 36
38 36 36 36
38 38 38 38
37 37 37 35
19 19
35 35 19 19
35 35 35 35
35 35 35 35
A
35 19 19
35 35 35 35
35 35 35 35
37 37 35 35
37 37 37 37
37 37 37 37
35 35 35 35
37 35 35 35
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
37 37 37 37
37 37 37 37
37 37 37 37
38 38 37 37
38 38 38 38
39 39 39 38
37 37 37 37
38 37 37 37
38 38 38 38
39 39 39 39
J
K
38 38 38 37
39 38 38 38
15 15 15 15 BA
13 15 15 15
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
ug475_c3_110_052311
Figure 3-79:
124
FFG1761 Package—XC7VX485T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-80
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A
37
B
11
C
11
11
D
F
11
H
34
38
L
11
11
39
11
36
11
P
R
0
2
5
10
5
10
10
4
10
10
4
10
10
4
10
10
3
34
2
34
18
18
1
16
0
14
AL
10
10
31
33
10
AP
10
10
10
AV
10
AY
10
31
2
3
4
5
6
7
8
9
AW
15
AY
13
33
32
1
15 AV
13
12
BB
AU
12
32
10
AT
15
13
32
10
BA
12
33
10
AR
15
12
31
10
AP
13
32
AW
AN
13
33
31
AM
15
14
33
31
AT
AU
AL
14
12
31
10
AK
14
32
10
AR
AJ
17
14
33
10
17 AH
14
12
10
AN
AG
14
31
AM
AF
17
0
32
AK
AE
17
16
AH
10
AD
16
3
10
AC
16
3
AJ
AB
17
1
AG
AA
17
AD
AF
Y
16
16
AB
BA
13
13
V
W
18
1
AE
U
34
Y
AC
T
18
2
AA
R
19
18
V
W
P
18
5
T
U
N
19
36
10
M
19
36
39
10
L
34
34
38
11
J
K
35
38
H
19
36
0
N
19
36
39
M
G
35
36
11
F
35
36
39
11
K
E
19
37
39
11
J
35
38
11
D
35
37
11
C
35
37
11
B
19
37
39
11
G
37
38
11
E
A
35
38
15
BB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
ug475_c3_111_052311
Figure 3-80:
FFG1761 Package—XC7VX485T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
125
Chapter 3: Device Diagrams
FFG1927 Package—XC7VX485T
X-Ref Target - Figure 3-81
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
A
B
V
C
E
E
B
V
V
C
V
D
V
E
E
V
V
E
E
V
D
E
E
F
G
F
V
G
V
V
E
E
V
H
V
E
E
V
K
V
E
E
V
V
V
H
J
J
K
L
V
L
V
M
M
N
N
P
V
V
E
V
T
V
U
V
V
V
Y
E
V
E
AB
E
P
V
AG
S
S
S
L
J
G
E
1
0
AD
AE
E
M
K
O
I
AF
V
E
AG
V
AH
V
V
E
n
n
r
r
n
AK
n
E
AJ
V
AK
Y
n
AT
AU n
V
n
n
V
n
AY
V
n
n
V
n
n
V
n
V
BB
n
V
2
n
n
n
n
n
n
n
3
4
n
V
n
5
6
n
B
n
n
B
E
n
U
n
B
E
n
n
E
n
n
n
n
B
n
E
n
E
E
n
n
n
B
n
B
E
n
n
7
8
n
9
n
n
n
n
n
n
V
n
n
n
n
V
n
n
n
n
n
n
n
AL
AM
n
n AN
n
n AR
n
n
AP
AT
AU
AV
n
n AW
n
n
AY
n
n
V
n
n
n
V
n
n
n
V
n
n
n
V
n
n
V
n
n
V
E
E
n
V
E
n
B
n
n
E
E
BA
n
BB
V
BC
n
BD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Transceiver Pins
E
MGTAVCC_G#
IO_XX_#
V
MGTAVTT_G#
Dedicated Pins
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
Multi−Function Pins
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
M
r
n
n
User I/O Pins
s
B
E
n
n
n
n
E
n
n
BC
1
n
n
n
E
n
n
n
BD
n
n
V
E
n
n
n
n
n
n
n
AV
AW n
n
n
AP
AR n
n
n
V
AN n
V
V
n
V
n
AM
BA
AC
V
V
AJ
AB
E
V
C
2
V
AH
D
S
V
V
G
V
AE
AL
AA
V
E
AF
Y
V
E
V
V
AD
W
V
E
E
AC
V
V
E
AA
T
U
E
V
V
R
V
V
E
W
P
V
E
V
R
VCCO_#
GNDADC_0
RS0−RS1
MGTHRXN
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_112_090511
Figure 3-81: FFG1927 Package—XC7VX485T Pinout Diagram
126
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-82
1
2
3
4
A
5
6
7
8
119 119
B
119 119
C 119 119
D
119 119
F
118 118
M
117 117
P
T
V
116 116
Y
115 115
AB
114 114
AF
39 37 37 37
39 39 39 39
18
215 215
39
215 215
114 114
214 214
115 115
215 215
113 113
36 36 36
34 34 34 35
36 36 34 34
36 36
AN
36 36 36 34
AP
36
AR
36 36 36
AT
AV
36
AW
36 36 36
AY
36 36 36 34
214 214 AE
36 36 36 36
36 36
BB
36 36 36 36
BC
36
BD
213 213 AG
8
9
36 34 34 34
35 35 35 35
AP
AR
AT
16
AU
16
AV
16 16 16 16
14 14 14 16
15 15 14 14
AK
AN
14 16 16 16
AW
16 16
AY
14 16 16 16
14 14 14 14
BA
16 16 16
16
BB
16 16 16 16
BC
14 16 16 16
14 14 14 14
15 15 15 14
213 213
16 16 16
15 14 14 14
35 15 15 15
213 213
AL
14 14 14 14
15 15 15 14
35 35 35 15
34 34 34 35
213 213 AJ
16 16
14 14 14 16
15 15 15 15
AH
213 213
14 14 16 16
15 15 15 14
35 35 15 15
34 35 35 35
34 34 34 34
36 36 36 34
36 36 36
7
34 34 34 35
36 36 34 34
AF
214 214
AM
15 14 14 14
35 15 15 15
35 35 35 35
AD
214 214
16
14 14 14 14
15 15 15 15
35 35 35 15
34 34 35 35
36 34 34 34
BA
6
214 214 AC
213 213
16 16 16
AB
215 215
14 16 16 16
14 14 16 16
15 15 15 14
35 35 35 15
34 35 35 35
34 34 34 34
15 14 14 14
15 15 14 14
35 15 15 15
35 35 35 35
34 34 34 35
14 16 16 16
15 15 15 15
35 35 35 15
34 34 35 35
36 36 34 34
36 36 36 36
15 15
35 35 15 15
34 35 35 35
34 34 34 34
36 34 34 34
AU
5
215 215 AA
214 214
213 213
35 35
Y
215 215
213 213
AL
4
215 215 W
214 214
213 213
34
V
216 216
213 213
AM
3
216 216 U
215 215
214 214
36
T
216 216
214 214
113 113
113 113
216 216 R
215 215
214 214
113 113
P
217 217
215 215
115 115
217 217 N
216 216
215 215
19 18 18 18
113 113
113 113
2
19 19 19 18
17 17 19 19
216 216
M
217 217
216 216
18 18 18
K
217 217 L
216 216
113 113
AJ 113 113
1
17 17 17 17
37 37 37 17
19 19 18 18
17 19 19 19
218 218 J
218 218
217 217
216 216
H
218 218
216 216
18 18
114 114
114 114
AK
38 38 39 39
17 17 17 19
37 37 17 17
217 217
19 18 18 18
19 19 19 19
218 218 G
217 217
217 217
18
F
219 219
217 217
113 113
AG 113 113
AH
38 38
17 17 19 19
37 17 17 17
37 37 37 37
39 39 39 37
19 19 18 18
219 219 E
218 218
217 217
114 114
114 114
AE 114 114
115 115
37 37 37 17
39 39 37 37
38 39 39 39
38 38 38
17 17 17 17
18 18
18 18 18
D
219 219
218 218
19 18 18 18
17 19 19 19
219 219 C
218 218
218 218
114 114
114 114
115 115
AD
38
116 116
115 115
115 115
AC 114 114
38 39 39 39
38 38 38 39
115 115
115 115
AA 115 115
38 38
116 116
39 37 37 37
218 218
18
B
219 219
219 219
218 218
18 18 18 18
19 19 19 18
17 17 17 19
37 37 17 17
219 219
18 18 18
A
219 219
219 219
18 18
19 19 18 18
17 17 19 19
37 17 17 17
37 37 37 37
39 39 39 37
38 38 38 39
116 116
116 116
39 39 37 37
38 38 39 39
38 38 38
117 117
116 116
W 115 115
38
116 116
117 117
U 116 116
38 38 38 38
219 219
19 18 18 18
19 19 19 19
17 17 17 19
37 37 37 17
18
18 18 18 18
19 19 19 18
17 17 19 19
37 37 17 17
39 37 37 37
38 39 39 39
19 19 18 18
17 19 19 19
37 17 17 17
39 37 37 37
39 39 39 39
38 38 38 39
117 117
116 116
R 116 116
38 38
117 117
117 117
N 117 117
118 118
117 117
117 117
118 118
L 117 117
38 38 38
17 17 17 19
37 37 37 17
39 39 39 37
38 38 39 39
118 118
118 118
118 118
J 118 118
K
38
39 39 37 37
38 39 39 39
38 38 38 38
118 118
119 119
H
38 38 38 39
38 38
119 119
118 118
G 118 118
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
119 119
119 119
E 119 119
9
119 119
14 14 16 16
BD
16 16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ug475_c3_113_052311
Figure 3-82:
FFG1927 Package—XC7VX485T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
127
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-83
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
38 38 38 39
B
38 38
C
38 38 38 38
D
38
E
38 38 38
F
39 39 37 37
38 39 39 39
39 39 39 37
38 38 39 39
G
38 38
H
38 38 38 38
J
38
K
38 38 38
L
38 39 39 39
39 39 37 37
38 38 39 39
38 38 38 39
38 38
N
38 38 38 39
P
38
R
38 38 38
T
39 37 37 37
38 39 39 39
39 39 37 37
38 39 39 39
39 39 39 37
38 38 39 39
38 38
V
J
K
18
L
19 18 18 18
M
19 19 19 19
N
18 18
P
19 19 18 18
17 19 19 19
17 17 17 17
37 37 37 17
H
18 18
18 18 18
19 19 18 18
17 17 17 19
37 37 17 17
39 37 37 37
39 39 39 39
G
19 18 18 18
17 17 19 19
37 17 17 17
37 37 37 37
F
18 18 18 18
17 19 19 19
17 17 17 17
37 37 37 17
E
18
19 19 19 18
17 17 17 19
37 37 17 17
D
18 18 18
19 19 18 18
17 17 19 19
37 17 17 17
37 37 37 37
39 39 39 37
M
U
37 37 37 17
B
C
18 18
19 18 18 18
19 19 19 19
17 17 17 19
A
18
18 18 18 18
19 19 19 18
17 17 19 19
37 37 17 17
39 37 37 37
19 19 18 18
17 19 19 19
37 17 17 17
39 37 37 37
39 39 39 39
38 38 38 39
17 17 17 19
37 37 37 17
18
T
19 18 18 18
U
19 19 19 18
17 17 19 19
R
18 18 18
V
39
W
W
Y
Y
AA
AA
AB
AB
AC
AC
AD
AD
AE
AE
AF
AF
AG
AG
AH
AH
AJ
36
AK
36 36 36
AL
34
35 35
34 34 34 35
35 35 15 15
36 36 34 34
AM
36 36
AN
36 36 36 34
AP
36
AR
36 36 36
AT
34 35 35 35
34 34 34 34
36 36 34 34
AU
36 36 36 36
AV
36
AW
36 36 36
AY
36 36 36 36
36 36
BB
36 36 36 36
BC
36
2
3
4
5
6
7
8
9
34 34 34 34
36 36 36 34
35 35 35 15
34 34 34 35
36 34 34 34
35 35 35 35
15 15 14 14
AU
16
AV
16 16 16 16
AW
16 16
AY
14 16 16 16
14 14 14 14
BA
16 16 16
16
BB
16 16 16 16
BC
14 16 16 16
14 14 14 14
15 15 15 14
AT
16
14 14 14 16
15 14 14 14
35 15 15 15
AP
AR
14 16 16 16
14 14 14 14
15 15 15 15
AN
16 16 16
14 14 14 16
15 15 15 14
35 35 15 15
34 35 35 35
AM
16 16
14 14 16 16
15 15 15 14
35 15 15 15
35 35 35 35
34 34 34 35
36 36 34 34
36 36 36
1
34 34 35 35
36 34 34 34
14 16 16 16
15 14 14 14
15 15 15 15
35 35 35 15
16
AL
14 14 14 14
15 15 15 14
AK
16 16 16
14 14 16 16
15 15 14 14
35 35 35 15
34 35 35 35
34 34 34 34
36 36 36 34
BA
BD
35 35 35 35
34 34 34 35
15 14 14 14
35 15 15 15
AJ
14 16 16 16
15 15 15 15
35 35 35 15
34 34 35 35
36 34 34 34
15 15
14 14 16 16
BD
16 16
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
ug475_c3_114_052311
Figure 3-83:
128
FFG1927 Package—XC7VX485T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-84
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
39
B
11
C
11
17
11
11
11
F
11
11
38
11
11
11
11
18
11
11
11
11
17
39
10
T
10
V
38
37
10
Y
18
1
AD
10
20
10
36
2
20
35
AL
9
9
9
AP
9
AR
9
9
AT
AV
36
35
34
9
AY
9
35
9
BB
9
BD
34
1
2
3
4
5
6
7
8
9
16
35
16
AW
AY
BA
19
15
36
AV
19
19
14
36
9
AU
19
14
34
9
BC
16
AR
AT
19
19
15
36
BA
19
19
15
36
AP
19
16
14
AL
AM
AN
19
35
9
9
19
15
9
19
19
19
14
34
9
AW
19
16
34
9
AU
19
15
35
AJ
AK
14
36
9
20
16
34
9
AN
AG
AH
20
15
AK
AF
20
0
10
AM
AE
20
2
AC
AD
20
10
AJ
20
20
2
0
AB
20
0
10
AH
AA
0
0
W
Y
20
20
10
AG
20
20
3
10
V
20
20
10
AE
AF
U
1
10
R
T
20
20
3
10
10
P
20
20
10
L
M
20
20
1
10
AB
21
3
10
AC
21
19
39
10
AA
21
20
37
10
10
21
17
10
W
K
N
19
39
10
U
H
21
18
39
10
21
21
21
37
R
21
19
17
N
G
J
18
38
F
18
37
11
P
21
D
21
17
38
M
21
19
39
J
21
C
E
37
37
K
21
17
11
H
21
19
38
B
21
18
39
E
L
21
37
D
G
A
19
38
BB
19
19
19
BC
BD
14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Power Pins
#
VCCO_#
VCCINT
MGTVCCAUX
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
VCCAUX_IO_G#
MGTAVCC
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
ug475_c3_115_052311
Figure 3-84:
FFG1927 Package—XC7VX485T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
129
Chapter 3: Device Diagrams
FFG1930 Package—XC7VX485T
X-Ref Target - Figure 3-85
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
n
B
n
C
n
n
n
n
n
D
n
n
E
n
n
F
n
G
n
H
K
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
J
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
A
n
n
B
n
C
n
D
n
n
n
n
n
n
n
n
n
E
F
G
n
n
H
J
K
L
L
M
M
N
N
P
V
E
R
n
V
n
P
E
R
T
T
U
U
V
V
E
W
V
C
V
E
W
K
Y
Y
M
AA
AA
I
AB
V
E
AC
O
V
E
Y
AD
D
AE
S
S
AB
S
S
AC
L
J
AD
AE
P
V
AF
E
V
AG
V
AH
0
V
AJ
V
E
AL
V
AK
AG
2
E
V
1
G
n
n
E
AM
AN
n
n
n
n
n
AP
V
E
AR
n
V
E
AT
n
n
n
n
AV
V
E
n
V
E
n
AY
BA
BB
V
E
BC
V
E
2
3
4
5
6
7
8
n
n
n
n
n
n
1
9
n
n
n
BD
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
B
n
n
n
B
n
n
n
n
n
n
n
n
n
n
B
U
B
B
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Transceiver Pins
AN
r
AP
B
AR
AT
n
AU
n
n
n
n
n
n
n
n
n
n
n
AV
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
E
MGTAVCC_G#
V
MGTAVTT_G#
Dedicated Pins
n
n AW
n
n
AY
n
n
BA
n
n
BB
n
n
BC
n
BD
C
Other Pins
CCLK_0
S
VP_0
GND
CFGBVS_0
S
VN_0
VCCAUX_IO_G#
MGTVCCAUX_G#
D
DONE_0
S
VREFP_0
VCCAUX
V
IO_LXXY_#
IO_XX_#
Multi−Function Pins
MGTAVTTRCAL
J
DXP_0
S
VREFN_0
VCCINT
G
MGTRREF
L
DXN_0
B
ADV_B
VRN
MGTREFCLK1/0P
B
FCS_B
VRP
MGTREFCLK1/0N
Y
INIT_B_0
B
FOE_B
VREF
MGTXRXP
0
M0_0
B
MOSI
D00−D31
MGTXRXN
1
M1_0
B
FWE_B
A00−A28
MGTXTXP
2
M2_0
B
DOUT_CSO_B
DQS
MGTXTXN
P
PROGRAM_B_0
B
CSI_B
MRCC
E
MGTHAVCC_G#
K
TCK_0
B
PUDC_B
SRCC
V
MGTHAVTT_G#
I
TDI_0
U
RDWR_B
MGTHRXP
O
TDO_0
M
r
r
n
n
n
n
AM
n
n
n
AL
B
n
n
n
B
n
n
n
AK
n
n
n
n
AJ
n
n
n
n
n
n
n
n
AH
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
User I/O Pins
s
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
AU
AW
n
n
V
AF
VCCO_#
GNDADC_0
RS0−RS1
MGTHRXN
AD0P/AD0N−AD15P/AD15N
MGTHTXP
VCCADC_0
EMCCLK
MGTHTXN
VCCBATT_0
VCCBRAM
n
NC
TMS_0
ug475_c3_116_090511
Figure 3-85: FFG1930 Package—XC7VX485T Pinout Diagram
130
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-86
1
2
A
3
4
5
6
7
36 36 36 36
B
36 36
C
36 36 36 36
9
36 36 37 37
D
36 36
E
36 36 36 36
F
36
G
36 36 36
H
8
36 36 37 37
36 36 36 36
J
36 36
36 36 36 36
L
36
37 37 38 38
37 37 37 37
36 36 36 37
36 36 36 36
37
N 118 118
P
118 118
118 118
R 118 118
T
118 118
V
117 117
18 18
17
116 116
116 116
AG 116 116
116 116
116 116
AJ 115 115
14 14 14 14
115 115
115 115
AL 115 115
114 114
AT
114 114
AW 113 113
14
113 113
113 113
113 113
113 113
113 113
1
2
3
4
113 113
5
6
7
8
9
13 13 13 15
14
15 AP
13 13 13 13 AR
13 13 13 13
13 13 13 13
13 13 AT
13 13 13 13
13 13 13 13
13 13 13
AM
15 15 15 AN
15 15 15 15
13 13 13 13
13 13 13
15 15 AL
15 15 15 15
15 15 15 15
13 13 13 13
16 AJ
15 16 16 16 AK
15 15 15 15
15 15 15 15
13 13 13
AG
16 16 16 AH
16 16 16 16
15 15 15 15
15 15 15 15
13
16 16 AF
16 16 16 16
16 16 16 16
15 15 15 15
13 13
14 14 14
AU
13 13 13 AV
13 13
AW
14 14 14
AY
14 14
BA
113 113
BC
BD
14 14
14 14 14
114 114
BA 113 113
BB
14
114 114
113 113
14
14 14 14 14
114 114
114 114
AY
14 14
114 114
15 15 15 16
15 15 15
15 15
14 14 14
115 115
15
14 14
14 14 14
114 114
AU 114 114
AV
14
115 115
115 115
AR 114 114
14
14 14 14 14
115 115
115 115
AN 115 115
AP
14 14
115 115
17 AD
16 16 16 16 AE
16 16 16 16
16 16
AB
17 17 17 AC
16 16 17 17
16 16 16 16
15
Y
17 17 AA
17 17 17 17
16 16 16 16
V
17 W
17 17 17 17
17 17 17 17
16 16 16
116 116
T
U
17 17 17
17 17 17 17
16 16 16 16
16
18 18
17 17 17 17
17 17 17 17
17 17
116 116
P
R
18 18 18 18
17 17 17 17
17 17 17
N
18 18 18 18
18 18 18 18
17 17 17 17
L
18
18 18 18 18
18 18 18 18
K
M
19 19 19
18 18 18 18
18 18 18 18
18 18 18 18
18 18 18 18
117 117
117 117
AM
33 33 18 18
116 116
AE 116 116
AK
34 33
117 117
117 117
AH
34 34 34 33
35 35 34 34
19 19
19 19 19 19
19 19 19 19
19 18 18 18
18 18 18 18
19 19 19 19
19 19 19 19
19 19 19 19
19 19 19 19
33 19 19 19
33 33 33 33
19 19 19 19
19 19 19 19
19 19 19 19
33 33 33 19
34 34 33 33
35 34 34 34
35 35 35 35
38 39 39 35
33 33 19 19
34 34 33 33
35 34 34 34
19 19
117 117
AC 116 116
AF
38 38 38 39
J
33 33
118 118
117 117
AD
39 39 35 35
H
33 33 33 33
34 33 33 33
34 34 34 34
35 35 35 34
F
G
33
117 117
AA 117 117
AB
38 38 38 38
118 118
39 39 35 35
38 38 39 39
E
33 33 33
34 34 34 33
35 35 35 34
D
33 33
34 34 33 33
35 35 34 34
39 35 35 35
38 39 39 39
38 38 38 38
37 38 38
118 118
W 117 117
Y
37
118 118
118 118
U 118 118
38 38 38 39
37 37 38 38
C
34 33 33 33
35 34 34 34
39 35 35 35
39 39 39 39
B
33 33 33 33
34 34 34 34
35 35 35 34
39 39 39 35
38 38 39 39
37 38 38 38
37 37 37 37
M
38 39 39 39
38 38 38 38
37 37 37 38
36 37 37 37
39 39 35 35
33
34 34 34 33
35 35 35 34
A
33 33 33
34 34 33 33
35 35 34 34
39 35 35 35
39 39 39 39
38 38 38 39
35 34 34 34
35 35 35 35
39 39 39 35
38 39 39 39
37 38 38 38
37 37 37 37
39 39 35 35
39 39 39 39
38 38 38 39
37 37 37 38
36 37 37 37
36 36 36 36
38 38 39 39
37 37 38 38
37 37 37 37
36 36 37 37
K
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
37 37 37 37
14 14
BB
14 14 14
BC
14
BD
14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ug475_c3_117_052311
Figure 3-86:
FFG1930 Package—XC7VX485T I/O Banks
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
131
Chapter 3: Device Diagrams
X-Ref Target - Figure 3-87
1
2
A
3
4
5
6
7
36 36 36 36
B
36 36
C
36 36 36 36
9
36 36 37 37
D
36 36
E
36 36 36 36
F
36
G
36 36 36
H
8
36 36 37 37
36 36 36 36
J
36 36
36 36 36 36
L
36
37 37 38 38
37 37 37 37
36 36 36 37
36 36 36 36
37 37 37 37
M
37
38 38 38 39
37 37 38 38
N
37
P
37 38 38
R
38 38 38 38
T
39 39 35 35
38 38 39 39
38 38 38 38
38 38 38 39
H
33 33 33 33
J
33 33
35 34 34 34
34 34 34 33
33 33 18 18
34 33
V
18 18
W
17 17 17 17
Y
17
AA
AB
AD
16 16 16 16
AE
16
AF
16 16 16
14 14 14 14
AJ
14 14
AK
14 14 14 14
AL
14
AM
14 14 14
AN
14
15
15 15 15 16
15 15 15
14 14
14 14 14
AP
14 14
AR
14 14 14 14
AT
14
AU
14 14 14
14
13
16 AJ
15 16 16 16 AK
15 15 AL
15 15 15 15
15 15 15 AN
15 AP
15 15 15 15
13 13 13 13 AR
13 13 13 13
13 13 AT
13 13 13 13
13 13 13 13
AM
15 15 15 15
15 15 15 15
13 13 13 13
AG
16 16 16 AH
16 16 16 16
13 13 13 15
13 13
16 16 AF
16 16 16 16
15 15 15 15
13 13 13
14 14
16 16 16 16 AE
15 15 15 15
15 15 15 15
17 AD
16 16 17 17
16 16 16 16
15 15 15 15
15 15
AB
17 17 17 AC
16 16 16 16
16 16
Y
17 17 AA
17 17 17 17
16 16 16 16
15
V
17 W
17 17 17 17
17 17 17 17
16 16 16 16
T
U
17 17 17
17 17 17 17
17 17 17 17
17 17
AH
18 18
17 17 17 17
AC
AG
P
R
18 18 18 18
17 17 17 17
N
18 18 18 18
18 18 18 18
17 17 17
L
18
18 18 18 18
18 18 18 18
K
M
19 19 19
18 18 18 18
18 18 18 18
18 18 18 18
18 18 18 18
19 19
19 19 19 19
19 19 19 19
19 18 18 18
18 18 18 18
19 19 19 19
19 19 19 19
19 19 19 19
19 19 19 19
33 19 19 19
33 33 33 33
19 19 19 19
19 19 19 19
19 19 19 19
33 33 33 19
34 34 33 33
35 34 34 34
19 19
33 33 19 19
34 34 33 33
35 35 34 34
F
G
33
34 33 33 33
34 34 34 34
35 35 35 35
38 39 39 35
E
33 33 33
34 34 34 33
35 35 35 34
39 39 35 35
U
35 34 34 34
35 35 35 34
D
33 33
34 33 33 33
35 35 34 34
39 35 35 35
38 39 39 39
C
34 34 33 33
39 35 35 35
39 39 39 39
B
33 33 33 33
34 34 34 34
35 35 35 34
39 39 39 35
38 38 39 39
37 38 38 38
33
34 34 34 33
35 35 35 34
39 39 35 35
38 39 39 39
38 38 38 38
37 37 37 38
36 37 37 37
35 35 34 34
A
33 33 33
34 34 33 33
39 35 35 35
39 39 39 39
38 38 38 39
35 34 34 34
35 35 35 35
39 39 39 35
38 39 39 39
37 38 38 38
37 37 37 37
39 39 35 35
39 39 39 39
38 38 38 39
37 37 37 38
36 37 37 37
36 36 36 36
38 38 39 39
37 37 38 38
37 37 37 37
36 36 37 37
K
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
37 37 37 37
13 13 13 13
AU
AV
14 14 14
AW
14
AY
14 14 14
AY
BA
14 14
BA
13 13 13
14
13 13 13 13
13 13 13
13 13 13 AV
13 13
AW
BB
14 14
BB
BC
14 14 14
BC
14
BD
BD
1
2
3
4
5
6
7
8
9
14
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Memory Groupings Pins
#
HP I/O
#
DQS pin
#
HR I/O
#
DCI pin
#
HP I/O − VCCAUX Group 0
#
Memory Byte Group 0
#
HP I/O − VCCAUX Group 1
#
Memory Byte Group 1
#
HP I/O − VCCAUX Group 2
#
Memory Byte Group 2
#
HP I/O − VCCAUX Group 3
#
Memory Byte Group 3
#
HP I/O − VCCAUX Group 4
#
Bank Number
#
HP I/O − VCCAUX Group 5
#
HP I/O − VCCAUX Group 6
#
HP I/O − VCCAUX Group 7
ug475_c3_118_052311
Figure 3-87:
132
FFG1930 Package—XC7VX485T Memory Groupings
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Virtex-7 FPGAs Device Diagrams
X-Ref Target - Figure 3-88
1
2
3
4
5
6
A
B
C
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
37
39
36
36
G
H
36
39
37
34
39
N
11
33
R
11
T
11
34
18
3
11
11
Y
7
2
6
2
AB
11
11
AC
11
AE
AF
11
11
AG
11
11
AH
AK
10
0
10
AL
12
10
30
AP
10
12
10
AT
10
14
10
13
10
AY
32
10
30
BB
10
10
10
10
30
1
2
3
4
5
6
7
8
9
11 BB
11
30
BD
BA
11
14
32
AY
11
12
31
10
AW
11
10
31
BC
AV
13
14
BA
AU
13
12
32
AT
13
10
31
10
AP
AR
13
30
AV
AN
13
12
32
AW
15 AM
15
12
31
AU
AL
15
10
30
10
AK
15
14
10
AR
AJ
16
15
14
32
AH
15
10
31
AN
AG
16
14
30
AM
AF
16
16
32
0
10
AE
16
0
31
10
AD
16
0
4
AC
17
4
11
AJ
17 AB
17
0
4
AA
1
5
Y
17
17
1
5
W
17
1
5
AD
V
18
2
6
11
U
18
3
6
AA
T
18
33
3
11
P
R
18
35
V
N
19
18
34
38
W
19 M
33
39
U
L
19
19
35
11
K
19
35
11
J
20
19
34
37
P
H
20
20
33
38
G
20
34
35
M
F
21
33
38
37
L
20
39
36
K
E
20
35
37
D
21
34
38
C
21
33
38
36
J
21
39
36
B
21
35
37
E
A
21
34
37
D
F
33
38
12
11
BC
BD
11
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Power Pins
#
VCCO_#
MGTVCCAUX
VCCINT
#
MGTVCCAUX_G# or MGTHVCCAUX_G#
#
MGTAVCC_G# or MGTHAVCC_G#
#
MGTAVTT_G# or MGTHAVTT_G#
VCCAUX
#
MGTAVCC
VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
MGTAVTT
GND
GNDADC_0
ug475_c3_119_052311
Figure 3-88:
FFG1930 Package—XC7VX485T Power and GND Placement
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
133
Chapter 3: Device Diagrams
134
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
Chapter 4
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the following
7 series FPGA packages:
•
FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 136
•
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 137
•
FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 138
•
FF(G)676 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 139
•
FF(G)900 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 140
•
FF(G)901 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 141
•
FF(G)1156 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch), page 142
•
FF(G)1157 and FF(G)1158 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch), page 143
•
FF(G)1761 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch), page 144
•
FH(G)1761 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch), page 145
•
FF(G)1926, FF(G)1927, FF(G)1928, and FF(G)1930 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch), page 146
•
FL(G)1925, FL(G)1928, and FL(G)1930 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm
Pitch), page 147
Note: This chapter is intentionally missing drawings.
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7 Series FPGAs Packaging
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www.xilinx.com
135
Chapter 4: Mechanical Drawings
FB(G)484 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-1
ug475_c4_01_031511
Figure 4-1:
136
FB(G)484 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs) (1.0 mm Pitch)
FB(G)676 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-2
ug475_c4_02_031511
Figure 4-2:
FB(G)676 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
137
Chapter 4: Mechanical Drawings
FB(G)900 Flip-Chip Bare-Die BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-3
ug475_c4_03_031511
Figure 4-3:
138
FB(G)900 Flip-Chip Bare-Die BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
FF(G)676 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch)
FF(G)676 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-4
ug475_c4_04_031511
Figure 4-4:
FF(G)676 Flip-Chip BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
139
Chapter 4: Mechanical Drawings
FF(G)900 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-5
ug475_c4_05_031511
Figure 4-5:
140
FF(G)900 Flip-Chip BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
FF(G)901 Flip-Chip BGA (Kintex-7 FPGAs) (1.0 mm Pitch)
FF(G)901 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-6
ug475_c4_06_031511
Figure 4-6:
FF(G)901 Flip-Chip BGA Package Specifications for Kintex-7 FPGAs
www.BDTIC.com/XILINX
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
www.xilinx.com
141
Chapter 4: Mechanical Drawings
FF(G)1156 Flip-Chip BGA (Kintex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-7
ug475_c4_07_052311
Figure 4-7:
142
FF(G)1156 Flip-Chip BGA Package Specification for Kintex-7 FPGAs
www.BDTIC.com/XILINX
www.xilinx.com
7 Series FPGAs Packaging
UG475 (v1.4) October 17, 2011
FF(G)1157 and FF(G)1158 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch)
FF(G)1157 and FF(G)1158 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-8
ug475_c4_08_052311
Figure 4-8:
FF(G)1157 and FF(G)1158 Flip-Chip BGA Package Specification for Virtex-7 FPGAs
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Chapter 4: Mechanical Drawings
FF(G)1761 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-9
ug475_c4_09_091411
Figure 4-9: FF(G)1761 Flip-Chip BGA Package Specification for Virtex-7 FPGAs
144
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FH(G)1761 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch)
FH(G)1761 Flip-Chip BGA (Virtex-7 FPGAs)
(1.0 mm Pitch)
X-Ref Target - Figure 4-10
ug475_c4_10_100311
Figure 4-10:
FF(G)1761 Flip-Chip BGA Package Specification for Virtex-7 FPGAs
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Chapter 4: Mechanical Drawings
FF(G)1926, FF(G)1927, FF(G)1928, and FF(G)1930 Flip-Chip BGA
(Virtex-7 FPGAs) (1.0 mm Pitch)
X-Ref Target - Figure 4-11
ug475_c4_11_100311
Figure 4-11: FF(G)1926, FF(G)1927, FF(G)1928, and FF(G)1930 Flip-Chip BGA Package Specification
for Virtex-7 FPGAs
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FL(G)1925, FL(G)1928, and FL(G)1930 Flip-Chip BGA (Virtex-7 FPGAs) (1.0 mm Pitch)
FL(G)1925, FL(G)1928, and FL(G)1930 Flip-Chip BGA
(Virtex-7 FPGAs) (1.0 mm Pitch)
X-Ref Target - Figure 4-12
ug475_c4_12_100311
Figure 4-12:
FL(G)1925, FL(G)1928, and FL(G)1930 Flip-Chip BGA Package Specification
for Virtex-7 FPGAs
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Chapter 4: Mechanical Drawings
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Chapter 5
Thermal Specifications
Summary
This chapter provides thermal data associated with 7 series FPGAs packages. The
following topics are discussed:
•
Introduction
•
Power Management Strategy
•
Some Thermal Management Options
•
Support for Compact Thermal Models (CTM)
•
References
Introduction
7 series FPGAs are offered exclusively in thermally efficient flip-chip BGA packages. These
0.5 mm, 0.8 mm, and 1.0 mm flip-chip packages range in pin-count from the smaller
10 x 10 mm CPG236 to the 45 x 45 mm FFG1930. The suite of packages is used to address
the various power requirements of the 7 series devices. All 7 series devices are
implemented in the 28 nm process technology.
Similar to Virtex®-6 FPGAs, all 7 series devices feature the versatile SelectIO™ resources
that support a variety of I/O standards. They also include analog-to-digital converters
(XADC), DSPs, and other traditional features and blocks (such as block RAM) contained in
earlier Virtex products.
In line with Moore's law, the transistor count in this family of devices has been increased
substantially. Though several innovative features at the silicon level have been deployed to
minimize power dissipation, including leakage at the 28 nm node, these products have
more densely packed transistors and embedded blocks with the capability to run faster
than before. Thus, a fully configured 7 series FPGA design that exploits the fabric speed
and incorporates several embedded circuits and systems can present power consumption
challenges that must be managed.
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in
a user application are not known to the component supplier. Therefore, it remains a
challenge for Xilinx to predict the power requirements of a given FPGA when it leaves the
factory. Accurate estimates are obtained when the board design takes shape. For this
purpose, Xilinx offers and supports a suite of integrated device power analysis tools to
help users quickly and accurately estimate their design power requirements. 7 series
devices are supported similarly to previous FPGA products. The uncertainty of design
power requirements makes it difficult to apply canned thermal solutions to fit all users.
Therefore, Xilinx devices do not come with preset thermal solutions. The user’s operating
conditions dictate the appropriate solution.
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Chapter 5: Thermal Specifications
Table 5-1 shows the thermal resistance data for 7 series devices (grouped in the packages
offered). The data includes junction-to-ambient in still air, junction-to-case, and
junction-to-board data based on standard JEDEC four-layer measurements.
•
Thermal data is available on the Xilinx website at:
http://www.xilinx.com/cgi-bin/thermal/thermal.pl.
•
Compact package thermal models for these products are available on the Xilinx
support download center (under the Device Model tab) at:
http://www.xilinx.com/support/download/index.htm
Table 5-1:
Thermal Resistance Data—All Devices
Package
Package
Body Size
JA
(°C/W)
JB
(°C/W)
JC
(°C/W)
JA (°C/W)
@ 250 LFM
JA (°C/W)
@ 500 LFM
JA (°C/W)
@ 750 LFM
XC7A8
41.0
23.4
8.89
35.2
33.3
32.0
XC7A15
41.0
23.4
8.89
35.2
33.3
32.0
XC7A30T
26.1
10.9
4.94
21.1
19.7
18.8
XC7A50T
26.1
10.9
4.94
21.1
19.7
18.8
XC7A8
29.6
16.1
7.41
24.6
23.2
22.4
XC7A15
29.6
16.1
7.41
24.6
23.2
22.4
XC7A30T
24.5
11.3
4.67
19.6
18.4
17.6
XC7A50T
24.5
11.3
4.67
19.6
18.4
17.6
XC7A100T
21.9
8.8
3.37
16.8
15.6
15.0
XC7A8
31.2
21.1
11.08
26.5
25.0
24.2
XC7A15
31.2
21.1
11.08
26.5
25.0
24.2
XC7A30T
24.3
14.2
7.14
19.8
18.5
17.7
XC7A50T
24.3
14.2
7.14
19.8
18.5
17.7
XC7A100T
21.8
11.0
5.24
16.9
16.6
14.9
XC7A200T
14.2
4.6
0.05
10.2
9.1
8.6
XC7A350T
14.3
4.2
0.05
9.6
8.6
8.1
XC7A30T
19.7
11.3
7.01
15.1
14.0
13.5
XC7A50T
19.7
11.3
7.01
15.1
14.0
13.5
XC7A100T
17.9
9.1
5.48
13.3
12.2
11.7
XC7A200T
14.3
4.6
0.05
9.5
8.4
7.9
XC7A350T
13.3
4.0
0.04
8.7
7.7
7.1
XC7A100T
16.8
8.5
5.2
12.3
11.3
10.8
XC7A200T
10.2
3.7
0.33
6.4
5.4
4.8
XC7A350T
9.8
2.2
0.23
6.1
5.2
4.6
Devices
Artix-7 FPGAs
CP(G)236
10 x 10
CS(G)225
12 x 12
CS(G)324
FT(G)256
FB(G)484
FG(G)484
15 x 15
17 x 17
23 x 23
23 x 23
FB(G)676
27 x 27
FG(G)676
27 x 27
FF(G)1156
35 x 35
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Introduction
Table 5-1:
Package
Thermal Resistance Data—All Devices (Cont’d)
Package
Body Size
JA
(°C/W)
JB
(°C/W)
JC
(°C/W)
JA (°C/W)
@ 250 LFM
JA (°C/W)
@ 500 LFM
JA (°C/W)
@ 750 LFM
XC7K70T
16.4
6.6
0.16
12.0
11.0
10.4
XC7K160T
13.5
5.0
0.06
10.4
9.4
8.8
XC7K70T
15.8
6.8
0.16
11.7
10.8
10.2
XC7K160T
12.8
5.1
0.09
9.8
8.9
8.3
XC7K325T
11.8
4.0
0.04
9.1
8.1
7.5
XC7K410T
11.1
3.6
0.03
8.5
7.5
7.0
XC7K325T
11.3
4.1
0.04
8.8
7.9
7.3
XC7K410T
10.6
4.3
0.04
8.3
7.3
6.8
XC7K160T
10.5
4.4
0.41
7.4
6.4
5.8
XC7K325T
9.5
3.7
0.25
7.1
6.1
5.6
XC7K410T
9.3
3.4
0.19
6.8
5.9
5.4
XC7K325T
8.4
2.6
0.24
6.1
5.3
5.0
XC7K410T
8.2
2.6
0.19
5.9
5.1
4.7
XC7K355T
8.6
3.6
0.22
6.1
5.3
4.8
XC7K420T
8.1
3.2
0.19
6.0
5.2
4.7
XC7K480T
7.6
3.2
0.17
5.9
5.1
4.6
XC7K420T
7.3
3.2
0.19
5.8
4.9
4.4
XC7K480T
7.0
3.1
0.17
5.6
4.8
4.3
Devices
Kintex-7 FPGAs
FB(G)484
23 x 23
FB(G)676
27 x 27
FB(G)900
31 x 31
FF(G)676
27 x 27
FF(G)900
31 x 31
FF(G)901
31 x 31
FF(G)1156
35 x 35
Virtex-7V FPGAs
FF(G)1157
35 x 35
XC7V585T
6.9
2.2
0.13
5.4
4.6
4.3
FF(G)1761
42.5 x 42.5
XC7V585T
5.9
2.1
0.11
4.6
3.9
3.6
FL(G)1761
42.5 x 42.5
XC7V1500T
FH(G)1761
42.5 x 42.5
XC7V2000T
FL(G)1925
45 x 45
XC7V2000T
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151
Chapter 5: Thermal Specifications
Table 5-1:
Package
Thermal Resistance Data—All Devices (Cont’d)
Package
Body Size
JA
(°C/W)
JB
(°C/W)
JC
(°C/W)
JA (°C/W)
@ 250 LFM
JA (°C/W)
@ 500 LFM
JA (°C/W)
@ 750 LFM
XC7VX330T
7.4
2.3
0.18
5.6
4.8
4.4
XC7VX415T
7.0
2.1
0.14
5.4
4.7
4.3
XC7VX485T
6.7
2.4
0.11
5.3
4.6
4.2
XC7VX690T
6.1
2.0
0.04
4.8
4.2
3.8
XC7VX415T
6.8
2.2
0.13
5.4
4.7
4.3
XC7VX485T
6.4
2.2
0.11
5.2
4.6
4.2
XC7VX550T
6.5
2.1
0.09
5.2
4.5
4.2
XC7VX690T
6.2
2.1
0.04
4.8
4.2
3.8
XC7VX330T
6.4
2.3
0.19
4.8
4.1
3.7
XC7VX485T
5.8
2.0
0.13
4.5
3.9
3.5
XC7VX690T
5.4
1.9
0.09
4.3
3.7
3.4
XC7VX690T
4.9
1.8
0.07
4
3.5
3.1
XC7VX980T
4.8
1.7
0.04
3.8
3.2
2.9
XC7VX415T
5.6
1.8
0.14
4.3
3.7
3.3
XC7VX485T
5.2
1.8
0.13
4.5
3.8
3.4
XC7VX550T
5.4
1.8
0.09
4.2
3.6
3.3
XC7VX690T
4.9
1.8
0.07
3.8
3.2
2.9
XC7VX980T
4.8
1.7
0.04
4.0
3.4
3.1
XC7VX485T
5.5
1.8
0.11
4.3
3.6
3.3
XC7VX690T
5.2
1.7
0.04
3.9
3.3
3.0
XC7VX980T
5.0
1.7
0.04
3.8
3.2
2.9
Devices
Virtex-7VX FPGAs
FF(G)1157
FF(G)1158
FF(G)1761
FF(G)1926
FF(G)1927
FF(G)1928
FF(G)1930
152
35 x 35
35 x 35
42.5 x 42.5
45 x 45
45 x 45
45 x 45
45 x 45
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Power Management Strategy
Power Management Strategy
Xilinx relies on a multi-prong approach with regards to the heat-dissipating potential of
7 series devices:
•
Design and Silicon
Significant power reduction in 7 series devices at the 28 nm node is achieved through
innovative process and circuit design. For example, transistor static leakage current is
minimized by more than 50 percent (comparable devices) by deploying multi-gate
oxide transistors in the power-efficient 7 series architecture. Despite these
improvements and a lower operating voltage, the base transistor counts are higher for
these 7 series devices. They pack higher gate densities and the fabric is faster.
Compared to previous generations, the power consumption is lower for the same
design (same function and gate density) in a 7 series FPGA implementation.
However, the increased resources and functionality associated with these higher gate
density devices and faster switching fabric implies that more computation is possible
in shorter time. Associated with this improved functionality is potential higher power
dissipation that would have been worse without the silicon and device-based
innovations.
•
Packaging
At the package component level, Xilinx has selected the more efficient flip-chip BGA
packages, which present a low thermal path to the outside. This package incorporates
a heat spreader with a thermal interface material (TIM), as shown in Figure 5-1.
X-Ref Target - Figure 5-1
Thermal Interface Material (TIM)
Lid-Heat Spreader
Die
Substrate
UG475_c05_01_082610
Figure 5-1:
Heat Spreader with Thermal Interface Material
Materials with better thermal conductivity and consistent process applications deliver
low thermal resistance up to the heat spreader. The junction-to-case thermal resistance
(top of heat spreader) of all 7 series FPGA packages is typically less than 0.20°C/W.
These packages deliver a low resistance platform for heat sink applications.
The parallel effort to ensure optimized package electrical return paths has produced an
added benefit of enhanced power and ground plane arrangement in the packages. The
boost in copper density on the planes improves the overall thermal conductivity
through the laminate. In addition, the extra dense and distributed via fields in the
package increase the vertical thermal conductivity. These packages offer up to 20%
lower JB compared to previous flip-chips packages.
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Chapter 5: Thermal Specifications
•
Heat Sinking Solutions at the System Level
Depending on the system's physical as well as mechanical constraints, the expectation
is that the thermal budget is maintained with custom or OEM heat sink solutions,
providing the third prong in the thermal management strategy. At this point, Xilinx
has left the heat sink solution to the system-level designers who can tailor the design
and solution to the constraints of their systems, being fully aware that the part has
certain inherent capabilities for delivering the heat to the surface.
Heat sink solutions do exist and can be effective on these low JB flip-chip platforms.
Table 5-2 illustrates a finned heat sink solution matrix in Network environment (1U
and 2U) arrangement for 35 mm packages and up for power ranging from 15W to 40W.
The AAVID standard finned heat sink offerings are used to illustrate the coverage
given thermal budgets of T = 35°C and T = 45°C scenarios. Other heat sink
configurations can be explored similarly.
Table 5-2:
Finned Heat Sink Solution Matrix for Large Flip-chip BGA in Network
Package Power
(W)
15W
25W
35W
40W
35 x 35 mm
FF1156
T=35°C
42.5 x 42.5 mm
FF1761
T=45°C
T=35°C
T=45°C
(5)
Note 1
Note 1
2U (6)
Note 1
Note 1
1U
1U (5)
Note 4
Note 2
Note 4
Note 2
2U (6)
Note 2
Note 1
Note 2
Note 1
1U (5)
Note 4
Note 3
Note 4
Note 3
(6)
Note 4
Note 2
Note 4
Note 2
1U (5)
–
–
Note 4
Note 3
2U (6)
–
–
Note 3
Note 2
2U
Notes:
1.
2.
3.
4.
5.
6.
Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.
Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.
Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.
No standard. AAVID finned solution below 600 LFM—custom finned might be required.
For 1U Height—(max heat sink height = 26 mm)
For 2U Height—(max heat sink height = 64 mm
The 7 series FPGA packages can be grouped into medium- and high-performance
packages based on their power handling capabilities. All 7 series FPGA packages can use
thermal enhancements, ranging from simple airflow to schemes that can include passive as
well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages
where system designers have the option to further enhance the packages with bigger and
more elaborate heat sinks to handle excesses of 25W with arrangements that consider
system –physical constraints as illustrated in Table 5-2.
154
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Some Thermal Management Options
Some Thermal Management Options
The flip-chip thermal management chart in Figure 5-2 illustrates simple but incremental
power management schemes that can be applied on a flip-chip BGA package.
X-Ref Target - Figure 5-2
Low End
1–6W
Bare Package with
Moderate Air
8–12°C/W
Mid Range Passive H/S + Air
5–10°C/W
4–10W
Bare Package
Package can be
used with moderate
airflow within a system
Packaged Used with
Various Forms of
Passive Heat Sinks
Heat spreader techniques
High End
Active Heat Sink
2–3°C/W or Better
8–25W
Package Used with
Active Heat Sinks
TEC and board level
heat spreader techniques
UG475_c5_02_082610
Figure 5-2:
Thermal Management Options for Flip-Chip BGA Packages
•
For moderate power dissipation (less than 6W), the use of passive heat sinks and heat
spreaders attached with thermally conductive double-sided tapes or retainers (with
TIM around 0.2°C/W) can offer quick thermal solutions in these packages.
•
The use of lightweight, finned, external, passive heat sinks can be effective for
dissipating up to 10–25W in the bigger packages. The more efficient external heat
sinks tend to be tall and heavy. To help protect component joints from heat sink
induced stress cracks, the use of spring-loaded pins or clips that transfer the mounting
stress to a circuit board is advisable whenever a bulky heat sink is considered.
•
As stated earlier, the flip-chip BGA packages offered for 7 series devices are thermally
enhanced BGAs with the die facing down. These packages have an exposed metal
heat sink at the top. These high-end thermal packages lend themselves to the
application of efficient external heat sinks (passive or active) for further heat removal
efficiency. Again, precautions must be taken to prevent component damage when a
bulky heat sink is attached. The thermal interface resistance needs to be controlled to
take full advantage of these packages.
•
An active heat sink might include a simple heat sink incorporating a mini fan or even
a Peltier Thermoelectric Cooler (TEC) with a fan to carry away any dissipated heat.
When considering the use of a TEC for heat management, consultation with experts in
using the device is important because these devices can be reversed and cause
damage to components. Also condensation can be an issue with these devices.
•
The printed circuit board on which the package is mounted can have a significant
impact on thermal performance. As much as 60 to 80 percent of the dissipated heat
can go through the BGA balls and thus to the board. A typical systems board is larger
than the standard 4 x 4 in JEDEC thermal board. Components mounted on these
boards with multiple copper layers and several internal vias show low effective
junction-to-ambient thermal resistances.
Table 5-3 shows this impact as an FF1156 flip-chip package's effective junction to
ambient resistance is changed depending on the mounting board.
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Chapter 5: Thermal Specifications
Table 5-3:
Impact of Mounted Board Characteristics on JA(FF1156)
JA (°C/W) for Different Board Sizes
Xilinx 35 x 35mm
FF1156
Layer Count of
Mounted Board
4 x 4 in
10 x 10 in
20 x 20 in
4
9.1 (1)
8.3
–
8
8.0
5.5
4.9
12
7.5
4.7
4.4
16
7.2
4.5
4.2
24
–
4.3
4.0
Notes:
1. Base JEDEC Mount Conditions
•
Designs can be implemented to take advantage of the board's ability to spread heat.
The effect of the board is dependent on its size and how it conducts heat. Board size,
the level of copper traces, and the number of buried copper planes all lower the
junction-to-ambient thermal resistance for a package mounted on the board. The cold
ring junction-to-board thermal data for 7 series FPGA packages are given in Table 5-1.
Users need to be aware that a direct heat path to the board from a component also
exposes the component to the effect of other heat sources on the board, particularly if
the board is not cooled effectively. An otherwise cooler component can be heated by
other heat contributing components on the board.
Support for Compact Thermal Models (CTM)
Table 5-1 provides the traditional thermal resistance data for 7 series devices. These
resistances are measured using a prescribed JEDEC standard that might not necessarily
reflect the user’s actual board conditions and environment. The quoted JA and JC
numbers are environmentally dependent, and JEDEC has traditionally recommended that
these be used with that awareness. For more accurate junction temperature prediction,
these might not be enough, and a system-level thermal simulation might be required.
Though Xilinx continues to support these figure of merit data, for 7 series FPGAs,
boundary conditions independent compact thermal models (BCI-CTM) are also available
to assist users in their thermal simulations.
Two-resistor as well as eight to ten-resistor network models are offered for all 7 series
devices. These compact models seek to capture the thermal behavior of the packages more
accurately at predetermined critical points (junction, case, top, leads, and so on) with the
reduced set of nodes as illustrated in Figure 5-3.
Unlike a full 3D model, these are computationally efficient and work well in an integrated
system simulation environment. Delphi CTM models are available on the Xilinx support
download center (under the Device Model tab) at:
http://www.xilinx.com/support/download/index.htm
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References
X-Ref Target - Figure 5-3
DELPHI BCI-CTM Topology for
FCBGA
TI
Two Resistor Model
TO
Rjc
Junction
Junction
SIDE
Rjb
BI
BO
UG475_c05_03_082610
Figure 5-3: Thermal Model Topologies
The CTM models are based on the DELPHI approach that JEDEC has proposed. Since the
JEDEC neutral (XML) format proposal has not been adopted yet, the DELPHI approach is
used to generate these files and the data saved in the NATIVE and proprietary file formats
of the targeted CFD tools - rather than follow a neutral file format. The CTM libraries are
available in Flotherm (PDML) format – good for V5.1 and above and Icepack (version 4.2
and above) format.
References
The following websites contain additional information on heat management and contact
information.
•
http://www.wakefield.com
•
http://www.aavidthermalloy.com
•
http://www.qats.com
Refer to the following websites for interface material sources:
•
Power Devices - http://www.powerdevices.com
•
Bergquist Company - http://www.bergquistcompany.com
•
AOS Thermal Compound - http://www.aosco.com
•
Chometrics - http://www.chomerics.com
•
Kester - http://www.kester.com
Refer to the following websites for CFD tools Xilinx supports with thermal models.
•
Flomerics - Flotherm & FloPCB - http://www.flomerics.com
•
Fluent - Icepak - http://www.icepak.com
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Chapter 5: Thermal Specifications
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Chapter 6
Package Marking
All 7 series devices have package top-markings similar to the examples shown in
Figure 6-1 and Figure 6-2 and explained in Table 6-1.
X-Ref Target - Figure 6-1
XC7K325T
Device Type
Package
Speed Grade
TM
FF900xxxXXXX
DDxxxxxxxA
1C ES
Operating Range
Figure 6-1:
Lot Code
Engineering Sample
ug475_c6_01_031511
Kintex-7 Device Package Marking
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Date Code
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Chapter 6: Package Marking
X-Ref Target - Figure 6-2
XC7VX485T
Device Type
TM
FFG1761xxxXXXX
DDxxxxxxxA
1C ES
Package
Speed Grade
Date Code
Lot Code
Engineering Sample
Operating Range
Figure 6-2:
Table 6-1:
ug475_c6_02_081011
Virtex-7 Device Package Marking
Xilinx Device Marking Definition—Example
Item
Definition
Xilinx Logo
Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family Brand
Logo
Device family name with trademark and trademark-registered status. This line is optional and could
appear blank.
1st Line
Device type.
2nd Line
Package code, circuit design revision, the location code for the wafer fab, the geometry code, and date
code.
A G in the third letter of a package code indicates a Pb-free RoHS compliant package. For more details
on Xilinx Pb-Free and RoHS Compliant Products, see: http://www.xilinx.com/pbfree.
3rd Line
Ten alphanumeric characters for Assembly, Lot, and Step information. The last digit is usually an A or
an M if a stepping version does not exist.
Device speed grade and temperature range. When not marked on the package, the product is
considered to operate at the commercial (C) temperature range. For more information on the ordering
codes, see DS180: 7 Series FPGAs Overview.
Other variations for the 4th line:
L2E
The L2E indicates a -2LE device. The -2L devices operate at either of two voltages, 0.9V
and 1.0V. The E is for the extended temperature operating range. For more information,
see the specific device’s data sheet at:
http://www.xilinx.com/support/documentation/7_series.htm#156339.
1C xxxx
The xxxx indicates the SCD for the device. An SCD is a special ordering code that is not
always marked in the device top mark.
1C ES
The ES indicates an Engineering Sample.
4th Line
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Appendix A
Recommended PCB Design Rules for
BGA Packages
Xilinx provides the diameter of a land pad on the component side. This information is
required prior to the start of the board layout so the board pads can be designed to match
the component-side land geometry. The typical values of these land pads are described in
Figure A-1 and summarized in Table A-1. For Xilinx® BGA packages, Non-Solder Mask
Defined (NSMD) pads on the board are suggested to allow a clearance between the land
metal (diameter L) and the solder mask opening (diameter M) as shown in Figure A-1. The
space between the NSMD pad and the solder mask as well as the actual signal trace widths
depend on the capability of the PCB vendor. The cost of the PCB is higher when the line
width and spaces are smaller.
X-Ref Target - Figure A-1
VL
VH
W
D
L
M
Mask Opening outside of Land
e
UG475_aA_01_082610
Figure A-1:
Suggested Board Layout of Soldered Pads for BGA Packages
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Appendix A: Recommended PCB Design Rules for BGA Packages
Table A-1:
Recommended PCB Design Rules for All FF(G) Packages
Design Rule
FF(G) Packages
(Dimensions in mm)
Component Land Pad Diameter (SMD)(1)
0.53
Solder Land (L) Diameter
0.45
Opening in Solder Mask (M) Diameter
0.55
Solder (Ball) Land Pitch (e)
1.00
Line Width Between Via and Land (w)
0.13
Distance Between Via and Land (D)
0.70
Via Land (VL) Diameter
0.61
Through Hole (VH) Diameter
0.300
Notes:
1. Component land pad diameter refers to the pad opening on the component side (solder
mask defined).
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