Virtex-5 RocketIO GTP Transceiver Characterization Report

Virtex-5 RocketIO
GTP Transceiver
Characterization
Report
RPT056 (v1.1) May 20, 2008
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the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
06/08/07
1.0
Initial Xilinx release.
05/20/08
1.1
• Added figures that were missing or occupied by placeholders in previous revision.
• Added and/or updated figures and table entries for 3.75 Gb/s operation.
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RPT056 (v1.1) May 20, 2008
Table of Contents
Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
15
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
23
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 1: Introduction
Virtex-5 LXT and SXT FPGA Platforms Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RocketIO GTP Transceiver Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scope of Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup and Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterization Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterization Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterization Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characterization Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
27
31
32
32
34
34
34
Summary of Characterization Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 2: PMA Transmitter Characterization
TX Near-End Output Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 100 Mb/s, Oversampled . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 500 Mb/s, Oversampled . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.0 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.0 Gb/s, 200 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.5 Gb/s, 62.5 MHz REFCLK. . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.5 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
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37
40
40
41
41
42
42
43
43
44
44
45
45
3
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TX Near-End Eye Diagram at 2.5 Gb/s, 250 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 3.2 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Near-End Eye Diagram at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
47
47
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TX Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 500 Mb/s Using Oversampling . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.0 Gb/s Using 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.0 Gb/s Using 200 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.5 Gb/s Using 62.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.5 Gb/s Using 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.5 Gb/s Using 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 2.5 Gb/s Using 250 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Generation at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
TX REFCLK to TX Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 1.0 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 2.0 Gb/s, 200 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 2.5 Gb/s, 62.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 2.5 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 2.5 Gb/s, 250 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Jitter Transfer at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
69
69
69
70
70
71
71
72
72
73
TX Output Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time as a Function of TXDIFFCTRL . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time as a Function of Process . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time as a Function of Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Rise and Fall Time as a Function of Temperature . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
77
77
78
79
80
81
82
83
84
85
TX Output Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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TX Amplitude Test, Histograms by Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Histograms by Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Histograms by Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Trends by Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Trends by Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Trends by Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Amplitude Test, Trends by Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
90
91
92
92
93
93
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TX Output Amplitude Squelched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Output Amplitude OOB Squelched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
95
98
98
98
TX Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TX Pre-emphasis Test, Minimum Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TX Pre-emphasis Test, Maximum Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TX Pre-emphasis Test, Max Setting, 1 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . . . . . 103
TX Pre-emphasis Test, Max Setting, 1 Gb/s, dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TX Pre-emphasis Test, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, % . . . . . . . . . . . . . . 104
TX Pre-emphasis Test, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB . . . . . . . . . . . . . 104
TX Pre-emphasis Test, Max Setting, 3.2 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . . . . 105
TX Pre-emphasis Test, Max Setting, 3.2 Gb/s, dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TX Pre-emphasis Test, Max Setting, 3.75 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . . . 106
TX Pre-emphasis Test, Max Setting, 3.75 Gb/s, dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, % . . . . . . . . . . 107
TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, dB . . . . . . . . . . 107
TX Pre-emphasis Test, Percentage vs. Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
TX Pre-emphasis Test, dB vs. Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
TX Pre-emphasis Test, Percent by TXPREEMPHASIS Settings at 3.2 Gb/s . . . . . . . . . 109
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TX Termination DC Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX DC Resistance Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
111
114
114
114
Chapter 3: PMA Receiver Characterization
RX Stressed Eye Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 80 MHz, 3.2 Gb/s Data Rate. . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 20 MHz 3.2 Gb/s Data Rate . . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 22 KHz, 3.2 Gb/s Data Rate . . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 80 MHz, 3.75 Gb/s Data Rate . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 20 MHz 3.75 Gb/s Data Rate . . . . . . . . .
RX Stressed Eye Composite Jitter Tolerance, 22 KHz, 3.75 Gb/s Data Rate . . . . . . . . .
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120
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RX Stressed Eye, Channel Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
RX Sinusoidal Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 100 Mb/s (Oversampled) . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 500 Mb/s (Oversampled) . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.0 Gb/s, 100 MHz REFCLK . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 62.5 MHz REFCLK . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 100 MHz REFCLK . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 125 MHz REFCLK . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 250 MHz REFCLK . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . .
RX Sinusoidal Jitter Tolerance Test Results for 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
122
125
125
125
126
126
127
127
128
128
129
129
130
130
131
131
132
RX Sinusoidal Jitter Tolerance with CDR Frequency Offset . . . . . . . . . . . . . . . . . 132
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX SJ Tolerance with CDR Frequency Offset Results, 500 Mb/s (Oversampled) . . . . .
RX SJ Tolerance with CDR Frequency Offset Results, 500 Mb/s . . . . . . . . . . . . . . . . .
RX SJ Tolerance with CDR Frequency Offset Results, 1.00 Gb/s . . . . . . . . . . . . . . . . .
RX SJ Tolerance with CDR Freq. Offset Results, 2.0 Gb/s, 100 MHz REFCLK . . . . . . .
RX SJ Tolerance with CDR Freq. Offset Results, 2.50 Gb/s, 62.5 MHz REFCLK. . . . . .
RX SJ Tolerance with CDR Freq. Offset Results, 2.50 Gb/s, 125 MHz REFCLK . . . . . .
RX SJ Tolerance with CDR Frequency Offset Results, 3.2 Gb/s . . . . . . . . . . . . . . . . . .
RX SJ Tolerance with CDR Frequency Offset Results, 3.75 Gb/s . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
132
135
135
135
136
136
137
137
138
138
139
RX CDR Frequency Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 1.25 Gb/s, 125 MHz REFCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 2.0 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 2.488 Gb/s, 155.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 2.5 Gb/s, 62.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 2.5 Gb/s, 250 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 3.125 Gb/s, 156.25 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 3.2 Gb/s, 320 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CDR Offset at 3.75 Gb/s, 187.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
139
142
142
142
143
143
144
144
145
145
146
146
RX Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 100 Mb/s Using Oversampling . . . . . . . . . . . . . . . . . . . . . . . .
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RX Input Sensitivity at 500 Mb/s Using Oversampling . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 2.0 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Input Sensitivity at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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151
151
152
152
153
153
154
154
155
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RX Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Equalization Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Equalization ATE Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Equalization Test, Stress Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer Off . . . . .
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 25% . . . .
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 37% . . . .
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 50% . . . .
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 62% . . . .
156
156
156
156
159
160
161
161
162
162
163
RX Equalization Test, Mean Sinusoidal Jitter Tolerance vs.
RX Equalizer Settings, 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RX OOB Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
RX CID Run Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 500 Mb/s, External AC. . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 1.00 Gb/s, External AC . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 2.0 Gb/s, 100 MHz REFCLK, External AC . . . . . .
RX CID Run Length Test Results at 2.488 Gb/s, Internal AC . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 2.5 Gb/s, 62.5 MHz REFCLK, External AC . . . . .
RX CID Run Length Test Results at 2.5 Gb/s, 100 MHz REFCLK, Internal AC . . . . . .
RX CID Run Length Test Results at 2.5 Gb/s, 125 MHz REFCLK, External AC . . . . . .
RX CID Run Length Test Results at 3.125 Gb/s, Internal AC . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 3.2 Gb/s, External AC . . . . . . . . . . . . . . . . . . . . .
RX CID Run Length Test Results at 3.75 Gb/s, External AC . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
167
170
170
170
171
171
172
172
173
173
174
174
175
RX Jitter Transfer Based on Data to Recovered Clock . . . . . . . . . . . . . . . . . . . . . . . 176
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Jitter Transfer to Recovered Clock Test, Trends . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Jitter Transfer to Recovered Clock Test, 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . .
RX Jitter Transfer to Recovered Clock Test, 2.0 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Jitter Transfer to Recovered Clock Test, 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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RX Termination DC Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Test Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 4: GTP_DUAL Transceiver Power Consumption
GTP_DUAL Transceiver PMA Power Consumption (ATE Measurement). . . . 187
Appendix A: General GTP_DUAL Test Settings
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Schedule of Figures
Chapter 1: Introduction
Figure 1-1: Bench Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 1-2: TX Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 1-3: RX Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 1-4: High-Volume Characterization Tester, Top View. . . . . . . . . . . . . . . . . . . . . . . 30
Figure 1-5: High-Volume Characterization Tester, Whole View . . . . . . . . . . . . . . . . . . . . 30
Chapter 2: PMA Transmitter Characterization
Figure 2-1: TX Near-End Output Eye Measurement Bench Setup . . . . . . . . . . . . . . . . . . . 38
Figure 2-2: Representative TX Output Eye at 100 Mb/s (5X Oversampling). . . . . . . . . . . 40
Figure 2-3: Representative TX Output Eye at 500 Mb/s (5X Oversampling). . . . . . . . . . . 41
Figure 2-4: Representative TX Output Eye at 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-5: Representative TX Output Eye at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-6: Representative TX Output Eye at 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 2-7: Representative TX Output Eye at 2.0 Gb/s, REFCLK 100 MHz. . . . . . . . . . . . 43
Figure 2-8: Representative TX Output Eye at 2.0 Gb/s, REFCLK 200 MHz. . . . . . . . . . . . 43
Figure 2-9: Representative TX Output Eye at 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 2-10: Representative TX Output Eye at 2.5 Gb/s, REFCLK 62.5 MHz . . . . . . . . . . 44
Figure 2-11: Representative TX Output Eye at 2.5 Gb/s, REFCLK 100 MHz. . . . . . . . . . . 45
Figure 2-12: Representative TX Output Eye at 2.5 Gb/s, REFCLK 125 MHz. . . . . . . . . . . 45
Figure 2-13: Representative TX Output Eye at 2.5 Gb/s, REFCLK 250 MHz. . . . . . . . . . . 46
Figure 2-14: Representative TX Output Eye at 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-15: Representative TX Output Eye at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-16: Representative TX Output Eye at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-17: ATE Test Setup for TX Jitter Generation Tests . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2-18: TX Jitter Generation at 500 Mb/s, Oversampled, C and I Grade . . . . . . . . . 52
Figure 2-19: TX Jitter Generation at 1.00 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . 53
Figure 2-20: TX Jitter Generation at 1.25 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-21: TX Jitter Generation at 2.00 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-22: TX Jitter Generation at 2.00 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . 56
Figure 2-23: TX Jitter Generation at 2.488 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . 57
Figure 2-24: TX Jitter Generation at 2.5 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 2-25: TX Jitter Generation at 2.5 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-26: TX Jitter Generation at 2.5 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 2-27: TX Jitter Generation at 2.5 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2-28: TX Jitter Generation at 3.125 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . 62
Figure 2-29: TX Jitter Generation at 3.2 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 2-30: TX Jitter Generation at 3.75 Gb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . . 64
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Figure 2-31: ATE Test Setup for TX REFCLK to TX Jitter Transfer Tests . . . . . . . . . . . . . 68
Figure 2-32: TX Jitter Transfer vs. Modulation Frequency at 1.0 Gb/s. . . . . . . . . . . . . . . . 69
Figure 2-33: TX Jitter Transfer vs. Modulation Frequency at 2.00 Gb/s . . . . . . . . . . . . . . 69
Figure 2-34: TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s. . . . . . . . . . . . . . . . 70
Figure 2-35: TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s . . . . . . . . . . . . . . . 70
Figure 2-36: TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s. . . . . . . . . . . . . . . . 71
Figure 2-37: TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s. . . . . . . . . . . . . . . . 71
Figure 2-38: TX Jitter Transfer vs. Modulation Frequency at 3.125 Gb/s. . . . . . . . . . . . . . 72
Figure 2-39: TX Jitter Transfer vs. Modulation Frequency at 3.2 Gb/s. . . . . . . . . . . . . . . . 72
Figure 2-40: Bench Test Setup for TX Output Rise and Fall Time Tests . . . . . . . . . . . . . . 76
Figure 2-41: TX Output Rise Time at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 2-42: TX Output Fall Time at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 2-43: TX Output Rise Time at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . 78
Figure 2-44: TX Output Fall Time at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . 78
Figure 2-45: TX Output Rise Time at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-46: TX Output Fall Time at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-47: TX Output Rise Time at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2-48: TX Output Fall Time at 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2-49: TX Output Rise Time as a Function of TXDIFFCTRL . . . . . . . . . . . . . . . . . . 81
Figure 2-50: TX Output Fall Time as a Function of TXDIFFCTRL . . . . . . . . . . . . . . . . . . . 81
Figure 2-51: TX Output Rise Time as a Function of Process . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-52: TX Output Fall Time as a Function of Process . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-53: TX Output Rise Time as a Function of Voltage . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 2-54: TX Output Fall Time as a Function of Voltage . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 2-55: TX Output Rise Time as a Function of Temperature . . . . . . . . . . . . . . . . . . . 84
Figure 2-56: TX Output Fall Time as a Function of Temperature . . . . . . . . . . . . . . . . . . . . 84
Figure 2-57: Bench Test Setup for TX Output Amplitude Tests . . . . . . . . . . . . . . . . . . . . . 88
Figure 2-58: TX Amplitude, Across All Rates, Silicon = SS . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 2-59: TX Amplitude, Across All Rates, Silicon = TT. . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 2-60: TX Amplitude, Across All Rates, Silicon = FF . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 2-61: TX Amplitude, across All Rates, VCC = VMIN . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 2-62: TX Amplitude, across All Rates, VCC = VMAX . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 2-63: TX Amplitude, across All Rates, Temp = –40°C. . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-64: TX Amplitude, Across All Rates, Temp = 0°C . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-65: TX Amplitude, Across All Rates, Temp = 100°C . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 2-66: TX Amplitude, Process Split vs. TXDIFFCTRL . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 2-67: TX Amplitude, MGTAVTTTX Supply vs. TXDIFFCTRL Trend . . . . . . . . . 92
Figure 2-68: TX Amplitude, Temperature vs. TXDIFFCTRL . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2-69: TX Amplitude, Data Rate vs. TXDIFFCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2-70: Qualitative TX Amplitude Swept across TXDIFFCTRL . . . . . . . . . . . . . . . . 94
Figure 2-71: Bench Test Setup for TX Output Amplitude (Squelched) Tests . . . . . . . . . 97
Figure 2-72: TX Output Amplitude Histogram when OOB Squelched, 2.5 Gb/s . . . . . . 98
Figure 2-73: TX Output Amplitude Squelched, 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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Figure 2-74: Bench Test Setup for TX Pre-emphasis Tests . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 2-75: Pre-emphasis Concept Showing Min and Max Voltage Levels . . . . . . . . . 101
Figure 2-76: TX Pre-emphasis, Minimum Setting, 2.5 Gb/s, 125 MHz REFCLK . . . . . . 102
Figure 2-77: TX Pre-emphasis, Maximum Setting at 2.5 Gb/s, 125 MHz REFCLK . . . . 102
Figure 2-78: TX Pre-emphasis, Max Setting, 1 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . . 103
Figure 2-79: TX Pre-emphasis, Max Setting, 1 Gb/s, dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 2-80: TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, Percentage . 104
Figure 2-81: TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB . . . . . . . . 104
Figure 2-82: TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage . . . . . . . . . . . . . . . . . . 105
Figure 2-83: TX Pre-emphasis, Max Setting, 3.2 Gb/s, dB. . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 2-84: TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage . . . . . . . . . . . . . . . . . 106
Figure 2-85: TX Pre-emphasis, Max Setting, 3.75 Gb/s, dB. . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 2-86: TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, % 107
Figure 2-87: TX Pre-emphasis Test, AVTTX Supply Trend vs. Temperature, dB . . . . . 107
Figure 2-88: TX Pre-emphasis Test, Percentage vs. Data Rate . . . . . . . . . . . . . . . . . . . . . . 108
Figure 2-89: TX Pre-emphasis Test, dB vs. Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 2-90: TX Pre-emphasis Test, by TXPREEMPHASIS Settings at 3.2 Gb/s . . . . . . 109
Figure 2-91: TX Pre-emphasis Test, dB by TXPREEMPHASIS Settings at 3.2 Gb/s . . . 109
Figure 2-92: Qualitative Measurement of the Different Pre-emphasis Settings . . . . . . 110
Figure 2-93: Bench Test Setup for TX Termination Resistance Tests . . . . . . . . . . . . . . . 112
Figure 2-94: RX and TX Termination for GTP Transceivers in LXT Devices . . . . . . . . . 113
Figure 2-95: TX Termination DC Resistance Histogram. . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 3: PMA Receiver Characterization
Figure 3-1: ATE Test Setup for RX Stressed Eye Jitter Tolerance Tests
(ATE Measurement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-2: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 80 MHz, 3.2 Gb/s . . . 118
Figure 3-3: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 20 MHz, 3.2 Gb/s . . . 118
Figure 3-4: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 22 KHz, 3.2 Gb/s . . . 119
Figure 3-5: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 80 MHz, 3.75 Gb/s . . 119
Figure 3-6: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 20 MHz, 3.75 Gb/s . . 120
Figure 3-7: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 22 KHz, 3.75 Gb/s . . 120
Figure 3-8: RX Stressed Eye, DCAj Channel Stress at 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . 121
Figure 3-9: RX Sinusoidal Jitter Tolerance Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 3-10: RX SJ Tolerance, 100 Mb/s (OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 3-11: RX SJ Tolerance, 500 Mb/s (OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 3-12: RX SJ Tolerance, 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 3-13: RX SJ Tolerance, 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 3-14: RX SJ Tolerance, 1.25 Gb/Sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 3-15: RX SJ Tolerance, 2.0 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 3-16: RX SJ Tolerance, 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 3-17: RX SJ Tolerance, 2.5 Gb/s, 62.5 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 3-18: RX SJ Tolerance, 2.5 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . 129
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Figure 3-19: RX SJ Tolerance, 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 3-20: RX SJ Tolerance, 2.5 Gb/s, 250 MHz REFCLK . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 3-21: RX SJ Tolerance, 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 3-22: RX SJ Tolerance, 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 3-23: RX SJ Tolerance, 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 3-24: RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 3-25: RX SJ Tolerance w/ CDR Frequency Offset, 500 Mb/s (OS) . . . . . . . . . . . . 135
Figure 3-26: RX SJ Tolerance w/ CDR Frequency Offset, 500 Mb/s . . . . . . . . . . . . . . . . . 135
Figure 3-27: RX SJ Tolerance w/ CDR Frequency Offset, 1.00 Gb/s . . . . . . . . . . . . . . . . . 136
Figure 3-28: RX SJ Tolerance w/ CDR Frequency Offset, 2.0 Gb/s, 100 MHz REFCLK 136
Figure 3-29: RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 62.5 MHz REFCLK 137
Figure 3-30: RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 125 MHz REFCLK 137
Figure 3-31: RX SJ Tolerance w/ CDR Frequency Offset, 3.2 Gb/s . . . . . . . . . . . . . . . . . . 138
Figure 3-32: RX SJ Tolerance w/ CDR Frequency Offset, 3.75 Gb/s . . . . . . . . . . . . . . . . . 138
Figure 3-33: ATE Test Setup for RX CDR Offset Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 3-34: RX CDR Offset at 1.25 Gb/s, C and I Grade, 125 MHz REFCLK . . . . . . . . 142
Figure 3-35: RX CDR Offset at 2.0 Gb/s, C and I Grade, 100 MHz REFCLK . . . . . . . . . 142
Figure 3-36: RX CDR Offset at 2.488 Gb/s, C and I Grade, 155.5 MHz REFCLK . . . . . . 143
Figure 3-37: RX CDR Offset at 2.5 Gb/s, C and I Grade, 62.5 MHz REFCLK . . . . . . . . . 143
Figure 3-38: RX CDR Offset at 2.5 Gb/s, C and I Grade, 125 MHz REFCLK . . . . . . . . . 144
Figure 3-39: RX CDR Offset at 2.5 Gb/s, C and I Grade, 250 MHz REFCLK . . . . . . . . . 144
Figure 3-40: RX CDR Offset at 3.125 Gb/s, C and I Grade, 156.25 MHz REFCLK . . . . . 145
Figure 3-41: RX CDR Offset at 3.2 Gb/s, C and I Grade, 320 MHz REFCLK . . . . . . . . . 145
Figure 3-42: RX CDR Offset at 3.75 Gb/s, C and I Grade, 187.5 MHz REFCLK . . . . . . . 146
Figure 3-43: ATE Test Setup for RX Input Sensitivity Tests . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 3-44: RX Input Sensitivity at 100 Mb/s, C and I Grade, Oversampled . . . . . . . . 150
Figure 3-45: RX Input Sensitivity at 500 Mb/s, C and I Grade, Oversampled . . . . . . . . 150
Figure 3-46: RX Input Sensitivity at 500 Mb/s, C and I Grade. . . . . . . . . . . . . . . . . . . . . . 151
Figure 3-47: RX Input Sensitivity at 1.00 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . 151
Figure 3-48: RX Input Sensitivity at 1.25 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . 152
Figure 3-49: RX Input Sensitivity at 2.0 Gb/s, C and I Grade, 100 MHz REFCLK . . . . 152
Figure 3-50: RX Input Sensitivity at 2.488 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . 153
Figure 3-51: RX Input Sensitivity at 2.5 Gb/s, C and I Grade, 125 MHz REFCLK . . . . 153
Figure 3-52: RX Input Sensitivity at 3.125 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . 154
Figure 3-53: RX Input Sensitivity at 3.2 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . . 154
Figure 3-54: RX Input Sensitivity at 3.75 Gb/s, C and I Grade . . . . . . . . . . . . . . . . . . . . . 155
Figure 3-55: RX Equalization Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 3-56: RX Equalization ATE Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 3-57: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = Off . . . . . . . . . . 161
Figure 3-58: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 25% . . . . . . . . . . 161
Figure 3-59: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 37% . . . . . . . . . . 162
Figure 3-60: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 50% . . . . . . . . . . 162
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Figure 3-61: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 62% . . . . . . . . . . 163
Figure 3-62: RX Equalization Test, Mean SJ Tolerance at 3.2 Gb/s vs. RX EQ Settings 163
Figure 3-63: ATE Test Setup for RX OOB Signal Detect Tests . . . . . . . . . . . . . . . . . . . . . 165
Figure 3-64: RX OOB Signal Detect Results by OOB Setting at 2.5 Gb/s . . . . . . . . . . . . 166
Figure 3-65: RX OOB Signal Detect Example Distribution, OOB . . . . . . . . . . . . . . . . . . 166
Figure 3-66: ATE Test Setup for RX CID Run Length Tests . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 3-67: RX CID Run Length at 500 Mb/s, C & I Grades . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 3-68: RX CID Run Length at 1.00 Gb/s, C & I Grades. . . . . . . . . . . . . . . . . . . . . . . 170
Figure 3-69: RX CID Run Length at 2.00 Gb/s, 100 MHz REFCLK, C & I Grades . . . . . 171
Figure 3-70: RX CID Run Length Test at 2.488 Gb/s, C & I Grades . . . . . . . . . . . . . . . . . 171
Figure 3-71: RX CID Run Length at 2.5 Gb/s, 62.5 MHz REFCLK, C & I Grades . . . . . 172
Figure 3-72: RX CID Run Length Test at 2.5 Gb/s, 100 MHz REFCLK, C & I Grades. . 172
Figure 3-73: RX CID Run Length at 2.5 Gb/s, 125 MHz REFCLK, C & I Grades . . . . . . 173
Figure 3-74: RX CID Run Length at 3.125 Gb/s, C & I Grades. . . . . . . . . . . . . . . . . . . . . . 173
Figure 3-75: RX CID Run Length at 3.2 Gb/s, C & I Grades. . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 3-76: RX CID Run Length at 3.75 Gb/s, C & I Grades. . . . . . . . . . . . . . . . . . . . . . . 174
Figure 3-77: RX Jitter Transfer to Recovered Clock Test Bench Setup . . . . . . . . . . . . . . 176
Figure 3-78: RX Jitter Transfer to Recovered Clock, Trends . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 3-79: RX Jitter Transfer to Recovered ClockK, 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . 178
Figure 3-80: RX Jitter Transfer to Recovered Clock, 2.0 Gb/s, 100 MHz REFCLK . . . . . 179
Figure 3-81: RX Jitter Transfer to Recovered Clock, 2.5 Gb/s, 125 MHz REFCLK . . . . . 179
Figure 3-82: RX Termination Resistance Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 3-83: RX Termination Resistor Calibration Macro . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 3-84: RX Termination DC Resistance Historgram. . . . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 4: GTP_DUAL Transceiver Power Consumption
Figure 4-1: GTP Single Transceiver Power Consumption at Differing Rates . . . . . . . . 188
Appendix A: General GTP_DUAL Test Settings
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Schedule of Tables
Chapter 1: Introduction
Table 1-1: Test Setup Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-2: Example PLL Settings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 1-3: Example Test Settings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 1-4: Example Test Conditions Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 1-5: Summary of Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 2: PMA Transmitter Characterization
Table 2-1: TX Near-End Output Eye PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-2: TX Near End Output Eye Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2-3: TX Near-End Output Eye Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-4: TX Jitter Generation Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 2-5: TX Jitter Generation Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-6: TX Jitter Generation Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 2-7: TX Jitter Generation Measurement at 500 Mb/s Data Rate . . . . . . . . . . . . . . . . 52
Table 2-8: TX Jitter Generation Measurement at 100 Mb/s Data Rate . . . . . . . . . . . . . . . . 53
Table 2-9: TX Jitter Generation Measurement at 1.25 Gb/s Data Rate . . . . . . . . . . . . . . . . 54
Table 2-10: TX Jitter Generation Measurement at 2.00 Gb/s Data Rate . . . . . . . . . . . . . . . 55
Table 2-11: TX Jitter Generation Measurement at 2.00 Gb/s Data Rate . . . . . . . . . . . . . . . 56
Table 2-12: TX Jitter Generation Measurement at 2.488 Gb/s Data Rate . . . . . . . . . . . . . . 57
Table 2-13: TX Jitter Generation Measurement at 2.5 Gb/s Data Rate . . . . . . . . . . . . . . . . 58
Table 2-14: TX Jitter Generation Measurement at 2.5 Gb/s Data Rate . . . . . . . . . . . . . . . . 59
Table 2-15: TX Jitter Generation Measurement at 2.5 Gb/s Data Rate . . . . . . . . . . . . . . . . 60
Table 2-16: TX Jitter Generation Measurement at 2.5 Gb/s Data Rate . . . . . . . . . . . . . . . . 61
Table 2-17: TX Jitter Generation Measurement at 3.125 Gb/s Data Rate . . . . . . . . . . . . . . 62
Table 2-18: TX Jitter Generation Measurement at 3.2 Gb/s Data Rate . . . . . . . . . . . . . . . . 63
Table 2-19: TX Jitter Generation Measurement at 3.75 Gb/s Data Rate . . . . . . . . . . . . . . . 64
Table 2-20: Summary of Results for TX Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 2-21: TX REFCLK to TX Jitter Transfer Test PLL Parameters . . . . . . . . . . . . . . . . . . 66
Table 2-22: TX REFCLK to TX Jitter Transfer Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 2-23: TX REFCLK to TX Jitter Transfer Test Conditions . . . . . . . . . . . . . . . . . . . . . . 67
Table 2-24: TX Jitter Transfer Measurement at 1.0 Gb/s Date Rate. . . . . . . . . . . . . . . . . . . 69
Table 2-25: TX Jitter Transfer Measurement at 2.0 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 69
Table 2-26: TX Jitter Transfer Measurement at 2.5 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 70
Table 2-27: TX Jitter Transfer Measurement at 2.5 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 70
Table 2-28: TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 71
Table 2-29: TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 71
Table 2-30: TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 72
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Table 2-31: TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate. . . . . . . . . . . . . . . . . . . 72
Table 2-32: TX Jitter Transfer Measurement Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 2-33: TX Output Rise and Fall Time Test PLL Parameters . . . . . . . . . . . . . . . . . . . . 74
Table 2-34: TX REFCLK to TX Jitter Transfer Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-35: TX Output Rise and Fall Time Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-36: TX Output Rise and Fall Time at 1.00 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 2-37: TX Output Rise and Fall Time at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . 78
Table 2-38: TX Output Rise and Fall Time at 3.2 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 2-39: TX Output Rise and Fall Time at 3.75 Gb/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 2-40: TX Rise Time Measurement Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-41: TX Fall Time Measurement Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-42: TX Output Amplitude Test PLL Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 2-43: TX Output Amplitude Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-44: TX Output Amplitude Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 2-45: TX Output Amplitude Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 2-46: TX Output Amplitude (Squelched) Test PLL Parameters . . . . . . . . . . . . . . . . 95
Table 2-47: TX Output Amplitude (Squelched) Test Settings . . . . . . . . . . . . . . . . . . . . . . . 96
Table 2-48: TX Output Amplitude (Squelched) Test Conditions . . . . . . . . . . . . . . . . . . . . 96
Table 2-49: TX Output Fall Time at 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . . . . 98
Table 2-50: TX Pre-emphasis Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 2-51: TX Pre-emphasis Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 2-52: TX Pre-emphasis Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 2-53: TX Pre-emphasis, Minimum Setting at 2.5 Gb/s, 125 MHz REFCLK . . . . . 102
Table 2-54: TX Pre-emphasis, Maximum Setting at 2.5 Gb/s, 125 MHz REFCLK . . . . . 102
Table 2-55: TX Pre-emphasis, Max Setting, 1 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . . . 103
Table 2-56: TX Pre-emphasis, Max Setting, 1 Gb/s, dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 2-57: TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, Percentage . . 104
Table 2-58: TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB . . . . . . . . . 104
Table 2-59: TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . 105
Table 2-60: TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage . . . . . . . . . . . . . . . . . . . 105
Table 2-61: TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage . . . . . . . . . . . . . . . . . . 106
Table 2-62: TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage . . . . . . . . . . . . . . . . . . 106
Table 2-63: TX Termination Resistance PLL Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 2-64: TX Termination Resistance Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 2-65: TX Termination Resistance Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 2-66: TX Termination DC Resistance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 3: PMA Receiver Characterization
Table 3-1: RX Stressed Eye Jitter Tolerance Test PLL Parameters. . . . . . . . . . . . . . . . . . . 116
Table 3-2: RX Stressed Eye Jitter Tolerance Test Test Settings . . . . . . . . . . . . . . . . . . . . . 116
Table 3-3: RX Stressed Eye Jitter Tolerance Test Conditions. . . . . . . . . . . . . . . . . . . . . . . 116
Table 3-4: RX Stressed Eye SJ Jitter Tolerance, 80 MHz, 3.2 Gb/s Data Rate . . . . . . . . . 118
Table 3-5: RX Stressed Eye SJ Jitter Tolerance, 20 MHz, 3.2 Gb/s Data Rate . . . . . . . . . 118
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Table 3-6: RX Stressed Eye SJ Jitter Tolerance, 22 KHz, 3.2 Gb/s Data Rate . . . . . . . . . 119
Table 3-7: RX Stressed Eye SJ Jitter Tolerance, 80 MHz, 3.75 Gb/s Data Rate . . . . . . . . 119
Table 3-8: RX Stressed Eye SJ Jitter Tolerance, 20 MHz, 3.75 Gb/s Data Rate . . . . . . . . 120
Table 3-9: RX Stressed Eye SJ Jitter Tolerance, 22 KHz, 3.75 Gb/s Data Rate . . . . . . . . 120
Table 3-10: RX Stressed Eye SJ Jitter Tolerance, Summary of Results. . . . . . . . . . . . . . . 121
Table 3-11: RX Sinusoidal Jitter Tolerance Test PLL Parameters . . . . . . . . . . . . . . . . . . . 122
Table 3-12: RX Sinusoidal Jitter Tolerance Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 3-13: RX Sinusoidal Jitter Tolerance Test Conditions . . . . . . . . . . . . . . . . . . . . . . . 123
Table 3-14: RX Sinusoidal Jitter Test, 100 Mb/s (Oversampled) . . . . . . . . . . . . . . . . . . . . 125
Table 3-15: RX Sinusoidal Jitter Test, 500 Mb/s (Oversampled) . . . . . . . . . . . . . . . . . . . . 125
Table 3-16: RX Sinusoidal Jitter Test, 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 3-17: RX Sinusoidal Jitter Test, 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 3-18: RX Sinusoidal Jitter Test, 1.25 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 3-19: RX Sinusoidal Jitter Test, 2.00 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . 127
Table 3-20: RX Sinusoidal Jitter Test, 2.488 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 3-21: RX Sinusoidal Jitter Test, 2.5 Gb/s, 62.5 MHz REFCLK . . . . . . . . . . . . . . . . . 128
Table 3-22: RX Sinusoidal Jitter Test, 2.5 Gb/s, 100 MHz REFCLK . . . . . . . . . . . . . . . . . 129
Table 3-23: RX Sinusoidal Jitter Test, 2.5 Gb/s, 125 MHz REFCLK . . . . . . . . . . . . . . . . . 129
Table 3-24: RX Sinusoidal Jitter Test, 2.5 Gb/s, 250 MHz REFCLK . . . . . . . . . . . . . . . . . 130
Table 3-25: RX Sinusoidal Jitter Test, 3.125 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 3-26: RX Sinusoidal Jitter Test, 3.2 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 3-27: RX Sinusoidal Jitter Test, 3.75 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 3-28: RX Sinusoidal Jitter Tolerance Summary Results. . . . . . . . . . . . . . . . . . . . . . 132
Table 3-29: RX Sinusoidal Jitter Tolerance - CDR Freq. Offset Test, PLL Parameters . 133
Table 3-30: RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 3-31: RX Sinusoidal Jitter Tolerance with CDR Freq. Offset
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 3-32: RX SJ Tolerance with CDR Frequency Offset, 500 Mb/s (OS) . . . . . . . . . . . 135
Table 3-33: RX SJ Tolerance with CDR Frequency Offset, 500 Mb/s (OS) . . . . . . . . . . . 135
Table 3-34: RX SJ Tolerance w/ CDR Frequency Offset, 1.00 Gb/s . . . . . . . . . . . . . . . . . . 136
Table 3-35: RX SJ Tolerance w/ CDR Frequency Offset, 2.00 Gb/s, 100 MHz REFCLK 136
Table 3-36: RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 62.5 MHz REFCLK. 137
Table 3-37: RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 125 MHz REFCLK . 137
Table 3-38: RX SJ Tolerance w/ CDR Frequency Offset, 3.2 Gb/s . . . . . . . . . . . . . . . . . . . 138
Table 3-39: RX SJ Tolerance w/ CDR Frequency Offset, 3.75 Gb/s . . . . . . . . . . . . . . . . . . 138
Table 3-40: RX SJ Tolerance with CDR Frequency Offset Summary Results. . . . . . . . . 139
Table 3-41: RX CDR Offset Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 3-42: RX CDR Offset Test Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 3-43: RX CDR Offset Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 3-44: RX CDR Offset at 1.25 Gb/s Data Rate, 125 MHz REFCLK . . . . . . . . . . . . . . 142
Table 3-45: RX CDR Offset at 2.0 Gb/s Data Rate, 100 MHz REFCLK . . . . . . . . . . . . . . . 142
Table 3-46: RX CDR Offset at 2.488 Gb/s Data Rate, 155.5 MHz REFCLK . . . . . . . . . . . 143
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Table 3-47: RX CDR Offset at 2.5 Gb/s Data Rate, 62.5 MHz REFCLK . . . . . . . . . . . . . . 143
Table 3-48: RX CDR Offset at 2.5 Gb/s Data Rate, 125 MHz REFCLK . . . . . . . . . . . . . . . 144
Table 3-49: RX CDR Offset at 2.5 Gb/s Data Rate, 250 MHz REFCLK . . . . . . . . . . . . . . . 144
Table 3-50: RX CDR Offset at 3.125 Gb/s Data Rate, 156.25 MHz REFCLK, Minus . . . 145
Table 3-51: RX CDR Offset at 3.2 Gb/s Data Rate, 320 MHz REFCLK . . . . . . . . . . . . . . . 145
Table 3-52: RX CDR Offset at 3.2 Gb/s Data Rate, 320 MHz REFCLK . . . . . . . . . . . . . . . 146
Table 3-53: RX CDR Offset Test Summary Results, Minus . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 3-54: RX CDR Offset Test Summary Results, Plus . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 3-55: RX Input Sensitivity Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 3-56: RX Input Sensitivity Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 3-57: RX Input Sensitivity Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 3-58: RX Input Sensitivity at 100 Mb/s Data Rate, Oversampled. . . . . . . . . . . . . . 150
Table 3-59: TX Generation Measurement at 500 Mb/s Date Rate, Oversampled . . . . . . 150
Table 3-60: RX Input Sensitivity at 500 Mb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 3-61: RX Input Sensitivity at 1.00 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 3-62: RX Input Sensitivity at 1.25 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 3-63: RX Input Sensitivity at 2.0 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 3-64: RX Input Sensitivity at 2.488 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 3-65: RX Input Sensitivity at 2.5 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 3-66: RX Input Sensitivity at 3.125 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 3-67: RX Input Sensitivity at 3.2 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 3-68: RX Input Sensitivity at 3.75 Gb/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 3-69: RX Input Sensitivity Summary Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 3-70: RX Equalization Test PLL Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 3-71: RX Equalization Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 3-72: RX Equalization Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 3-73: RX Equalization Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 3-74: RX Stress Test, Various Rates, Various FR-4 Trace Lengths . . . . . . . . . . . . . 160
Table 3-75: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = Off . . . . . . . . . . . 161
Table 3-76: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 25% . . . . . . . . . . . 161
Table 3-77: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 37% . . . . . . . . . . . 162
Table 3-78: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 50% . . . . . . . . . . . 162
Table 3-79: RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 62% . . . . . . . . . . . 163
Table 3-80: RX Equalization Test, Mean SJ Tolerance at 3.2 Gb/s vs. RX EQ Settings . 163
Table 3-81: RX OOB Signal Detect Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 3-82: RX OOB Signal Detect Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 3-83: RX OOB Signal Detect Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 3-84: RX OOB Signal Detect Results by OOB Setting at 2.5 Gb/s . . . . . . . . . . . . . 166
Table 3-85: RX OOB6 Signal Detect Results at 2.5 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 3-86: RX CID Run Length Test PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 3-87: RX CID Run Length Test Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 3-88: RX CID Run Length Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 3-89: RX CID Run Length Test at 500 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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Table 3-90: RX CID Run Length Test at 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 3-91: RX CID Run Length Test at at 2.00 Gb/s, 100 MHz REFCLK, C & I Grades 171
Table 3-92: RX CID Run Length Test at 2.488 Gb/s, C & I Grades . . . . . . . . . . . . . . . . . . 171
Table 3-93: RX CID Run Length Test at 2.5 Gb/s, 62.5 MHz REFCLK, C & I Grades . . 172
Table 3-94: RX CID Run Length Test at 2.5 Gb/s, 100 MHz REFCLK, C & I Grades. . . 172
Table 3-95: RX CID Run Length Test at 2.5 Gb/s, 125 MHz REFCLK, C & I Grades. . . 173
Table 3-96: RX CID Run Length Test at 3.125 Gb/s, C & I Grades . . . . . . . . . . . . . . . . . . 173
Table 3-97: RX CID Run Length Test at 3.2 Gb/s, C & I Grades . . . . . . . . . . . . . . . . . . . . 174
Table 3-98: RX CID Run Length Test at 3.75 Gb/s, C & I Grades . . . . . . . . . . . . . . . . . . . 174
Table 3-99: RX CID Run Length Test, Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 3-100: RX Jitter Transfer to Recovered Clock Test PLL Settings . . . . . . . . . . . . . . 177
Table 3-101: RX Jitter Transfer to Recovered Clock Test Settings . . . . . . . . . . . . . . . . . . 177
Table 3-102: RX Jitter Transfer to Recovered Clock Test Conditions. . . . . . . . . . . . . . . . 177
Table 3-103: RX Jitter Transfer to Recovered Clock, 1.00 Gb/s . . . . . . . . . . . . . . . . . . . . . 178
Table 3-104: RX Jitter Transfer to Recovered Clock, 2.0 Gb/s, 100 MHz REFCLK . . . . . 179
Table 3-105: RX Jitter Transfer to Recovered Clock, 2.5 Gb/s, 125 MHZ REFCLK . . . . 179
Table 3-106: RX Jitter Transfer to Recovered Clock Test, Summary . . . . . . . . . . . . . . . . 180
Table 3-107: RX Transfer Jitter Test PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 3-108: RX Transfer Jitter Test Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 3-109: RX Termination Resistance Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 3-110: RX Termination DC Resistance Measurement. . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 4: GTP_DUAL Transceiver Power Consumption
Table 4-1: Average and Deviation Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 4-2: Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Appendix A: General GTP_DUAL Test Settings
Table A-1: Relevant GTP_DUAL Port Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table A-2: Relevant GTP_DUAL Attribute Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Preface
About This Guide
This characterization report provides FPGA characterization results for Virtex®-5 LXT and
SXT RocketIO™ GTP transceivers across specified process, voltage, and temperature
(PVT) conditions.
Guide Contents
This manual contains the following chapters:
•
Chapter 1, “Introduction,” introduces the Virtex-5 LXT and SXT platforms and
describes: the tests conducted, test methodology, test setup, and test conditions.
•
Chapter 2, “PMA Transmitter Characterization,” describes the characterization
process and results for various Physical Media Attachment (PMA) transmitter tests.
•
Chapter 3, “PMA Receiver Characterization,” describes the characterization process
and results for various PMA receiver tests.
•
Chapter 4, “GTP_DUAL Transceiver Power Consumption,” describes the power
consumption of the PMA portion of the GTP.
•
Appendix A, “General GTP_DUAL Test Settings,” describes the GTP settings applied
in every test, except where noted within the individual tests.
References
The following documents provide useful supplementary material. All can be accessed on
the Xilinx website. From the Home page, select Documentation → By Device → Virtex-5.
•
Virtex-5 RocketIO GTP Transceiver User Guide
•
Virtex-5 FPGA User Guide
•
Virtex-5 Data Sheet: DC and Switching Characteristics
•
Virtex-5 Gigabit Ethernet Serial Protocol Standard Characterization Test Report
•
Virtex-5 PCI Express Protocol Standard Characterization Test Report
•
Virtex-5 OC-48 Protocol Standard Characterization Test Report
•
Virtex-5 XAUI Protocol Standard Characterization Test Report
•
Virtex-5 CPRI Protocol Standard Characterization Test Report
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Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Definition of Terms
ATE
Automated Test Equipment
BER
Bit Error Ratio
BERT
Bit Error Ratio Tester
Channel
The high-speed serial signal path, which can include printed circuit board (PCB) material,
connectors, cabling, and so on.
CDR
Clock and Data Recovery
DCD
Duty Cycle Distortion
DDJ
Data Dependent Jitter
DJ
Deterministic Jitter – attributable to specific data patterns or events.
DRP
Dynamic Reconfiguration Port. Used to dynamically modify PMA settings such as data rate or
equalization.
DUT
Device Under Test
FPGA
Field Programmable Gate Array
FR-4
Generic name for printed circuit board dielectric material
Gb/s
Gigabits per Second
I/O
Input/Output
ISI
Inter Symbol Interference
PJ
Periodic Jitter
PLL
Phase-Locked Loop
PMA
Physical Media Attachment – also known as the SerDes portion of the transceiver.
PCS
Physical Coding Sublayer – digital logic that supports the 8B/10B encoding/decoding.
PVT
Process, Voltage, and Temperature
RJ
Random Jitter – attributable to random noise. Random jitter is Gaussian in nature.
RocketIO™
Xilinx trademark for the high-speed serial I/O transceivers
RX
Receiver
SerDes
Serializer/Deserializer. A complete transceiver with RX, TX, CDR, and PLL blocks.
TJ
Total Jitter
TX
Transmitter
VCO
Voltage-Controlled Oscillator
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Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold
Literal commands that you enter
in a syntactical statement
ngdbuild design_name
Commands that you select from
a menu
File → Open
Keyboard shortcuts
Ctrl+C
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [option_name]
design_name
A list of items from which you
must choose one or more
lowpwr ={on|off}
Separates items in a list of
choices
lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . .
Repetitive material that has
been omitted
allow block block_name loc1
loc2 ... locn;
Helvetica bold
Italic font
Square brackets
Braces
[ ]
{ }
Vertical bar
|
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Online Document
The following conventions are used in this document:
Convention
24
Meaning or Use
Example
Blue text
Cross-reference link to a location
in the current document
Blue, underlined text
Hyperlink to a website (URL)
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Go to http://www.xilinx.com
for the latest speed files.
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Chapter 1
Introduction
Virtex-5 LXT and SXT FPGA Platforms Overview
Customers should see Virtex-5 Data Sheet: DC and Switching Characteristics (DS202) and
Virtex-5 FPGA User Guide (UG190) for complete information on the Virtex®-5 LXT and SXT
FPGA platforms.
RocketIO GTP Transceiver Overview
The Virtex-5 RocketIO GTP Transceiver User Guide (UG196) provides an excellent
introduction to Virtex-5 RocketIO™ GTP transceivers. Refer to this document for
additional GTP transceiver information.
Scope of Characterization
This document serves as a general characterization report for Virtex-5 LXT and SXT
devices. It is not designed to demonstrate compliance to specific standards. Xilinx
produces standards-based characterization reports that detail specific setup and
measurement requirements per those standards. See the “References” section for
additional details. Also, check online at http://www.xilinx.com for the latest standardsbased reports.
This report is designed to document the behavior characteristics of the physical media
attachment (PMA) and not that of the physical coding sublayer (PCS).
The intention of this report is to provide a consistent framework for evaluating the various
aspects of the PMA transmitter and receiver. The same setups are used, with the same
settings, wherever possible. Some tests require differing setups due to their nature.
Importantly, the test setups used for this report are different than those of the specific
standards-based characterization reports. Results can differ between these reports due to
the nature of the test setup and/or test conditions used in the creation of each report. Use
the report appropriate for the intended use.
Test Setup and Methodology
Characterization of a complex analog component requires a variety of test setups in order
to cover all of the interested parameters. Where possible, Automated Test Equipment
(ATE) was used to perform measurements. In some instances, bench measurements are
required to explore a particular parameter. Table 1-1 identifies how each test was
conducted, and cross references a picture of those setups. Three different bench setups and
one ATE setup are used.
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Chapter 1: Introduction
Table 1-1:
Test Setup Reference
Test Conducted
Test Setup Reference Figure
Test Style
TX Near-End Output Eye
Figure 1-1
Bench
TX Jitter Generation
Figure 1-4, Figure 1-5
ATE
TX REFCLK to TX Jitter Transfer
Figure 1-4, Figure 1-5
ATE
TX Output Rise and Fall Time
Figure 1-2
TX Bench
TX Output Amplitude
Figure 1-2
TX Bench
TX Output Amplitude Squelched
Figure 1-2
TX Bench
TX Pre-Emphasis
Figure 1-2
TX Bench
TX Termination DC Resistance
Figure 1-2
TX Bench
RX Stressed Eye Jitter Tolerance
Figure 1-4, Figure 1-5
ATE
RX Sinusoidal Jitter Tolerance
Figure 1-4, Figure 1-5
ATE
RX Sinusoidal Jitter Tolerance with
CDR Frequency Offset
Figure 1-4, Figure 1-5
ATE
RX CDR Frequency Tolerance
Figure 1-4, Figure 1-5
ATE
RX Input Sensitivity
Figure 1-4, Figure 1-5
ATE
RX Equalization
Figure 1-1, Figure 1-4, Figure 1-5
RX OOB Signal Detect
Figure 1-4, Figure 1-5
ATE
RX CID Run Length
Figure 1-4, Figure 1-5
ATE
RX Jitter Transfer Based on Data to
Recovered Clock
Figure 1-3
RX Termination DC Resistance
Figure 1-1, Figure 1-4, Figure 1-5
Bench and ATE
RX Bench
Bench and ATE
Figure 1-1 through Figure 1-5 show the test setups that were used for this characterization
document.
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Test Setup and Methodology
Characterization Test Setup
Figure 1-1 shows a picture of the test setup used to capture the TX near-end output eye and
measure the RX and TX resistance. This setup consisted of a high-precision clock source, a
Virtex-5 ML523 characterization platform, a temperature forcing unit (illustrated in
Figure 1-3), a BERT generator, high-precision power supplies, and a high-speed Agilent
Infinium DCA (86100A). Additionally, a high-precision digital voltmeter was used for DC
resistance measurements. Not all instruments shown were used for all tests.
Connection to the Device Under Test (DUT) was made through a high speed, low profile,
zero insertion force socket. The device was configured for these tests via the JTAG port
using Xilinx ChipScope™ Pro SerialIO Toolkit software.
RPT056_c1_01_040507
Figure 1-1:
Bench Setup
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Chapter 1: Introduction
Figure 1-2 shows a picture of the TX bench setup used to capture PMA transmitter
characteristics. It consists of a Virtex-5 ML523 characterization platform, a programmable
temperature forcing unit, high precision programmable power supplies, an Agilent
Infinium DCA 86100A, a programmable HP 8133A Signal Generator, and a programmable
HP 3499B Switch Control System.
Connection to the DUT was made through a high speed, low profile, zero insertion force
socket. The device was configured for these tests via the JTAG port using Xilinx ChipScope
Pro SerialIO Toolkit software.
The TX bench setup was controlled by a PC running a PERL program with GPIB interfaces
to control the power supplies, clocks, data generation, and data gathering facilities..
RPT056_c1_02_040507
Figure 1-2:
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TX Bench Setup
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Test Setup and Methodology
Figure 1-3 shows a picture of the RX bench setup used to capture some of the PMA receiver
characteristics. It consists of an ML523, a programmable temperature forcing unit, high
precision programmable power supplies, an Agilent Infinium DCA 86100A, a
programmable HP 8648C Signal Generator, an Agilent N4901B SerBERT, and a
programmable HP 3499B Switch Control System.
Connection to the DUT was made through a high speed, low profile, zero insertion force
socket. The device was configured for these tests via the JTAG port using Xilinx ChipScope
Pro SerialIO Toolkit software.
The RX bench setup was controlled by a PC running a PERL program with GPIB interfaces
to control the power supplies, clocks, data generation, and data gathering facilities.
RPT056_c1_03_040507
Figure 1-3:
RX Bench Setup
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Chapter 1: Introduction
Figure 1-4 and Figure 1-5 show the Agilent ParBERT ATE equipment setup. This
equipment includes fully programmable multi-channel BERT, clock sources, power
supplies, and measurement equipment, which can be automated to sequence through
various test setups and conditions, including reconfiguring the FPGA. The automated
temperature-forcing equipment is not shown.
RPT056_c1_04_040507
Figure 1-4:
High-Volume Characterization Tester, Top View
RPT056_c1_05_040507
Figure 1-5:
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High-Volume Characterization Tester, Whole View
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Test Setup and Methodology
A DUT test fixture was used to hold an FPGA under test. An FPGA was placed in the test
fixture, and the temperature forcing equipment was placed over the top of the FPGA. The
ATE equipment sequences through the specified tests across voltage and temperature.
FPGAs from various process corners are used to capture the process-related variances in
the GTP PMA transmitter and receiver.
The Automated Test Equipment, or ATE, is a state-of-the-art test system designed
specifically for PMA parametric testing. It is based on the Agilent 81250 13.5 Gb/s
ParBERT and provides a total of twelve generator and analyzer channels operating in
parallel.
The ParBERT generators and analyzers are clocked from separate very low-jitter signal
generators, permitting both synchronous operation (TX and RX operating at the same data
rate) and asynchronous operation (TX and RX operating at different frequencies with a
data rate offset).
An arbitrary waveform generator was used to provide a modulation source for both
Sinusoidal Jitter Tolerance and Jitter Transfer testing. The arbitrary waveform generator
can be programmed for up to 80 MHz modulation frequency.
Two pairs of differential low-jitter reference clocks (GTP REFCLK) are provided from a
3.2 Gb/s data generator to clock the device under test. The data rate of the 3.2 Gb/s data
generator was adjusted to generate the desired clock frequency. The 3.2 Gb/s data
generator can be modulated with an arbitrary waveform generator for Jitter Transfer
testing.
The ATE system was programmed using the Agilent VEE GPIB programming language.
Use of a programming language offers many benefits including repeatable and efficient
operation.
A custom test fixture was designed to interface the device’s high-speed I/O channels and
REFCLK to the ParBERT, provide power, and configure the device. Device configuration
was via JTAG. Test vectors can also be applied to the device through a 96-channel I/O
interface.
The basic design, used for all the test cases, connects the device RX to the ParBERT
generator and the device TX to the ParBERT analyzer. Output from the PCS RX port was
connected to the PCS TX port using FPGA on-chip fabric routing (fabric loopback).
Configuration files (.BIT) used for the ATE were developed using Xilinx ISE® Design Tools.
A standard configuration was used in all test cases. The DRP (Dynamic Re-Configuration
Port) was used to change the attributes of the device for specific tests.
The DUT incorporates external AC coupling of 100 nF on the RX pins. For most tests, the
internal AC coupling was bypassed, except where noted otherwise in the test results.
Characterization Test Methodology
Each test consisted of a bench test and/or ATE tests. Each test set was run across process,
voltage, and temperature (PVT). Silicon process corners, along with typical silicon, were
used to provide data on the effects of process to each test. Similarly, the power supplies
were varied from their nominal voltages by the percent of variance specified in the data
sheet, typically ±5%. Devices under test were also temperature-forced at –40°C, 0°C, and
100°C, ambient.
Each test looks for a specific characteristic of interest. The tests are designed, where
possible, to test only the elements that can affect that specific test. Trend lines are provided,
where appropriate, to illustrate the effect that a parameter has on the specific characteristic.
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Chapter 1: Introduction
This document is organized first by PMA transmitter characteristics, then by PMA receiver
characteristics. Under these broad categories, specific tests are listed as subsections. Each
subsection is broken down into four items, which repeat for each test:
•
Test Description
•
Test Setup
•
•
♦
Table: PLL Settings
♦
Table: Test Settings
♦
Table: Test Conditions
Test Results
♦
Figure: Graphical results by data rate a
♦
Figure: Graphical results by data rate b
♦
Figure: Graphical results by data rate [. . .]
Conclusion
Test Description
Test Description provides a high-level explanation of what the test does.
Test Setup Sections
Test Setup provides details of how the test was conducted, including all relevant GTP
transceiver settings that were changed relative to those contained in Appendix A,
“General GTP_DUAL Test Settings.”
A PLL settings table is provided, which documents the per-rate settings for relevant PLL
settings. Table 1-2 illustrates an example of one of these PLL settings tables.
Table 1-2:
Example PLL Settings Table
Data Rate
PLL Freq REFCLK
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(GHz)
Freq (MHz)
and DIV
Post Divider (1)
Oversample
100 Mb/s (OS) (2)
1.00
100
1
2 * 5 = 10
4
5
500 Mb/s (OS) (2)
1.25
125
1
2 * 5 = 10
1
5
500 Mb/s
1.00
100
1
2 * 5 = 10
4
1
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
1.25 Gb/s
1.25
125
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
250
1
1*5=5
1
1
1.5625
156.25
1
2 * 5 = 10
1
1
1.60
320
1
1*5=5
1
1
3.125 Gb/s
3.2 Gb/s
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
2. (OS) means oversampled mode enabled.
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Test Setup and Methodology
Another table is provided to show the settings of the FPGA that differ from the standard
settings contained in Appendix A, “General GTP_DUAL Test Settings.” Table 1-3 shows an
example settings table. Only the relevant parameters that differ from the standard settings
are shown.
Table 1-3:
Example Test Settings Table
GTP_Dual Port Settings
PORT
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_Dual Attribute Settings
ATTRIBUTE
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 & 500 Mb/s (OS)
TRUE
A table is also provided which details the relevant conditions of the particular test.
Table 1-4 illustrates an example of one of these PLL settings tables. Definitions of some of
the test parameters used in this table are as follows:
•
•
•
Loopback Mode – Refer to UG196, Virtex-5 RocketIO GTP Transceiver User Guide
Pattern – Pattern(s) that were used for the particular test.
Silicon Corner Used
SS – Slow PMOS, Slow NMOS
FS – Fast PMOS, Slow NMOS
SF – Slow PMOS, Fast NMOS
TT – Typical PMOS, Typical NMOS
FF – Fast PMOS, Fast NMOS
•
•
•
GTP_DUAL Location Used – Locations of GTP_DUAL transceivers that were tested
Junction Temperature – Junction or case temperature(s) at which the tests were run
Test Board – Test Platform used:
ML523 – Virtex-5 ML523 Characterization Platform
Virtex-5 LXT FF1136 Test Fixture
•
•
FR-4 Length – Length of GTP transceiver traces on specified test board
REFCLK and PLL Rates – See the table referred to for rate-specific PLL settings
Table 1-4:
Example Test Conditions Table
Test Parameter
Loopback Mode
Test Value
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, FS, SF, TT, FF
GTP_DUAL Location Used
X0Y1
Junction Temperature
100°C
Power Supplies
–5%
Test Board
ML52x, Virtex-5 Test Fixture
Transmitter Termination Style
AC Coupled, 50Ω to Ground
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 2-1)
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Chapter 1: Introduction
Finally, a diagram is provided for each test to illustrate the instrumentation used during
the test.
Conclusion Sections
The conclusion provides a summary of the results where a summary is warranted.
Characterization Test Conditions
The data collected for this report was collected under specific test conditions. These
conditions are generally across Process, Voltage and Temperature, as well as various data
rates and PLL settings. The test conditions used for each test are documented within the
Test Setup section of each test.
This document serves as a general characterization report for Virtex-5 LXT devices. It is not
designed to demonstrate compliance to specific standards. Xilinx produces
standards-based characterization reports that detail specific setup and measurement
requirements as per those standards. See the “References” section in the Preface for
additional information.
Importantly, the test setups used for this report are different than those used in the specific
standards-based characterization reports. Results can differ between these reports due to
the nature of the test setup and/or test conditions used in the creation of each report. Use
the report appropriate for the intended use.
See Table 1-4 for an example of test conditions used.
Characterization Devices
Xilinx used the Virtex-5 XC5VLX50T FPGA in a FF1136 package as its primary DUT.
Devices were selected from fast process lots, slow process lots, and typical process lots.
Each of these devices was tested at the specified temperature and voltage. Any test escapes
that were found during characterization testing were retested for functional behavior
using the production tester. The characterization test results were removed if they did not
pass the production tests.
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Summary of Characterization Results
Summary of Characterization Results
Table 1-5 provides a quick reference to the characterization test results.
Table 1-5:
Summary of Characterization Results
Test Conducted
TX Near-End Output Eye
Test Style
Bench
TX Jitter Generation
ATE
TX REFCLK to TX Jitter Transfer
ATE
TX Output Rise and Fall Time
TX Bench
TX Output Amplitude
TX Bench
TX Output Amplitude Squelched
TX Bench
TX Pre-Emphasis
TX Bench
TX Termination DC Resistance
TX Bench
RX Stressed Eye Jitter Tolerance
ATE
RX Sinusoidal Jitter Tolerance
ATE
RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
ATE
RX CDR Frequency Tolerance
ATE
RX Input Sensitivity
ATE
RX Equalization
Bench and ATE
RX OOB Signal Detect
ATE
RX CID Run Length
ATE
RX Jitter Transfer Based on Data to Recovered Clock
RX Bench
RX Termination DC Resistance
RX Bench
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Chapter 1: Introduction
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Chapter 2
PMA Transmitter Characterization
TX Near-End Output Eye
Test Description
Eye diagrams are commonly used to evaluate the quality of signals at different points
along a serial link. The TX near-end eye diagrams that follow are representative samples
for different rates.
Test Setup
TX near-end output eye diagram data was collected using a differentially connected
Agilent 86100A DCA for bench measurements. Figure 2-1 illustrates the equipment used
for this test.
The TX near-end eye diagrams are shown centered on 1.5 bit times per screen. The tests
were run using a PRBS31 pattern for a capture duration of approximately 300 seconds
using SS corner silicon, power supplies set at –5%, and case temperature of 100°C. These
are representative diagrams only, and not intended to quantify any particular bit-error
ratio (BER).
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Chapter 2: PMA Transmitter Characterization
71501C Jitter Analysis System
Black denotes front panel connection.
Blue denotes back panel connection.
3325B Modulator
Main Signal
Sync Out
10 MHz Ref In
IEEE
83752A Sweeper
NC 6108 Noise
Generator
FM Input
IEEE
10 MHz Ref In
70820A MTA
Chan1
Sync In
IEEE
10 MHz Ref Out
Divide by 20
Trigger Out
156.25 MHz
Noise Out
RF Output
Chan2
81134A
Pulse
Generator
Channel 11 Clk
Out 3.125 Gb/s
Power Divider
10 MHz Ref In
86130A Bitalyzer
Pattern Generator
Clk Out
Clk In
IEEE
Data P Data N
Error Detector
Clk In
Data In
CLK/REF Input
ML523
RXP
81130A Pattern Generator
Trigger Out
Clk P Clk N
RXN
86100A Infinium
DCA Scope
20
TXN
Channel 1
TXP
Channel 2
20
MGTREFCLKN
MGTREFCLKP
External Trigger
RPT056_02_01_060107
Figure 2-1:
TX Near-End Output Eye Measurement Bench Setup
Two pairs of REFCLKs were used to clock the six GTP_DUALs in two groups of three
GTP_DUALs. The REFCLKs were sourced from an Agilent 81130A data generator using a
clock pattern. This particular test used only one GTP transceiver of the GTP_DUAL located
at X0Y0. Table 2-1 shows the appropriate REFCLK frequency, and PLL ratio to create a
proper PLL frequency for each of the tested data rates.
Table 2-1:
TX Near-End Output Eye PLL Settings
Data Rate
PLL Freq
(GHz)
100 Mb/s (OS)
1.00
100
1
500 Mb/s (OS)
1.25
125
500 Mb/s
1.00
1.00 Gb/s
1.00
38
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
Post
Divider(1)
Oversample
2 * 5 = 10
4
5
1
2 * 5 = 10
1
5
100
1
2 * 5 = 10
4
1
100
1
2 * 5 = 10
2
1
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Table 2-1:
TX Near-End Output Eye
TX Near-End Output Eye PLL Settings (Continued)
PLL_DIVSEL_FB
REFCLK Freq
PLL_DIVSEL_REF
and DIV
(MHz)
Post
Divider(1)
Oversample
2 * 5 = 10
2
1
1
2 * 5 = 10
1
1
200
1
2 * 5 = 10
2
1
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
2.5 Gb/s
1.25
125
1
2 * 5 = 10
1
1
2.5 Gb/s
1.25
250
1
1*5=5
1
1
3.125 Gb/s
1.5625
156.25
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
Data Rate
PLL Freq
(GHz)
1.25 Gb/s
1.25
125
1
2.0 Gb/s
1.00
100
2.0 Gb/s
2.00
2.488 Gb/s
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE® software by Xilinx was used to configure the FPGA and
set the parameters of the GTP transceivers. Each GTP transceiver was set up with the
settings in Table 2-2. Only those settings that differ from Appendix A, “General
GTP_DUAL Test Settings” or were otherwise important for this specific test are listed.
Table 2-2:
TX Near End Output Eye Test Settings
GTP_DUAL Port Settings
Port
INTDATAWIDTH
Rate Affected
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
The test fixture uses a high-speed zero insertion force (ZIF) socket to connect the device under
test (DUT) to the test equipment. Figure 2-1 shows a picture of the test testup.
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Chapter 2: PMA Transmitter Characterization
Various conditions were used to characterize the GTP transceivers. Conditions relevant to
this test are contained in Table 2-3.
Table 2-3:
TX Near-End Output Eye Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
X0Y1
Case Temperature
100°C
Power Supplies
–5%
Test Board
ML523
Transmitter Termination Style
AC Coupled, 50Ω to Ground into the DCA
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 2-1)
Results
Figure 2-2 through Figure 2-15, captured near-end eye diagrams, are representative
samples based upon the test conditions described in Table 2-3.
TX Near-End Eye Diagram at 100 Mb/s, Oversampled
RPT056_c2_02_040607
Figure 2-2: Representative TX Output Eye at 100 Mb/s (5X Oversampling)
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TX Near-End Output Eye
TX Near-End Eye Diagram at 500 Mb/s, Oversampled
RPT056_c2_03_040607
Figure 2-3:
Representative TX Output Eye at 500 Mb/s (5X Oversampling)
TX Near-End Eye Diagram at 500 Mb/s
RPT056_c2_04_041107
Figure 2-4: Representative TX Output Eye at 500 Mb/s
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Chapter 2: PMA Transmitter Characterization
TX Near-End Eye Diagram at 1.00 Gb/s
RPT056_c2_05_053007
Figure 2-5:
Representative TX Output Eye at 1.00 Gb/s
TX Near-End Eye Diagram at 1.25 Gb/s
RPT056_c2_06_040607
Figure 2-6:
42
Representative TX Output Eye at 1.25 Gb/s
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TX Near-End Output Eye
TX Near-End Eye Diagram at 2.0 Gb/s, 100 MHz REFCLK
RPT056_c2_12_032907
Figure 2-7:
Representative TX Output Eye at 2.0 Gb/s, REFCLK 100 MHz
TX Near-End Eye Diagram at 2.0 Gb/s, 200 MHz REFCLK
RPT056_c2_13_032907
Figure 2-8:
Representative TX Output Eye at 2.0 Gb/s, REFCLK 200 MHz
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Chapter 2: PMA Transmitter Characterization
TX Near-End Eye Diagram at 2.488 Gb/s
RPT056_c2_09_040607
Figure 2-9:
Representative TX Output Eye at 2.488 Gb/s
TX Near-End Eye Diagram at 2.5 Gb/s, 62.5 MHz REFCLK
RPT056_c2_10_040607
Figure 2-10:
44
Representative TX Output Eye at 2.5 Gb/s, REFCLK 62.5 MHz
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TX Near-End Output Eye
TX Near-End Eye Diagram at 2.5 Gb/s, 100 MHz REFCLK
RPT056_c2_11_040607
Figure 2-11:
Representative TX Output Eye at 2.5 Gb/s, REFCLK 100 MHz
TX Near-End Eye Diagram at 2.5 Gb/s, 125 MHz REFCLK
RPT056_c2_12_040607
Figure 2-12:
Representative TX Output Eye at 2.5 Gb/s, REFCLK 125 MHz
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Chapter 2: PMA Transmitter Characterization
TX Near-End Eye Diagram at 2.5 Gb/s, 250 MHz REFCLK
RPT056_c2_13_041007
Figure 2-13:
Representative TX Output Eye at 2.5 Gb/s, REFCLK 250 MHz
TX Near-End Eye Diagram at 3.125 Gb/s
RPT056_c2_19_032907
Figure 2-14:
46
Representative TX Output Eye at 3.125 Gb/s
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TX Near-End Output Eye
TX Near-End Eye Diagram at 3.2 Gb/s
RPT056_c2_15_040607
Figure 2-15:
Representative TX Output Eye at 3.2 Gb/s
TX Near-End Eye Diagram at 3.75 Gb/s
RPT056_c2_102_040308
Figure 2-16:
Representative TX Output Eye at 3.75 Gb/s
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Chapter 2: PMA Transmitter Characterization
Conclusion
The TX near-end output eye tests display representative eyes for the rates contained in
Table 2-1. The near-end output eye diagrams in Figure 2-2 through Figure 2-15 illustrate
GTP transceiver performance for the conditions listed in Table 2-2 and Table 2-3.
TX Jitter Generation
Test Description
Eye width measurements of the transmitter output were performed by the Bath Tub Curve
(BTC) method, whereas the random jitter component was extrapolated to 1E–12 BER to
measure the transmitter output's total jitter (TJ).
The TX jitter generation test measures the TJ and estimates random jitter (RJ) at the TX
outputs of the device using a low-jitter REFCLK source. For each datapoint, deterministic
jitter (DJ) was calculated as follows:
DJ = TJ – RJ
The reported jitter is broadband, with no filtering. TX jitter was measured with BTC
method, using 10E9 bits of data. RJ was extrapolated from the measurements to BER = 1E–
12. Note that the data reported in the histogram tables contains local minimum and
maximum data across all devices tested. As such, the reported minimum and maximum
data columns may not appear to obey the above formula, but the data is correct.
Table 2-20 shows a summary of the results for various data rates.
Test Setup
TX jitter data was collected using ATE. Figure 2-17 illustrates the equipment used for this
test.
Agilent ParBERT 13.5 Gb/s ATE was used to measure TX jitter on all 12 GTP transceivers
simultaneously. A ParBERT analyzer was used to measure the BER of each of the GTP TX
outputs. Temperature control was achieved through forced-air cooling/heating using a
programmable Thermionics unit. Twelve GTP transceiver channels can be characterized
simultaneously in a single pass.
No filtering was used on the ParBERT, so the results include the entire noise spectrum.
The device was configured using JTAG. Power was supplied from eight programmable
power supplies through connectors on the side of the fixture.
High-speed connections from the test fixture to the ParBERT were made through SMP and
SMA coax connectors. Blind-mate connectors were used to permit quick removal of the test
fixture. A low-profile, high-speed socket was used to collect the data.
Two pairs of REFCLKs were used to clock the six GTP_DUAL tiles in two groups of three
GTP_DUAL tiles. The REFCLKs were sourced from a 3.2 Gb/s data generator using a
clock pattern.
Table 2-4 shows the appropriate REFCLK frequency and PLL multiplier to create a proper
PLL frequency for each of the tested data rates.
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Table 2-4:
TX Jitter Generation
TX Jitter Generation Test PLL Parameters
Data Rate
PLL Freq REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(GHz)
(MHz)
and DIV
Post
Divider(1)
Oversample
500 Mb/s (OS)
1.25
125
1
2 * 5 = 10
1
5
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
1.25 Gb/s
1.25
125
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.0 Gb/s
2.00
200
1
2 * 5 = 10
2
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
2.5 Gb/s
1.25
125
1
2 * 5 = 10
1
1
2.5 Gb/s
1.25
250
1
1*5=5
1
1
3.125 Gb/s
1.5625
156.25
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Typical, slow, and fast corner material was characterized using the ATE system over
voltage and temperature corners. All twelve GTP transceivers on each unit were tested.
The configuration designs use fabric loopback in single-byte mode, with both TXUSRCLK
and RXUSRCLK clocked from TXOUTCLK. The configuration provides connections to
GTP_RESET, CDR_RESET, and the DRP interface. For all test cases, the RX was configured
for termination to GND, with RX front end using internal AC coupling.
Serial data to the RX was provided by the Agilent ParBERT Pattern Generator. This was
converted to 8-bit or 10-bit data at the PMA deserializer and passed through the PCS. The
RX parallel data port was connected to the TX parallel data port in the FPGA fabric.
The 8-bit or 10-bit parallel data was then sent through the TX PCS and converted back to
serial data at the TX PMA. The TX serial data was connected to the ParBERT Data
Analyzer.
Figure 2-17 shows a diagram of the test setup.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceivers was set up with the settings in
Table 2-5. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
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Chapter 2: PMA Transmitter Characterization
Table 2-5:
TX Jitter Generation Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-6.
Table 2-6:
TX Jitter Generation Test Conditions
Test Parameter
Loopback Mode
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 locations
Ambient Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
50
Test Value
Various (see Table 2-4)
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TX Jitter Generation
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c2_16_041907
Figure 2-17:
ATE Test Setup for TX Jitter Generation Tests
Results
Figure 2-18 through Figure 2-29 and Table 2-7 through Table 2-18 present the TX jitter
generation test results. Table 2-20 provides a summary chart of the results across various
data rates.
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 500 Mb/s Using Oversampling
Virtex-5 GTP TX Jitter, 0.500 Gb/s, REFCLK = 100 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
450
400
Number of Data Points
350
300
250
200
150
100
50
TX Total Jitter (UI)
Figure 2-18:
0.50
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.24
0.26
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
RPT056_c2_22_051807
TX Jitter Generation at 500 Mb/s, Oversampled, C and I Grade
Note: Histogram was generated from 630 Mb/s data (minimum instrument speed).
TX jitter as adjusted to 500 Mb/s using (630 Mb/s Jitter * 500 / 630).
Table 2-7:
TX Jitter Generation Measurement at 500 Mb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
0.052
0.072
0.052
0.006
UI
RJ, Random Jitter(1)
–
–
–
–
UI
DJ, Deterministic Jitter(1)
–
–
–
–
UI
TJ, Total Jitter
Notes:
1. There are insufficient data points to establish RJ and DJ for this graph.
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TX Jitter Generation
TX Jitter Generation at 1.00 Gb/s
Virtex-5 GTP TX Jitter, 1.00 Gb/s, REFCLK = 100 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
250
Number of Data Points
200
150
100
50
TX Total Jitter (UI)
Figure 2-19:
Table 2-8:
0.50
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.24
0.26
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
RPT056_c2_18_051807
TX Jitter Generation at 1.00 Gb/s, C and I Grade
TX Jitter Generation Measurement at 100 Mb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.084
0.237
0.124
0.021
UI
RJ, Random Jitter
0.048
0.119
0.072
0.010
UI
DJ, Deterministic Jitter
0.005
0.187
0.053
0.023
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 1.25 Gb/s
Virtex-5 GTP TX Jitter, 1.25 Gb/s, REFCLK = 125 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
450
400
Number of Data Points
350
300
250
200
150
100
50
TX Total Jitter (UI)
Figure 2-20:
Table 2-9:
0.50
0.48
0.46
0.44
0.42
0.40
0.38
RPT056_c2_19_051807
TX Jitter Generation at 1.25 Gb/s, C and I Grade
TX Jitter Generation Measurement at 1.25 Gb/s Data Rate
Parameter
54
0.36
0.34
0.32
0.30
0.28
0.24
0.26
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.084
0.186
0.123
0.015
UI
RJ, Random Jitter
0.051
0.138
0.077
0.011
UI
DJ, Deterministic Jitter
0.003
0.103
0.046
0.015
UI
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TX Jitter Generation
TX Jitter Generation at 2.0 Gb/s Using 100 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.00 Gb/s, REFCLK = 100 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
250
Number of Data Points
200
150
100
50
TX Total Jitter (UI)
Figure 2-21:
Table 2-10:
0.50
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.24
0.26
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
RPT056_c2_20_051807
TX Jitter Generation at 2.00 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.00 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.154
0.270
0.198
0.021
UI
RJ, Random Jitter
0.103
0.278
0.141
0.019
UI
DJ, Deterministic Jitter
0.000
0.250
0.062
0.035
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 2.0 Gb/s Using 200 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.00 Gb/s, REFCLK = 200 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
140
Number of Data Points
120
100
80
60
40
20
TX Total Jitter (UI)
Figure 2-22:
Table 2-11:
0.50
0.48
0.46
0.44
0.42
0.40
0.38
RPT056_c2_21_051807
TX Jitter Generation at 2.00 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.00 Gb/s Data Rate
Parameter
56
0.36
0.34
0.32
0.30
0.28
0.24
0.26
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.099
0.231
0.163
0.020
UI
RJ, Random Jitter
0.073
0.212
0.108
0.016
UI
DJ, Deterministic Jitter
0.000
0.108
0.055
0.018
UI
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TX Jitter Generation
TX Jitter Generation at 2.488 Gb/s
Virtex-5 GTP TX Jitter, 2.488 Gb/s, REFCLK = 155.52 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
350
Number of Data Points
300
250
200
150
100
50
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-23:
Table 2-12:
RPT056_c2_22_051807
TX Jitter Generation at 2.488 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.488 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.144
0.270
0.200
0.021
UI
RJ, Random Jitter
0.078
0.256
0.139
0.017
UI
DJ, Deterministic Jitter
0.001
0.149
0.062
0.019
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 2.5 Gb/s Using 62.5 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.5 Gb/s, REFCLK = 62.5 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
140
Number of Data Points
120
100
80
60
40
20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-24:
Table 2-13:
RPT056_c2_23_051807
TX Jitter Generation at 2.5 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.5 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.211
0.358
0.271
0.028
UI
RJ, Random Jitter
0.158
0.418
0.304
0.033
UI
–
–
–
–
UI
DJ, Deterministic Jitter (1)
Notes:
1. RJ is overestimated, therefore DJ measurement is meaningless.
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TX Jitter Generation
TX Jitter Generation at 2.5 Gb/s Using 100 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.5 Gb/s, REFCLK = 100 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
200
180
Number of Data Points
160
140
120
100
80
60
40
20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-25:
Table 2-14:
RPT056_c2_24_051807
TX Jitter Generation at 2.5 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.5 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.242
0.404
0.299
0.034
UI
RJ, Random Jitter
0.148
0.379
0.235
0.029
UI
DJ, Deterministic Jitter
0.000
0.328
0.065
0.034
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 2.5 Gb/s Using 125 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.5 Gb/s, REFCLK = 125 MHz, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
200
180
Number of Data Points
160
140
120
100
80
60
40
20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-26:
Table 2-15:
RPT056_c2_25_051807
TX Jitter Generation at 2.5 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.5 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.154
0.295
0.205
0.023
UI
RJ, Random Jitter
0.138
0.344
0.222
0.026
UI
–
–
–
–
UI
DJ, Deterministic Jitter (1)
Notes:
1. RJ is overestimated, therefore DJ measurement is meaningless.
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TX Jitter Generation
TX Jitter Generation at 2.5 Gb/s Using 250 MHz REFCLK
Virtex-5 GTP TX Jitter, 2.5 Gb/s, REFCLK = 250 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
300
Number of Data Points
250
200
150
100
50
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-27:
Table 2-16:
RPT056_c2_26_051807
TX Jitter Generation at 2.5 Gb/s, C and I Grade
TX Jitter Generation Measurement at 2.5 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.116
0.249
0.181
0.023
UI
RJ, Random Jitter
0.085
0.259
0.143
0.019
UI
DJ, Deterministic Jitter
0.000
0.121
0.040
0.019
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 3.125 Gb/s
Virtex-5 GTP TX Jitter, 3.125 Gb/s, REFCLK = 156.25 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
300
Number of Data Points
250
200
150
100
50
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-28:
Table 2-17:
TX Jitter Generation at 3.125 Gb/s, C and I Grade
TX Jitter Generation Measurement at 3.125 Gb/s Data Rate
Parameter
62
RPT056_c2_27_051807
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.156
0.320
0.229
0.024
UI
RJ, Random Jitter
0.102
0.270
0.155
0.018
UI
DJ, Deterministic Jitter
0.000
0.161
0.075
0.022
UI
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TX Jitter Generation
TX Jitter Generation at 3.2 Gb/s
Virtex-5 GTP TX Jitter, 3.200 Gb/s, REFCLK = 320 MHz
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
180
Number of Data Points
160
140
120
100
80
60
40
20
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0
TX Total Jitter (UI)
Figure 2-29:
Table 2-18:
RPT056_c2_28_051807
TX Jitter Generation at 3.2 Gb/s, C and I Grade
TX Jitter Generation Measurement at 3.2 Gb/s Data Rate
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.154
0.357
0.227
0.033
UI
RJ, Random Jitter
0.127
0.347
0.213
0.030
UI
DJ, Deterministic Jitter
0.000
0.350
0.017
0.047
UI
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Chapter 2: PMA Transmitter Characterization
TX Jitter Generation at 3.75 Gb/s
Virtex-5 GTP TX Jitter, 3.750 Gb/s, REFCLK = 187.5 MHz
Number of Data Points
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 100°C)
600
500
400
300
200
100
TX Total Jitter (UI)
Figure 2-30:
Table 2-19:
0.50
0.48
0.46
0.44
0.42
RPT056_c2_103_040308
TX Jitter Generation at 3.75 Gb/s, C and I Grade
TX Jitter Generation Measurement at 3.75 Gb/s Data Rate
Parameter
64
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.206
0.348
0.252
0.018
UI
RJ, Random Jitter
0.117
0.245
0.174
0.017
UI
DJ, Deterministic Jitter
0.009
0.148
0.079
0.019
UI
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TX Jitter Generation
Conclusion
Table 2-20 provides a summary of the results by data rate.
Table 2-20:
Summary of Results for TX Jitter Generation
Data Rate
(Gb/s)
REFCLK
(MHz)
TJ
(Avg)
RJ
(1E–12 Avg)
DJ
(Avg)
TJ
Std Dev
Units
Notes
0.500
100
0.052
-
-
0.006
UI
Oversampling
1.000
100
0.124
0.072
0.053
0.021
UI
1.250
125
0.123
0.077
0.046
0.015
UI
2.000
100
0.198
0.141
0.062
0.021
UI
2.000
200
0.163
0.108
0.055
0.020
UI
2.488
155.52
0.200
0.139
0.062
0.021
UI
2.500
62.5
0.271
0.304
-
0.028
UI
2.500
100
0.299
0.235
0.065
0.034
UI
2.500
125
0.205
0.222
-
0.023
UI
2.500
250
0.181
0.143
0.040
0.023
UI
3.125
156.25
0.229
0.155
0.075
0.024
UI
3.200
320
0.227
0.213
0.017
0.033
UI
3.750
187.5
0.252
0.174
0.079
0.018
UI
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RJ Overestimated
RJ Overestimated
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Chapter 2: PMA Transmitter Characterization
TX REFCLK to TX Jitter Transfer
Test Description
The TX REFCLK to TX Jitter Transfer test was an ATE test designed to identify the amount
of jitter that transfers from the REFCLK source to the PMA Transmitter. This test measures
sinusoidal jitter transfer from REFCLK to the PMA transmitter outputs. The sinusoidal
modulation was swept across the frequency spectrum in discrete steps and then fed into
REFCLK. The corresponding modulation amplitudes were measured at the TX output. The
ratio of TX output modulation amplitude to the REFCLK input modulation amplitude was
measured as jitter transfer.
Two results are reported for each measured data rate: a modulation frequency trend graph
and a histogram that shows the –3 dB loop bandwidth. Additionally, a table shows the
minimum, maximum, average, mean, and standard deviation values for the –3 dB loop
bandwidth histogram
Test Setup
TX REFCLK to TX jitter transfer data was collected using ATE. Figure 2-31 illustrates the
equipment setup used for this test.
ATE was used to measure TX jitter on all twelve GTP transceivers simultaneously. A
ParBERT analyzer was used to measure the Bit Error Ratio (BER) of each of the twelve GTP
TX outputs. The reported jitter is broadband, with no filtering. TX jitter was measured
using the Bath Tub Curve (BTC) method using 10E9 bits of data.
The device was configured using JTAG. Power was supplied from eight programmable
power supplies through connectors on the side of the fixture.
High-speed connections from the device to the ParBERT were made through SMP and
SMA coax connectors. Blind-mate connectors were used to permit quick removal of the test
fixture. A low-profile, high-speed socket from Alta Nova was used to collect the data.
Two pairs of REFCLKs were used to clock the six GTP_DUAL tiles in two groups of three
GTP_DUAL tiles. The REFCLKs were sourced from a 3.2 Gb/s data generator, using a
clock pattern. Table 2-21 shows the appropriate REFCLK frequency and PLL multiplier to
create a proper PLL frequency for each of the tested data rates.
Table 2-21:
TX REFCLK to TX Jitter Transfer Test PLL Parameters
PLL_DIVSEL_FB
REFCLK Freq
PLL_DIVSEL_REF
and DIV
(MHz)
Post
Divider (1)
Oversample
2 * 5 = 10
2
1
1
2 * 5 = 10
2
1
62.5
1
4 * 5 = 20
1
1
1.25
100
2
5 * 5 = 25
1
1
2.5
1.25
125
1
2 * 5 = 10
1
1
2.5
1.25
250
1
1*5=5
1
1
3.125
1.5625
156.25
1
2 * 5 = 10
1
1
3.2
1.60
320
1
1*5=5
1
1
Data Rate
(Gb/s)
PLL Freq
(GHz)
1.0
1.00
100
1
2.0
2.00
200
2.5
1.25
2.5
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
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TX REFCLK to TX Jitter Transfer
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-22. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 2-22:
TX REFCLK to TX Jitter Transfer Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit data path
2.488 Gb/s
0: 8-bit data path
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-23.
Table 2-23:
TX REFCLK to TX Jitter Transfer Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
Virtex-5 FF1136 Test Fixture Board
FR-4 Length
3.25 inches
REFCLK and PLL Rates
Various (see Table 2-21)
Devices from typical, slow, and fast corner material were characterized using the ATE
system over voltage and temperature corners. All twelve GTP transceivers on each unit
were tested.
The configuration designs use fabric loopback in single-byte mode, with both TXUSRCLK
and RXUSRCLK clocked from TXOUTCLK. The configuration provides connections to
GTP_RESET, CDR_RESET, and the DRP interface. For all test cases, the RX was configured
for termination to GND with RX front end using internal AC coupling.
Serial data to the RX, provided by the Agilent ParBERT Pattern Generator, was converted
to 8-bit or 10-bit data at the PMA deserializer and passed through the PCS. The RX parallel
data port was connected to the TX parallel data port in the FPGA fabric.
The 8-bit or 10-bit data parallel data was then sent through the TX PCS and converted back
to serial data at the TX PMA. The TX serial data was connected to the ParBERT Data
Analyzer.
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Chapter 2: PMA Transmitter Characterization
The test fixture uses a high-speed ZIF socket to connect the DUT to the test equipment.
Figure 2-31 shows a diagram of the test setup.
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c2_29_041907
Figure 2-31:
68
ATE Test Setup for TX REFCLK to TX Jitter Transfer Tests
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TX REFCLK to TX Jitter Transfer
Results
TX Jitter Transfer at 1.0 Gb/s
Virtex-5 GTP TX Jitter Transfer, 1.0 Gb/s, REFCLK = 100 MHz, PLL = 1.0 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1
Jitter Transfer Gain (dB)
-1
-3
AVG
-5
MIN
-7
MAX
-9
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-32:
Table 2-24:
RPT056_c2_30_040308
TX Jitter Transfer vs. Modulation Frequency at 1.0 Gb/s
TX Jitter Transfer Measurement at 1.0 Gb/s Date Rate
Parameter
–3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
20.0
35.0
27.0
2.5
MHz
TX Jitter Transfer at 2.0 Gb/s, 200 MHz REFCLK
Virtex-5 GTP TX Jitter Transfer, 2.0 Gb/s, REFCLK = 200 MHz, PLL = 2.0 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1
Jitter Transfer Gain (dB)
-1
-3
AVG
-5
MIN
-7
MAX
-9
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-33:
Table 2-25:
RPT056_c2_32_051807
TX Jitter Transfer vs. Modulation Frequency at 2.00 Gb/s
TX Jitter Transfer Measurement at 2.0 Gb/s Data Rate
Parameter
–3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
27.7
31.1
29.0
0.65
MHz
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Chapter 2: PMA Transmitter Characterization
TX Jitter Transfer at 2.5 Gb/s, 62.5 MHz REFCLK
Virtex-5 GTP TX Jitter Transfer, 2.5 Gb/s, REFCLK = 62.5 MHz, PLL = 1.25 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
3
Jitter Transfer Gain (dB)
1
-1
-3
-5
AVG
-7
MIN
-9
MAX
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-34:
Table 2-26:
RPT056_c2_34_051807
TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s
TX Jitter Transfer Measurement at 2.5 Gb/s Data Rate
Parameter
–3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
6.0
11.8
8.8
1.0
MHz
TX Jitter Transfer at 2.5 Gb/s, 100 MHz REFCLK
Virtex-5 GTP TX Jitter Transfer, 2.5 Gb/s, REFCLK = 100 MHz, PLL = 1.25 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
3
Jitter Transfer Gain (dB)
1
-1
-3
-5
AVG
-7
MIN
-9
MAX
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-35:
Table 2-27:
TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s
TX Jitter Transfer Measurement at 2.5 Gb/s Data Rate
Parameter
–3 dB Loop Bandwidth
70
RPT056_c2_36_051807
Min
Max
Average
Std Dev
Units
6.6
13.4
9.6
1.1
MHz
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TX REFCLK to TX Jitter Transfer
TX Jitter Transfer at 2.5 Gb/s, 125 MHz REFCLK
Virtex-5 GTP TX Jitter Transfer, 2.5 Gb/s, REFCLK = 125 MHz, PLL = 1.25 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
3
Jitter Transfer Gain (dB)
1
-1
-3
-5
AVG
-7
MIN
-9
MAX
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-36:
Table 2-28:
RPT056_c2_38_051807
TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s
TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate
Parameter
–3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
20.9
33.6
26.5
2.1
MHz
TX Jitter Transfer at 2.5 Gb/s, 250 MHz REFCLK
Virtex-5 GTP TX Jitter Transfer, 2.5 Gb/s, REFCLK = 250 MHz, PLL = 1.25 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
3
Jitter Transfer Gain (dB)
1
-1
-3
-5
AVG
-7
MIN
-9
MAX
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-37:
Table 2-29:
RPT056_c2_40_051807
TX Jitter Transfer vs. Modulation Frequency at 2.5 Gb/s
TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate
Parameter
-3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
9.9
16.2
12.9
1.0
MHz
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Chapter 2: PMA Transmitter Characterization
TX Jitter Transfer at 3.125 Gb/s
Virtex-5 GTP TX Jitter Transfer, 3.125 Gb/s, REFCLK = 156.25 MHz, PLL = 1.56 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
3
Jitter Transfer Gain (dB)
1
-1
-3
-5
-7
AVG
-9
MIN
-11
MAX
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-38:
Table 2-30:
RPT056_c2_42_051807
TX Jitter Transfer vs. Modulation Frequency at 3.125 Gb/s
TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate
Parameter
-3 dB Loop Bandwidth
Min
Max
Average
Std Dev
Units
22.3
29.8
25.0
1.2
MHz
TX Jitter Transfer at 3.2 Gb/s
Virtex-5 GTP TX Jitter Transfer, 3.2 Gb/s, REFCLK = 320 MHz, PLL = 1.56 GHz
(Units = SS, TT, FF; VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1
Jitter Transfer Gain (dB)
-1
-3
-5
AVG
-7
MIN
-9
MAX
-11
-13
-15
1000
10000
100000
Modulation Frequency (KHz)
Figure 2-39:
Table 2-31:
TX Jitter Transfer vs. Modulation Frequency at 3.2 Gb/s
TX Jitter Transfer Measurement at 3.2 Gb/s Data Rate
Parameter
-3 dB Loop Bandwidth
72
RPT056_c2_44_051807
Min
Max
Average
Std Dev
Units
25.1
31.4
26.7
1.04
MHz
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TX REFCLK to TX Jitter Transfer
Conclusion
The TX jitter transferred from REFCLK is documented in this section. Both modulation
frequency and loop bandwidth are provided. Table 2-32 summarizes the minimum,
maximum, average, and standard deviation of the –3dB loop bandwidth point.
Table 2-32:
TX Jitter Transfer Measurement Summary
Parameter
TX –3 dB Loop
Bandwidth
Rate
Min
Max
Average Std Dev
1.0 Gb/s
20.0
35.0
27.0
2.5
MHz
2.0 Gb/s at 100 MHz
27.7
31.1
29.0
0.65
MHz
2.5 Gb/s at 62.5 MHz
6.0
11.8
8.8
1.0
MHz
2.5 Gb/s at 100 MHz
6.6
13.4
9.6
1.1
MHz
2.5 Gb/s at 125 MHz
20.9
33.6
26.5
2.1
MHz
2.5 Gb/s at 250 MHz
9.9
16.2
12.9
1.0
MHz
3.125 Gb/s
22.3
29.8
25.0
1.2
MHz
3.2 Gb/s
25.1
31.4
26.7
1.04
MHz
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Units
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Chapter 2: PMA Transmitter Characterization
TX Output Rise and Fall Time
Test Description
This test was designed to measure the 20% to 80% time for both rise and fall at maximum
swing.
Test Setup
Transmitter output rise and fall time tests were conducted using a bench test set-up. The
internal swing control port signals TXDIFFCTRL[2:0] and TXBUFDIFFCTRL[2:0] were set
to 000.
The Agilent N4901B Serial BERT generated data and drove a rotary relay to four GTP
channels. The device operated in fabric loopback mode, whereas the received high-speed
data was looped back to the high-speed transmitter at the FPGA fabric interface. The TX
amplitude test was performed at differing data rates with a 00001111 data pattern. The
TX peak-to-peak differential output voltage was measured using the Agilent DCA 86100A.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 2-33 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 2-33:
TX Output Rise and Fall Time Test PLL Parameters
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
Post
Divider (1)
Oversample
1.00
1.00
100
1
2 * 5 = 10
2
1
2.5
1.25
125
1
2 * 5 = 10
1
1
3.2
1.60
320
1
1*5=5
1
1
3.75
1.875
187.5
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
A clock data pattern (00001111) was chosen for this test to reduce the effect of DJ(ISI)
from the test fixture. The test fixture uses a high-speed ZIF socket to connect the DUT to the
test equipment. Figure 2-40 shows a picture of the test setup.
The Virtex-5 GTP transceiver characterization bench setup consisted of several
components, such as the host PC with GUI, an ML523 characterization board, and test
equipment. The entire system was controlled by a PC with a GUI interface. The GUI was
written with the Agilent VEE software tool. The GUI interfaces with the FPGA's internal
controller via 32-bit parallel cable. To perform the characterization test, the GUI (in the first
step) set the Agilent 6624A System SC power supply voltage, and the Agilent N4901B
Serial BERT data rate and pattern based on the test conditions.
The Agilent 6624A System Controller Power Supply provided a separate voltage to each of
5V, MGTAVTTTX, MGTAVTTRX, MGTAVTTRXC, MGTAVCCPLL, MGTAVCC supplies.
Other onboard regulators provided voltage for VCCO , VCCINT, and VCCAUX.
The Agilent N4901B Serial BERT internal clock was used as master clock source for the
entire system. The pattern generator differential output signals drive the RX-side inputs of
74
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TX Output Rise and Fall Time
the FPGA. The patter generator's trigger output signal drove the Agilent 8133A Pulse
Generator external clock input. Agilent 8133A Pulse Generator generated differential clock
signals for the FPGA GTPs. After setting the equipment mentioned above, the system
configured the FPGA and changed the TXDIFFCTRL setting. After configuring the FPGA,
the system started to collect data using the Agilent 86100A Wide-Band Oscilloscope. This
loop continued until all test conditions were covered.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-33.
Table 2-34:
TX REFCLK to TX Jitter Transfer Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
TXDIFFCTRL[2:0]
TXBUFDIFFCTRL[2:0]
Value
All but 2.488 Gb/s
1:10-bit data path
2.488 Gb/s
0: 8-bit data path
All rates
000 (max)
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-35.
Table 2-35:
TX Output Rise and Fall Time Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric
Pattern
00001111 clock data pattern
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
Junction Temperature
All 12 Locations
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 2-33)
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Chapter 2: PMA Transmitter Characterization
IEEE-488 (GPIB)
Agilent
3646A
Power
Supplies
Agilent
8133A
Signal
Generator
LPT
PC
IEEE-488
(GPIB)
CLK
Splitter
PC4
FR4
PCB
120
GTP_DUAL X0Y5
FR4
PCB
122
GTP_DUAL X0Y0
SAMs
SAMs
P/N
Pair
FPGA
DUT
Virtex-5 ML523 Characterization
Platform
Rotary
Relay x2
A
B
C
D
Agilent
34999B
Switch
Control
System
P/N
Pair
Agilent
86100A
DCA
LPT
RPT056_c2_46_052407
Figure 2-40:
76
Bench Test Setup for TX Output Rise and Fall Time Tests
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TX Output Rise and Fall Time
Results
TX Output Rise and Fall Time at 1.00 Gb/s
Virtex-5 GTP TX Rise, 1.0 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
70
Number of Data Points
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Rise 20%-80% (ps)
Figure 2-41:
RPT056_c2_47_051807
TX Output Rise Time at 1.00 Gb/s
Virtex-5 GTP TX Fall, 1.0 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
70
Number of Data Points
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Fall 80%-20% (ps)
RPT056_c2_48_051807
Figure 2-42: TX Output Fall Time at 1.00 Gb/s
Table 2-36:
TX Output Rise and Fall Time at 1.00 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
TX Output Rise Time
136.9
157.9
147.2
4.4
ps
TX Output Fall Time
116.4
158.0
131.0
6.26
ps
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Chapter 2: PMA Transmitter Characterization
TX Output Rise and Fall Time at 2.5 Gb/s, 125 MHz REFCLK
Virtex-5 GTP TX Rise, 2.5 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
90
Number of Data Points
80
70
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Rise 20%-80% (ps)
Figure 2-43:
RPT056_c2_49_051807
TX Output Rise Time at 2.5 Gb/s, 125 MHz REFCLK
Virtex-5 GTP TX Fall, 2.5 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
50
45
Number of Data Points
40
35
30
25
20
15
10
5
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Fall 80%-20% (ps)
Figure 2-44:
Table 2-37:
TX Output Rise and Fall Time at 2.5 Gb/s, 125 MHz REFCLK
Parameter
78
RPT056_c2_50_051807
TX Output Fall Time at 2.5 Gb/s, 125 MHz REFCLK
Min
Max
Average
Std Dev
Units
TX Output Rise Time
130.5
151.8
139.3
4.28
ps
TX Output Fall Time
100.8
132.0
117.4
6.7
ps
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TX Output Rise and Fall Time
TX Output Rise and Fall Time at 3.2 Gb/s
Virtex-5 GTP TX Rise, 3.2 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
60
Number of Data Points
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Rise 20%-80% (ps)
Figure 2-45:
RPT056_c2_51_051807
TX Output Rise Time at 3.2 Gb/s
Virtex-5 GTP TX Fall, 3.2 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
70
Number of Data Points
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Fall 80%-20% (ps)
Figure 2-46:
Table 2-38:
RPT056_c2_52_051807
TX Output Fall Time at 3.2 Gb/s
TX Output Rise and Fall Time at 3.2 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
TX Output Rise Time
126.2
155.9
139.48
6.37
ps
TX Output Fall Time
92.0
130.5
109.65
7.99
ps
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Chapter 2: PMA Transmitter Characterization
TX Output Rise and Fall Time at 3.75 Gb/s
Virtex-5 GTP TX Rise, 3.75 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
80
Number of Data Points
70
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Rise 20%-80% (ps)
Figure 2-47:
RPT056_c2_104_040308
TX Output Rise Time at 3.75 Gb/s
Virtex-5 GTP TX Fall, 3.75 Gb/s
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
80
Number of Data Points
70
60
50
40
30
20
10
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
0
TX Fall 80%-20% (ps)
RPT056_c2_105_040308
Figure 2-48: TX Output Fall Time at 3.75 Gb/s
Table 2-39:
TX Output Rise and Fall Time at 3.75 Gb/s
Parameter
80
Min
Max
Average
Std Dev
Units
TX Output Rise Time
118.3
149.6
135.09
5.78
ps
TX Output Fall Time
98.0
128.7
110.20
5.45
ps
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TX Output Rise and Fall Time
TX Output Rise and Fall Time as a Function of TXDIFFCTRL
Virtex-5 GTP TX Rise vs. TXDIFFCTL
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
TX Rise 20%-80% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
2.5 Gb/s
100.00
3.2 Gb/s
3.7 Gb/s
90.00
80.00
000
011
TXDIFFCTL
Figure 2-49:
110
RPT056_c2_53_040408
TX Output Rise Time as a Function of TXDIFFCTRL
Virtex-5 GTP TX Fall vs. TXDIFFCTL
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
TX Fall 80%-20% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
2.5 Gb/s
100.00
3.2 Gb/s
3.7 Gb/s
90.00
80.00
000
011
TXDIFFCTL
Figure 2-50:
110
RPT056_c2_54_040408
TX Output Fall Time as a Function of TXDIFFCTRL
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Chapter 2: PMA Transmitter Characterization
TX Output Rise and Fall Time as a Function of Process
Virtex-5 GTP TX Rise vs. Process
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
TX Rise 20%-80% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
2.5 Gb/s
100.00
3.2 Gb/s
3.7 Gb/s
90.00
80.00
SS
TT
Process
Figure 2-51:
FF
RPT056_c2_55_040408
TX Output Rise Time as a Function of Process
Virtex-5 GTP TX Fall vs. Process
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
1 Gb/s
150.00
2.5 Gb/s
TX Fall 80%-20% (ps)
3.2 Gb/s
140.00
3.7 Gb/s
130.00
120.00
110.00
100.00
90.00
80.00
SS
TT
Process
Figure 2-52:
82
FF
RPT056_c2_56_040408
TX Output Fall Time as a Function of Process
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TX Output Rise and Fall Time
TX Output Rise and Fall Time as a Function of Voltage
Virtex-5 GTP TX Rise vs. Voltage
(AVTTX = VNOM ±5%, Split: FF, SS, TT)
160.00
TX Rise 20%-80% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
2.5 Gb/s
100.00
3.2 Gb/s
3.7 Gb/s
90.00
80.00
AVTTTX–5%
AVTTTX+5%
Voltage
Figure 2-53:
RPT056_c2_57_040408
TX Output Rise Time as a Function of Voltage
Virtex-5 GTP TX Fall vs. Voltage
(AVTTX = VNOM ±5%, Split: FF, SS, TT)
160.00
TX Fall 80%-20% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
100.00
2.5 Gb/s
3.2 Gb/s
90.00
3.7 Gb/s
80.00
AVTTTX–5%
AVTTTX+5%
Voltage
Figure 2-54:
RPT056_c2_58_040408
TX Output Fall Time as a Function of Voltage
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Chapter 2: PMA Transmitter Characterization
TX Output Rise and Fall Time as a Function of Temperature
Virtex-5 GTP TX Rise vs. Temperature
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
TX Rise 20%-80% (ps)
150.00
140.00
130.00
120.00
110.00
1 Gb/s
100.00
2.5 Gb/s
3.2 Gb/s
90.00
3.7 Gb/s
80.00
–40
0
100
Temperature
Figure 2-55:
RPT056_c2_59_040708
TX Output Rise Time as a Function of Temperature
Virtex-5 GTP TX Fall vs. Temperature
(AVTTX = VNOM ± 5%, Split: FF, SS, TT)
160.00
TX Fall 80%-20% (ps)
150.00
140.00
1 Gb/s
2.5 Gb/s
3.2 Gb/s
3.7 Gb/s
130.00
120.00
110.00
100.00
90.00
80.00
–40
0
Temperature
Figure 2-56:
84
100
RPT056_c2_60_040708
TX Output Fall Time as a Function of Temperature
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TX Output Rise and Fall Time
Conclusion
The histograms in this section illustrate the rise and fall response of the PMA transmitter
across process, voltage, and temperature. Additionally, the above trend graphs illustrate
the effects of process, voltage, and temperature on both output rise and fall time. A graph
is also provided for rise and fall time, which illustrates the effects of setting TXDIFFCTRL
to various values.
Table 2-40 and Table 2-41 summarize the minimum, maximum, average, and standard
deviation for TX rise and fall times.
Table 2-40:
Parameter
Tx Rise Time
Table 2-41:
Parameter
Tx Fall Time
TX Rise Time Measurement Summary
Rate
Min
Max
Average
Std Dev
Units
1.0 Gb/s
136.9
157.9
147.2
4.4
ps
2.5 Gb/s at 125 MHz
130.5
151.8
139.3
4.3
ps
3.2 Gb/s
126.2
155.9
139.5
6.4
ps
3.75Gb/s
118.3
149.6
135.09
5.78
ps
TX Fall Time Measurement Summary
Rate
Min
Max
Average
Std Dev
Units
1.0 Gb/s
116.4
158.0
131.0
6.3
ps
2.5 Gb/s at 125 MHz
100.8
132.0
117.4
6.7
ps
3.2 Gb/s
92.0
130.5
109.7
8.0
ps
3.75 Gb/s
98.0
128.7
110.20
5.45
ps
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Chapter 2: PMA Transmitter Characterization
TX Output Amplitude
Test Description
Transmitter output amplitude tests were conducted using the same TX bench setup
depicted in Figure 1-2, page 28. Figure 2-57 illustrates the equipment setup for these tests.
The Agilent N4901B Serial BERT generates data and drives a rotary relay to four GTP
channels. The device operates in fabric loopback mode, whereas the received high-speed
data was looped back to the high-speed transmitter at the FPGA fabric interface. The
TX-side amplitude test was performed at 2.5 Gb/s data rate with 00001111 data pattern.
TX peak-to-peak differential output voltage was measured using Agilent DCA 86100A.
Test Setup
TX output amplitude data was collected using the TX bench setup. Figure 2-57 illustrates
the equipment used for this test.
The Agilent N4901B Serial BERT internal clock was used as the master clock source for the
entire system. The pattern generator differential output signals drove the RX-side inputs of
the FPGA. The pattern generator's trigger output signal drove the Agilent 8133A Pulse
Generator's external clock input. The Agilent 8133A Pulse Generator generated differential
clock signals for FPGA GTP transceivers. After setting this equipment, the system
configured the FPGA and changed the TXDIFFCTRL setting. After configuring the FPGA
system, the equipment started to collect data using the Agilent 86100A Wide-Band
oscilloscope. The above loop continued until all test conditions were covered.
The internal swing control port signals TXDIFFCTRL [2:0] and TXBUFDIFFCTRL [2:0]
were set to 000.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 2-42 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 2-42:
TX Output Amplitude Test PLL Parameters
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
Post
Divider (1)
Oversample
1.00
1.00
100
1
2 * 5 = 10
2
1
2.5
1.25
125
1
2 * 5 = 10
1
1
3.2
1.60
320
1
1*5=5
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
A clock data pattern (00001111) was chosen for this test to reduce the effect of DJ(ISI)
from the test fixture. The test fixture uses a high-speed ZIF socket to connect the DUT to the
test equipment. Figure 2-57 shows a picture of the test setup.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-43. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
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TX Output Amplitude
Table 2-43:
TX Output Amplitude Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
INTDATAWIDTH
1: 10-bit datapath
TXBUFDIFFCTRL0[2:0]
TXBUFDIFFCTRL1[2:0]
All
000, 011, 110
TXDIFFCTRL0[2:0]
TXDIFFCTRL1[2:0]
GTP_DUAL Attribute Settings
Attribute
Rate Affected
Value
TXDIFFBOOST_0
FALSE
TXDIFFBOOST_1
All
TXPREEMPHASIS0[2:0]
000
TXPREEMPHASIS1[2:0]
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-44.
Table 2-44:
TX Output Amplitude Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric
Pattern
Clock Pattern 00001111
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 2-42)
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Chapter 2: PMA Transmitter Characterization
IEEE-488 (GPIB)
Agilent
3646A
Power
Supplies
Agilent
8133A
Signal
Generator
LPT
PC
IEEE-488
(GPIB)
CLK
Splitter
PC4
FR4
PCB
120
GTP_DUAL X0Y5
FR4
PCB
122
GTP_DUAL X0Y0
SAMs
SAMs
P/N
Pair
FPGA
DUT
Virtex-5 ML523 Characterization
Platform
Rotary
Relay x2
A
B
C
D
Agilent
34999B
Switch
Control
System
P/N
Pair
Agilent
86100A
DCA
LPT
RPT056_c2_61_052407
Figure 2-57:
Bench Test Setup for TX Output Amplitude Tests
Results
Figure 2-58 through Figure 2-69 illustrate the TX amplidtude test results.
NOTE: The bimodal distribution show in Figure 2-58 to Figure 2-60 and Figure 2-63 to
Figure 2-65 occurs because of sweeping across power supply settings. Figure 2-61 and
Figure 2-62 show this separation more clearly.
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TX Output Amplitude
TX Amplitude Test, Histograms by Process
Virtex-5 GTP TX Amplitude, All Rates, SS
(Units = SS, VCC = VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
60
Number of Data Points
50
40
30
20
10
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
Figure 2-58:
RPT056_c2_67_051807
TX Amplitude, Across All Rates, Silicon = SS
Virtex-5 GTP TX Amplitude, All Rates, TT
(Units = TT, VCC = VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
40
Number of Data Points
35
35
25
20
15
10
5
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
Figure 2-59:
RPT056_c2_63_051807
TX Amplitude, Across All Rates, Silicon = TT
Virtex-5 GTP TX Amplitude, All Rates, FF
(Units = FF, VCC = VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
40
Number of Data Points
35
35
25
20
15
10
5
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
Figure 2-60:
RPT056_c2_64_051807
TX Amplitude, Across All Rates, Silicon = FF
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Chapter 2: PMA Transmitter Characterization
TX Amplitude Test, Histograms by Voltage
Virtex-5 GTP TX Amplitude, All Rates, VMIN
(Units = TT, FF, SS, VCC = VNOM – 5% V, Temp = –40°C, 0°C, 100°C)
100
90
Number of Data Points
80
70
60
50
40
30
20
10
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
Figure 2-61:
RPT056_c2_65_051807
TX Amplitude, across All Rates, VCC = VMIN
Virtex-5 GTP TX Amplitude, All Rates, VMAX
(Units = TT, FF, SS, VCC = VNOM + 5% V, Temp = –40°C, 0°C, 100°C)
100
90
Number of Data Points
80
70
60
50
40
30
20
10
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
Figure 2-62:
90
RPT056_c2_66_051807
TX Amplitude, across All Rates, VCC = VMAX
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TX Output Amplitude
TX Amplitude Test, Histograms by Temperature
Virtex-5 GTP TX Amplitude, All Rates, –40°C
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C)
40
Number of Data Points
35
30
25
20
15
10
5
0.7
0.72
0.74
0.76
0.78
0.8
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
1.34
1.36
1.38
1.4
0
TX Differential Peak-Peak (V)
RPT056_c2_67_051807
Figure 2-63: TX Amplitude, across All Rates, Temp = –40°C
Virtex-5 GTP TX Amplitude, All Rates, 0°C
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = 0°C)
45
Number of Data Points
40
35
30
25
20
15
10
5
TX Differential Peak-Peak (V)
Figure 2-64:
1.38
1.3
1.34
1.26
1.22
1.18
1.1
1.14
1.06
1.02
0.98
0.9
0.94
0.86
0.82
0.78
0.7
0.74
0
RPT056_c2_68_051807
TX Amplitude, Across All Rates, Temp = 0°C
Virtex-5 GTP TX Amplitude, All Rates, 100°C
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = 100°C)
45
Number of Data Points
40
35
30
25
20
15
10
5
TX Differential Peak-Peak (V)
Figure 2-65:
1.46
1.42
1.38
1.34
1.3
1.26
1.22
1.18
1.1
1.14
1.06
1.02
0.98
0.94
0.9
0.86
0.82
0.78
0.7
0.74
0
RPT056_c2_69_051807
TX Amplitude, Across All Rates, Temp = 100°C
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Chapter 2: PMA Transmitter Characterization
TX Amplitude Test, Trends by Process
Virtex-5 GTP TX Amplitude Process Split vs. TXDIFFCTRL
(Data Rate = 1, 2.5, 3.2 Gb/s, AVTTX = VNOM ± 5%, Temp = –40°C, 0°C, 100°C)
1.400
1.200
FF
SS
TT
VDPPOUT
(V)
1.000
0.800
0.600
0.400
0.200
0.000
0
11
TXDIFFCTRL
Figure 2-66:
110
RPT056_c2_70_051807
TX Amplitude, Process Split vs. TXDIFFCTRL
TX Amplitude Test, Trends by Voltage
Virtex-5 GTP TX Amplitude MGTAVTTTX Supply Trend vs. TXDIFFCTRL
(Data Rate = 1, 2.5, 3.2 Gb/s, Split: FF, SS, TT Temp = –40°C, 0°C, 100°C)
1.400
1.200
1.16V
1.28V
VDPPOUT
(V)
1.000
0.800
0.600
0.400
0.200
0.000
0
11
TXDIFFCTRL
Figure 2-67:
92
110
RPT056_c2_71_051807
TX Amplitude, MGTAVTTTX Supply vs. TXDIFFCTRL Trend
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TX Output Amplitude
TX Amplitude Test, Trends by Temperature
Virtex-5 GTP TX Amplitude Temperature vs. TXDIFFCTRL
(Data Rate = 1, 2.5, 3.2 Gb/s, MGTAVTTTX = VNOM ± 5%, Split = SS, TT, FF)
1.400
1.200
–40°C
0°C
100°C
VDPPOUT
(V)
1.000
0.800
0.600
0.400
0.200
0.000
0
11
TXDIFFCTRL
Figure 2-68:
110
RPT056_c2_72_051807
TX Amplitude, Temperature vs. TXDIFFCTRL
TX Amplitude Test, Trends by Data Rate
Virtex-5 GTP TX Amplitude Data Rate vs. TXDIFFCTRL
(MGTAVTTTX = VNOM ± 5%, Split: FF, SS, TT Temp = –40°C, 0°C, 100°C)
1.400
1.200
1 Gb/s
2.5 Gb/s
3.2 Gb/s
VDPPOUT
(V)
1.000
0.800
0.600
0.400
0.200
0.000
0
11
TXDIFFCTRL
Figure 2-69:
110
RPT056_c2_73_051807
TX Amplitude, Data Rate vs. TXDIFFCTRL
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Chapter 2: PMA Transmitter Characterization
Conclusion
Table 2-45 is a summary of the preceding histograms, demonstrating TX output amplitude
across various conditions of test.
Table 2-45:
TX Output Amplitude Summary
Parameter
Min
Max
Average
Std Dev
Units
TX Amplitude, SS Si
0.990
1.271
1.129
0.070
V
TX Amplitude, TT Si
1.065
1.298
1.164
0.066
V
TX Amplitude, FF Si
1.085
1.325
1.192
0.068
V
TX Amplitude, VMIN
0.990
1.192
1.100
0.038
V
TX Amplitude, VMAX
1.073
1.325
1.224
0.040
V
TX Amplitude, –40°C
0.990
1.325
1.162
0.078
V
TX Amplitude, 0°C
1.025
1.316
1.170
0.073
V
TX Amplitude, 100°C
1.038
1.277
1.153
0.066
V
Figure 2-70 shows a qualitative summary of TX Amplitude with no pre-emphasis enabled.
RPT056_c2_98_051807
Figure 2-70:
94
Qualitative TX Amplitude Swept across TXDIFFCTRL
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TX Output Amplitude Squelched
TX Output Amplitude Squelched
Test Description
The TX output amplitude squelched test was designed to measure the TX output
amplitude in Out Of Band (OOB) mode where the output gets squelched in order to
produce an OOB signal to the receiver. This test executes a squelching command and then
measures the output amplitude.
Test Setup
Transmitter output amplitude tests were conducted using the same TX bench setup
depicted in Figure 1-2, page 28. Figure 2-71 illustrates the equipment setup for these tests.
Unlike the TX output amplitude tests in the “TX Output Amplitude” section, this test
squelched the output and then measured the resultant TX amplitude.
Agilent N4901B Serial BERT generated data and drove four channels of the high-speed
multiplexer. The high-speed multiplexer drove data to four different GTP transceivers of
the FPGA. The device operated in fabric loopback mode, whereas the received high-speed
data was looped back to the high-speed transmitter at the FPGA fabric interface. The
TX-side amplitude test was performed at 2.5 Gb/s data rate with 00001111 data pattern.
A squelch command was applied and then the TX peak-to-peak differential output voltage
was measured using Agilent DCA 86100A.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 2-46 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 2-46:
TX Output Amplitude (Squelched) Test PLL Parameters
Data Rate
(Gb/s)
PLL Freq
(GHz)
2.5
1.25
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
125
1
Post
Divider (1)
Oversample
1
1
2 * 5 = 10
Notes:
1. Post divider is the appropriate settings for PLL_TXDIVSELOUT[1:0] and PLL_TXDIVSEL_COMM_OUT.
A clock data pattern (00001111) was chosen for this test to reduce the effect of DJ(ISI)
from the test fixture. The test fixture uses a high-speed ZIF socket to connect the DUT to the
test equipment. Figure 2-71 shows a picture of the test setup.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-47. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
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Chapter 2: PMA Transmitter Characterization
Table 2-47:
TX Output Amplitude (Squelched) Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-48.
Table 2-48:
TX Output Amplitude (Squelched) Test Conditions
Test Parameter
Loopback Mode
Fabric
Pattern
Clock Pattern 00001111
Silicon Corner Used
SS, TT, FF,
GTP_DUAL Location Used
Junction Temperature
All 12 Locations
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL rates
96
Test Value
Various (see Table 2-46)
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TX Output Amplitude Squelched
IEEE-488 (GPIB)
Agilent
8133A
Signal
Generator
Agilent
3646A
Power
Supplies
LPT
PC
IEEE-488
(GPIB)
CLK
Splitter
PC4
FR4
PCB
120
GTP_DUAL X0Y5
FR4
PCB
122
GTP_DUAL X0Y0
FPGA
DUT
Virtex-5 ML523 Characterization
Platform
SAMs
SAMs
P/N
Pair
Rotary
Relay x2
A
B
C
D
Agilent
34999B
Switch
Control
System
P/N
Pair
Agilent
86100A
DCA
LPT
RPT056_c2_74_052407
Figure 2-71:
Bench Test Setup for TX Output Amplitude (Squelched) Tests
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Chapter 2: PMA Transmitter Characterization
Results
TX Output Amplitude OOB Squelched
Virtex-5 GTP TX OOB Squelched Amplitude
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
140
Number of Data Points
120
100
80
60
40
20
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
0
TX OOB Squelched Amplitude (mV)
Figure 2-72:
Table 2-49:
RPT056_c2_75_051807
TX Output Amplitude Histogram when OOB Squelched, 2.5 Gb/s
TX Output Fall Time at 2.5 Gb/s, 125 MHz REFCLK
Parameter
TX Output Amplitude,
OOB Squelched
Min
Max
Average
Std Dev
Units
2.75
4.25
3.54
0.30
mV
RPT056_c2_76_052107
Figure 2-73: TX Output Amplitude Squelched, 2.5 Gb/s
Conclusion
Figure 2-72 and Figure 2-73 demonstrate the PMA transmitter characteristics when OOB
squelched. This data is within data sheet specification.
98
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TX Pre-Emphasis
TX Pre-Emphasis
Test Description
TX pre-emphasis tests were bench tests designed to measure the effects on the PMA
transmitter for various settings of TX_PREEMPHASIS as well as the effects of Process,
Voltage, and Temperature (PVT). Data is presented in both VSMALL / VLARGE percentage
as well as VSMALL / VLARGE dB at various rates. Additionally, TX_PREEMPHASIS was
varied, and the resultant trend graph is presented. PVT trend graphs are also presented to
illustrate the effects of PVT on the pre-emphasis.
Test Setup
TX pre-emphasis tests were conducted using the same TX bench setup depicted in
Figure 1-2, page 28. Figure 2-74 illustrates the equipment used for this test.
The Agilent N4901B Serial BERT generated data and drove four channels of the high-speed
multiplexer. The high-speed multiplexer drove data to four different GTP transceivers of
the FPGA. The device operated in fabric loopback mode, whereas the received high-speed
data was looped back to the high-speed transmitter at the FPGA fabric interface. The TX
pre-emphasis test was performed at various data rates with 00001111 data pattern. The
TX output voltage was measured using Agilent DCA 86100A, with a focus on measuring
the pre-emphasis.
The TX pre-emphasis was tested at various rates at maximum setting. Data is presented in
both VSMALL / VLARGE and VSMALL / VLARGE dB percentages. Additionally, at 3.2 Gb/s,
TX pre-emphasis was measured at both minimum and maximum settings to illustrate the
range of TX pre-emphasis. PVT was varied across the specified data rates and trend data
was extracted to illustrate the effects that PVT has on TX_PREEMPHASIS when set to
maximum (111). Data was further collected at 3.2 Gb/s while varying TX_PREEMPHASIS
from 000 to 111 to demonstrate the percentage of change that each step has across PVT.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 2-50 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 2-50:
TX Pre-emphasis Test PLL Parameters
PLL_DIVSEL_FB
REFCLK Freq
PLL_DIVSEL_REF
and DIV
(MHz)
Post
Divider (1)
Oversample
2 * 5 = 10
4
5
1
2 * 5 = 10
1
5
100
1
2 * 5 = 10
4
1
1.00
100
1
2 * 5 = 10
2
1
1.25 Gb/s
1.25
125
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.0 Gb/s
2.00
200
1
2 * 5 = 10
2
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
Data Rate
PLL Freq
(GHz)
100 Mb/s (OS)
1.00
100
1
500 Mb/s (OS)
1.25
125
500 Mb/s
1.00
1.00 Gb/s
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Chapter 2: PMA Transmitter Characterization
Table 2-50:
TX Pre-emphasis Test PLL Parameters (Continued)
PLL_DIVSEL_FB
REFCLK Freq
PLL_DIVSEL_REF
and DIV
(MHz)
Post
Divider (1)
Oversample
2 * 5 = 10
1
1
1
1*5=5
1
1
156.25
1
2 * 5 = 10
1
1
1.60
320
1
1*5=5
1
1
1.875
187.5
1
2 * 5 = 10
1
1
Data Rate
PLL Freq
(GHz)
2.5 Gb/s
1.25
125
1
2.5 Gb/s
1.25
250
3.125 Gb/s
1.5625
3.2 Gb/s
3.75 Gb/s
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
A clock data pattern (00001111) was chosen for this test to reduce the effect of DJ(ISI)
from the test fixture. The test fixture uses a high-speed ZIF socket to connect the DUT to the
test equipment. Figure 2-74 shows a picture of the test setup.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-51. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 2-51:
TX Pre-emphasis Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-52.
Table 2-52:
TX Pre-emphasis Test Conditions
Test Parameter
Loopback Mode
Fabric
Pattern
Clock Pattern 00001111
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
100
Test Value
Various (see Table 2-50)
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TX Pre-Emphasis
IEEE-488 (GPIB)
Agilent
3646A
Power
Supplies
Agilent
8133A
Signal
Generator
LPT
PC
IEEE-488
(GPIB)
CLK
Splitter
PC4
FR4
PCB
120
GTP_DUAL X0Y5
FR4
PCB
122
GTP_DUAL X0Y0
SAMs
SAMs
P/N
Pair
FPGA
DUT
Virtex-5 ML523 Characterization
Platform
Rotary
Relay x2
A
B
C
D
Agilent
34999B
Switch
Control
System
P/N
Pair
Agilent
86100A
DCA
LPT
RPT056_c2_77_052407
Figure 2-74: Bench Test Setup for TX Pre-emphasis Tests
Results
Figure 2-75 illustrates conceptually how TX pre-emphasis works. A minimum and
maximum output amplitude are shown. TX pre-emphasis is shown on the histograms in
this section as Vsmall / Vlarge .
Vsmall
Vlarge
RPT056_c2_99_052107
Figure 2-75: Pre-emphasis Concept Showing Min and Max Voltage Levels
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Chapter 2: PMA Transmitter Characterization
TX Pre-emphasis Test, Minimum Setting
Virtex-5 GTP TX Pre-emphasis, Min = 000
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
700
Number of Data Points
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
TX Pre-emphasis VSMALL/VLARGE (%)
Figure 2-76:
Table 2-53:
90
100
RPT056_c2_78_051807
TX Pre-emphasis, Minimum Setting, 2.5 Gb/s, 125 MHz REFCLK
TX Pre-emphasis, Minimum Setting at 2.5 Gb/s, 125 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 000
93.82
99.94
98.39
1.08
%
TX Pre-emphasis Test, Maximum Setting
Virtex-5 GTP TX Pre-emphasis, Max = 111,
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
300
Number of Data Points
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
TX Pre-emphasis VSMALL/VLARGE (%)
Figure 2-77:
Table 2-54:
102
90
100
RPT056_c2_79_051807
TX Pre-emphasis, Maximum Setting at 2.5 Gb/s, 125 MHz REFCLK
TX Pre-emphasis, Maximum Setting at 2.5 Gb/s, 125 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
60.27
73.93
68.58
2.80
%
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TX Pre-Emphasis
TX Pre-emphasis Test, Max Setting, 1 Gb/s, Percentage
Virtex-5 GTP TX Pre-emphasis 1Gb/s, Max = 111,
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
20
40
60
80
100
TX Pre-emphasis (%)
Figure 2-78:
Table 2-55:
120
RPT056_c2_80_051807
TX Pre-emphasis, Max Setting, 1 Gb/s, Percentage
TX Pre-emphasis, Max Setting, 1 Gb/s, Percentage
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
49.7
65.9
54.2
3.797
%
TX Pre-emphasis Test, Max Setting, 1 Gb/s, dB
Virtex-5 GTP TX Pre-emphasis 1Gb/s, Max = 111,
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
1
2
3
4
5
TX Pre-emphasis (dB)
6
RPT056_c2_81_051807
Figure 2-79: TX Pre-emphasis, Max Setting, 1 Gb/s, dB
Table 2-56:
TX Pre-emphasis, Max Setting, 1 Gb/s, dB
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
3.5
4.4
3.8
0.211
dB
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Chapter 2: PMA Transmitter Characterization
TX Pre-emphasis Test, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, %
Virtex-5 GTP TX Pre-emphasis 2.5 Gb/s, Max = 111,
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
20
40
60
80
100
TX Pre-emphasis (%)
Figure 2-80:
120
RPT056_c2_82_051807
TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, Percentage
TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, Percentage
Table 2-57:
Parameter
TX_PREEMPHASIS[2:0] = 111
Min
Max
Average
Std Dev
Units
41.0
57.6
46.4
3.614
%
TX Pre-emphasis Test, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB
Virtex-5 GTP TX Pre-emphasis 2.5 Gb/s, Max = 111
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
100
90
Number of Data Points
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
TX Pre-emphasis (dB)
Figure 2-81:
Table 2-58:
104
6
RPT056_c2_83_051807
TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB
TX Pre-emphasis, Max Setting, 2.5 Gb/s, 125 MHz REFCLK, dB
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
3.0
4.0
3.3
0.212
dB
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TX Pre-Emphasis
TX Pre-emphasis Test, Max Setting, 3.2 Gb/s, Percentage
Virtex-5 GTP TX Pre-emphasis 3.2 Gb/s, Max = 111
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
20
40
60
80
100
TX Pre-emphasis (%)
Figure 2-82:
Table 2-59:
120
RPT056_c2_84_051807
TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage
TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
37.4
56.5
42.3
3.771
%
TX Pre-emphasis Test, Max Setting, 3.2 Gb/s, dB
Virtex-5 GTP TX Pre-emphasis 3.2 Gb/s, Max = 111
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
1
2
3
4
5
TX Pre-emphasis (dB)
Figure 2-83:
Table 2-60:
6
RPT056_c2_85_051807
TX Pre-emphasis, Max Setting, 3.2 Gb/s, dB
TX Pre-emphasis, Max Setting, 3.2 Gb/s, Percentage
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
2.8
3.9
3.1
0.226
dB
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Chapter 2: PMA Transmitter Characterization
TX Pre-emphasis Test, Max Setting, 3.75 Gb/s, Percentage
Virtex-5 GTP TX Pre-emphasis 3.75 Gb/s, Max = 111
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
20
40
60
80
100
TX Pre-emphasis (%)
Figure 2-84:
Table 2-61:
120
RPT056_c2_106_040708
TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage
TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
35.2
52.6
41.8
3.557
%
TX Pre-emphasis Test, Max Setting, 3.75 Gb/s, dB
Virtex-5 GTP TX Pre-emphasis 3.75 Gb/s, Max = 111
(Units = TT, FF, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
120
Number of Data Points
100
80
60
40
20
0
0
1
2
3
4
5
TX Pre-emphasis (dB)
Figure 2-85:
Table 2-62:
106
6
RPT056_c2_107_040708
TX Pre-emphasis, Max Setting, 3.75 Gb/s, dB
TX Pre-emphasis, Max Setting, 3.75 Gb/s, Percentage
Parameter
Min
Max
Average
Std Dev
Units
TX_PREEMPHASIS[2:0] = 111
2.6
3.7
3.0
0.216
dB
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TX Pre-Emphasis
TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, %
Virtex-5 GTP TX Pre-emphasis = 111, MGTAVTTTX Supply Trend vs. Temperature
(Data Rate = 1, 2.5, 3.2 Gb/s, Split: FF, SS, TT)
46.0
TX Median
Pre-emphasis (%)
45.5
45.0
44.5
44.0
Vmin
Vmax
43.5
43.0
42.5
–40°C
0°C
Temperature
Figure 2-86:
100°C
RPT056_c2_86_051807
TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, %
TX Pre-emphasis Test, MGTAVTTTX Supply Trend vs. Temperature, dB
Virtex-5 GTP TX Pre-emphasis = 111, MGTAVTTTX Supply Trend vs. Temperature
(Data Rate = 1, 2.5, 3.2 Gb/s, Split: FF, SS, TT)
3.28
3.26
TX Median
Pre-emphasis (dB)
3.24
3.22
3.2
3.16
3.16
Vmin
3.14
Vmax
3.12
3.1
3.08
–40°C
0°C
Temperature
Figure 2-87:
100°C
RPT056_c2_87_051807
TX Pre-emphasis Test, AVTTX Supply Trend vs. Temperature, dB
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Chapter 2: PMA Transmitter Characterization
TX Pre-emphasis Test, Percentage vs. Data Rate
Virtex-5 GTP TX Pre-emphasis = 111, Percentage vs. Data Rate
(Split: FF, SS, TT, Temp = –40°C, 0°C, 100°C, VCC=VNOM ±5%)
70
TX
Pre-emphasis (%)
60
50
40
30
Ave
Min
20
Max
10
0
1
2.5
Data Rate
Figure 2-88:
3.2
RPT056_c2_88_051807
TX Pre-emphasis Test, Percentage vs. Data Rate
TX Pre-emphasis Test, dB vs. Data Rate
Virtex-5 GTP TX Pre-emphasis = 111, dB vs. Data Rate
(Split: FF, SS, TT, Temp = –40°C, 0°C, 100°C, VCC=VNOM ±5%)
5
4.5
TX
Pre-emphasis (%)
4
3.5
3
2.5
2
Ave
Min
1.5
Max
1
0.5
0
1
2.5
Data Rate
Figure 2-89:
108
3.2
RPT056_c2_89_051807
TX Pre-emphasis Test, dB vs. Data Rate
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TX Pre-Emphasis
TX Pre-emphasis Test, Percent by TXPREEMPHASIS Settings at 3.2 Gb/s
Virtex-5 GTP TX Pre-emphasis 2.5 Gb/s
(Temp = –40°C, 0°C, 100°C, VCC=VNOM ±5%)
70.00
Pre-emphasis (%)
60.00
Ave
Min
Max
50.00
40.00
30.00
20.00
10.00
0.00
0
1
2
3
4
5
TXPreEmph Setting
Figure 2-90:
6
7
RPT056_c2_95_052407
TX Pre-emphasis Test, by TXPREEMPHASIS Settings at 3.2 Gb/s
Virtex-5 GTP TX Pre-emphasis 3.2 Gb/s
(Temp = –40°C, 0°C, 100°C, VCC=VNOM ±5%)
0.00
Avg
Min
Max
Pre-emphasis (dB)
-0.50
-1.00
-1.50
-2.00
-2.50
-3.00
-3.50
0
1
2
3
4
TXPreEmph Setting
Figure 2-91:
5
6
7
RPT056_c2_91_052407
TX Pre-emphasis Test, dB by TXPREEMPHASIS Settings at 3.2 Gb/s
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Chapter 2: PMA Transmitter Characterization
Conclusion
The TX pre-emphasis tests demonstrate the effects on TX pre-emphasis across PVT, data
rate, and TX_PREEMPHASIS settings. These results are contained in Figure 2-76 to
Figure 2-91 and Table 2-53 to Table 2-60.
Figure 2-92 demonstrates a DCA scope picture of differing TX pre-emphasis settings. It
provides a visual reference for the TX pre-emphasis settings.
RPT056_c2_100_051807
Figure 2-92:
110
Qualitative Measurement of the Different Pre-emphasis Settings
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TX Termination DC Resistance
TX Termination DC Resistance
Test Description
This test measures the DC resistance of the TX pair.
Test Setup
TX termination resistance was measured across the TXP and TXN pair, using a highprecision DVM after setting RREF to 50Ω ± 1%, while also setting TERMINATION_CTRL
to OFF (00000) and TERMINATION_OVERLOAD to FALSE. Measurements were taken
across PVT as well as differing GTP transceiver locations. Figure 2-93, page 112 illustrates
the equipment used for this test. Temperature forcing equipment was used to precisely
control the temperature of the DUT. Figure 2-94 illustrates how Virtex-5 LXT devices
terminate both RX and TX.
Since this test was done at DC conditions, no REFCLKs were used. Table 2-63 reflects these
DC conditions.
Virtex-5 GTP transceivers support one common resistor calibration circuit block for
trimming the input termination resistor to match line impedance to minimize reflections.
Figure 2-94, page 113 shows the general block diagram for the resistor calibration macro. It
requires an external resistor that sets up a reference current for comparison. Current
through the external resistor was compared against the current through the internal
variable resistor R0, which was then adjusted accordingly by the finite state machine
(FSM).
An external precision resistor used was specified at 50Ω with 1% tolerance. Measured
resistance was 49.9 to 50.1Ω, less than 1%.
Table 2-63:
TX Termination Resistance PLL Parameters
Data Rate
(Gb/s)
PLL Freq
(GHz)
N/A
N/A
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
N/A
N/A
N/A
Post
Divider (1)
Oversample
N/A
N/A
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 2-64. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 2-64:
TX Termination Resistance Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
N/A
N/A
N/A
GTP_DUAL Attribute Settings
Attribute
Rate Affected
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Value
111
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Chapter 2: PMA Transmitter Characterization
Table 2-64:
TX Termination Resistance Test Settings (Continued)
GTP_DUAL Port Settings
Port
Rate Affected
Value
TERMINATION_CTRL[4:0]
N/A
00000
TERMINATION_OVRD
N/A
FALSE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 2-65.
Table 2-65:
TX Termination Resistance Test Conditions
Test Parameter
Test Value
Loopback Mode
None
Pattern
N/A
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 2-63)
8060A DVM
TXP
MGTAVTTTX
TXN
RPT056_c2_92a_052807
Figure 2-93:
112
Bench Test Setup for TX Termination Resistance Tests
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TX Termination DC Resistance
RX/TX
Termination
Override/Offset
Code
Other GTP_DUAL Tiles North of the Center
BRcal
MGTRREF
Package Pin
Comparator
MGTAVTTTX
RREF
External 50Ω
Precision Resistor
rCtrl[0:4]
Internal Resistor
Network
“Master” GTP_DUAL Tile
for Resistor Calibration
Override/Offset
Code
RX/TX
Termination
Other GTP_DUAL Tiles South of the Center
RPT056_c2_93_042207
Figure 2-94:
RX and TX Termination for GTP Transceivers in LXT Devices
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Chapter 2: PMA Transmitter Characterization
Results
Figure 2-95 and Table 2-66 provide the results from the TX DC resistance measurement
tests.
TX DC Resistance Measurements
Virtex-5 GTP TX Impedance, Differential, C-Grade
(VNOM, VNOM ± 5% V, Temp = 0°C, 25°C, 100°C)
200
180
Number of Data Points
160
140
120
100
80
60
40
20
0
87
89
91
93
95
97
99
101 103 105 107 109 111 113 115 117
DC Termination Resistance
Figure 2-95:
Table 2-66:
RPT056_c2_94_051807
TX Termination DC Resistance Histogram
TX Termination DC Resistance Summary
Parameter
TX Termination at DC
Min
Max
Average
Std Dev
Units
97.00
111.80
103.69
1.86
Ω
Conclusion
The TX Termination DC resistance was measured and data presented above in Figure 2-95
and Figure 2-66.
114
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Chapter 3
PMA Receiver Characterization
RX Stressed Eye Jitter Tolerance
Test Description
The RX stressed eye jitter tolerance test was designed to measure the PMA receiver’s
tolerance-to- jitter on the input data stream. It is a test to failure, meaning that the input eye
was continually deteriorated until a bit error occured. To accomplish this, a fixed input
amplitude was set, and sinusoidal jitter was added until the bit failure occured. A BER of
10E–12 was used as the standard.
Test Setup
RX stressed eye jitter tolerance was collected using Automated Test Equipment (ATE).
Figure 3-1, page 117 illustrates the equipment used for this test. The test was conducted
using a fixed input amplitude of 185 mV with a fixed 0.38 U.I. of Deterministic Jitter (DJ)
and a fixed 0.18 U.I. of Random Jitter (RJ). Sinusoidal Jitter (SJ) was then added to the link
until the link failed. The histograms reflect the amount of SJ added where the link last
correctly operated to 1E–12 BER. The RX channel was AC-coupled, and the RX
Equalization was set to 100%. A PRBS31 pattern was used.
Agilent ParBERT 13.5 Gb/s ATE equipment was used to measure RX jitter on all twelve
GTP transceivers simultaneously. A ParBERT analyzer was used to measure the BER of
each of the GTP TX outputs. Temperature control was achieved through forced-air
cooling/heating using a programmable Termionics unit. Twelve GTP transceiver channels
can be characterized simultaneously in a single pass.
The device was configured using JTAG. Power was supplied from eight programmable
power supplies through connectors on the side of the fixture.
High-speed connections from the device to the ParBERT were made through SMP and
SMA coax connectors. Blind-mate connectors were used to permit quick removal of the test
fixture. A low-profile, high-speed socket from Alta Nova was used to collect the data.
Two pairs of REFCLKs were used to clock the six GTP_DUAL tiles into two groups of three
tiles. The REFCLKs were sourced from a 3.2 Gb/s data generator using a clock pattern.
Table 3-1 shows the appropriate REFCLK frequency and PLL multiplier to create a proper
PLL frequency for each of the tested data rates.
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Chapter 3: PMA Receiver Characterization
Table 3-1:
RX Stressed Eye Jitter Tolerance Test PLL Parameters
REFCLK Freq PLL_DIVSEL_REF
PLL_DIVSEL_FB
and DIV
Post
Divider (1)
Data Rate
PLL Freq
Oversample
3.2 Gb/s
1.60 GHz
320 MHz
1
1*5=5
1
1
3.75 Gb/s
1.875 GHz
187.5 MHz
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software by Xilinx was used to configure the FPGA and set
the parameters of the GTP transceivers. Each transceiver was set up with the settings in
Table 3-2. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-2:
RX Stressed Eye Jitter Tolerance Test Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
3.2 Gb/s,
3.75 Gb/s
1: 10-bit datapath
INTDATAWIDTH
GTP_DUAL Attribute Settings
Attribute
Rate Affected
Value
3.2 Gb/s,
3.75 Gb/s
FALSE
OVERSAMPLE_MODE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 3-3.
Table 3-3:
RX Stressed Eye Jitter Tolerance Test Conditions
Test Parameter
Loopback Mode
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
116
Test Value
Various (see Table 3-1)
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RX Stressed Eye Jitter Tolerance
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_01_041907
Figure 3-1:
ATE Test Setup for RX Stressed Eye Jitter Tolerance Tests
(ATE Measurement)
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Chapter 3: PMA Receiver Characterization
Results
RX Stressed Eye Composite Jitter Tolerance, 80 MHz, 3.2 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
250
Number of Data Points
200
150
100
50
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
Total Jitter = 0.38 DJ + 0.18 RJ + U.I. SJ 80 MHz
Figure 3-2:
RPT056_c3_02_052307
RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 80 MHz, 3.2 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.38 U.I. of Deterministic Jitter (DJ) and 0.18
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.38 U.I. DJ + 0.18
U.I. RJ + measured U.I. of SJ.
Table 3-4:
RX Stressed Eye SJ Jitter Tolerance, 80 MHz, 3.2 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.403
0.676
0.598
0.049
U.I.
RX Stressed Eye Composite Jitter Tolerance, 20 MHz 3.2 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
Number of Data Points
200
150
100
50
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
Total Jitter = 0.38 DJ + 0.18 RJ + U.I. SJ 20 MHz
Figure 3-3:
RPT056_c3_03_052307
RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 20 MHz, 3.2 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.38 U.I. of Deterministic Jitter (DJ) and 0.18
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.38 U.I. DJ + 0.18
U.I. RJ + measured U.I. of SJ.
Table 3-5:
RX Stressed Eye SJ Jitter Tolerance, 20 MHz, 3.2 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
118
Min
Max
Average
Std Dev
Units
0.379
0.598
0.506
0.048
U.I.
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RX Stressed Eye Jitter Tolerance
RX Stressed Eye Composite Jitter Tolerance, 22 KHz, 3.2 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
500
Number of Data Points
400
300
200
100
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
Total Jitter = 0.38 DJ + 0.18 RJ + U.I. SJ 22 MHz
Figure 3-4:
28
30
32
34
RPT056_c3_04_052307
RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 22 KHz, 3.2 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.38 U.I. of Deterministic Jitter (DJ) and 0.18
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.38 U.I. DJ + 0.18
U.I. RJ + measured U.I. of SJ.
Table 3-6:
RX Stressed Eye SJ Jitter Tolerance, 22 KHz, 3.2 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
Min
Max
Average
Std Dev
Units
11.4
25.3
25.3
0
U.I.
RX Stressed Eye Composite Jitter Tolerance, 80 MHz, 3.75 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
30
Number of Data Points
25
20
15
10
5
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
Total Jitter = 0.44 DJ + 0.11 RJ + U.I. SJ 80 MHz
RPT056_c3_78_040708
Figure 3-5: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 80 MHz, 3.75 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.44 U.I. of Deterministic Jitter (DJ) and 0.11
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.44 U.I. DJ + 0.11
U.I. RJ + measured U.I. of SJ.
Table 3-7:
RX Stressed Eye SJ Jitter Tolerance, 80 MHz, 3.75 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.259
0.550
0.413
0.070
U.I.
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Chapter 3: PMA Receiver Characterization
RX Stressed Eye Composite Jitter Tolerance, 20 MHz 3.75 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
35
Number of Data Points
30
25
20
15
10
5
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
Total Jitter = 0.44 DJ + 0.11 RJ + U.I. SJ 20 MHz
RPT056_c3_79_040708
Figure 3-6: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 20 MHz, 3.75 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.44 U.I. of Deterministic Jitter (DJ) and 0.11
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.44 U.I. DJ + 0.11
U.I. RJ + measured U.I. of SJ.
Table 3-8:
RX Stressed Eye SJ Jitter Tolerance, 20 MHz, 3.75 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.165
0.470
0.355
0.068
U.I.
RX Stressed Eye Composite Jitter Tolerance, 22 KHz, 3.75 Gb/s Data Rate
Virtex-5 GTP RX Composite Jitter Tolerance
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
90
Number of Data Points
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
Total Jitter = 0.44 DJ + 0.11 RJ + U.I. SJ 22 MHz
28
30
32
34
RPT056_c3_80_040708
Figure 3-7: RX Stressed Eye, Histogram of SJ w/ Fixed DJ & RJ, 22 KHz, 3.75 Gb/s
Note: This histogram demonstrates the amount of Sinusoidal Jitter (SJ) added to 0.44 U.I. of Deterministic Jitter (DJ) and 0.11
U.I. of Random Jitter (RJ) in which the link last passed a 1E–12 BER. The Total Jitter for the channel would be 0.44 U.I. DJ + 0.11
U.I. RJ + measured U.I. of SJ.
Table 3-9:
RX Stressed Eye SJ Jitter Tolerance, 22 KHz, 3.75 Gb/s Data Rate
Parameter
RX Composite Jitter Tolerance
120
Min
Max
Average
Std Dev
Units
14.0
25.5
25.3
1.30
U.I.
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RX Stressed Eye Jitter Tolerance
RX Stressed Eye, Channel Stress
RPT056_c3_05_040708
Figure 3-8:
RX Stressed Eye, DCAj Channel Stress at 3.2 Gb/s
Conclusion
Table 3-10 provides a summary of the RX Stressed Eye SJ Jitter Tolerance tests.
Table 3-10:
RX Stressed Eye SJ Jitter Tolerance, Summary of Results
Parameter
RX Composite Jitter Tolerance.
3.2 Gb/s
RX Composite Jitter Tolerance.
3.75 Gb/s
SJ Freq
Min
Max
Average Std Dev
22 KHz
11.4
25.3
25.3
0
UI
20 MHz
0.379
0.598
0.506
0.048
UI
80 MHz
0.403
0.676
0.598
0.049
UI
22 KHz
14.0
25.5
25.3
1.30
UI
20 MHz
0.165
0.470
0.355
0.068
UI
80 MHz
0.259
0.550
0.413
0.070
UI
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Units
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Chapter 3: PMA Receiver Characterization
RX Sinusoidal Jitter Tolerance
Test Description
This test measured the tolerance to the sinusoidal jitter on the RX inputs.
Test Setup
RX sinusoidal jitter data was collected using ATE. Figure 3-9, page 124 illustrates the
equipment used for this test.
Agilent ParBERT 13.5 Gb/s ATE equipment was used to measure RX jitter on all twelve
GTPs simultaneously. A ParBERT analyzer was used to measure the BER of each of the
GTP TX outputs to a BER of 10E12. Temperature control was achieved through forced-air
cooling/heating using a programmable Thermionics unit. Twelve GTP channels were
characterized simultaneously in a single pass.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-11 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 3-11:
RX Sinusoidal Jitter Tolerance Test PLL Parameters
Data Rate
PLL Freq REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(GHz)
(MHz)
and DIV
Post
Divider (1)
Oversample
100 Mb/s (OS)
1.00
100
1
2 * 5 = 10
4
5
500 Mb/s (OS)
1.25
125
1
2 * 5 = 10
1
5
500 Mb/s
1.00
100
1
2 * 5 = 10
4
1
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
1.25 Gb/s
1.25
125
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.0 Gb/s
2.00
200
1
2 * 5 = 10
2
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
2.5 Gb/s
1.25
125
1
2 * 5 = 10
1
1
2.5 Gb/s
1.25
250
1
1*5=5
1
1
3.125 Gb/s
1.5625
156.25
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each transeiver was set up with the settings in
Table 3-12. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
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RX Sinusoidal Jitter Tolerance
Table 3-12:
RX Sinusoidal Jitter Tolerance Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 3-13.
Table 3-13:
RX Sinusoidal Jitter Tolerance Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
Junction Temperature
All 12 Locations
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
Various (see Table 3-11)
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Chapter 3: PMA Receiver Characterization
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
FR4
PCB
12
Pair
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_06_042007
Figure 3-9:
124
RX Sinusoidal Jitter Tolerance Tests
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RX Sinusoidal Jitter Tolerance
Results
RX Sinusoidal Jitter Tolerance Test Results for 100 Mb/s (Oversampled)
Virtex-5 GTP RX Jitter Tolerance OS 100 Mb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
450
Number of Data Points
400
350
300
250
200
150
100
50
0
0
0.1
0.3
0.5
0.7
RX Jitter Tolerance (U.I.)
Figure 3-10:
Table 3-14:
RPT056_c3_07_052307
RX SJ Tolerance, 100 Mb/s (OS)
RX Sinusoidal Jitter Test, 100 Mb/s (Oversampled)
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.300
0.500
0.498
0.020
UI
RX Sinusoidal Jitter Tolerance Test Results for 500 Mb/s (Oversampled)
Virtex-5 GTP RX Jitter Tolerance OS 500 Mb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
RX Jitter Tolerance (U.I.)
Figure 3-11:
Table 3-15:
0.9
1
RPT056_c3_08_052307
RX SJ Tolerance, 500 Mb/s (OS)
RX Sinusoidal Jitter Test, 500 Mb/s (Oversampled)
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.400
0.600
0.508
0.044
UI
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RX Sinusoidal Jitter Tolerance Test Results for 500 Mb/s
Virtex-5 GTP RX Jitter Tolerance 500 Mb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
RX Jitter Tolerance (U.I.)
Figure 3-12:
Table 3-16:
0.9
1
RPT056_c3_09_052307
RX SJ Tolerance, 500 Mb/s
RX Sinusoidal Jitter Test, 500 Mb/s
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.400
0.700
0.610
0.047
UI
RX Sinusoidal Jitter Tolerance Test Results for 1.00 Gb/s
Virtex-5 GTP RX Jitter Tolerance 1.0 Gb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
700
Number of Data Points
600
500
400
300
200
100
0
0
0.2
0.4
0.6
0.8
RX Jitter Tolerance (U.I.)
Figure 3-13:
Table 3-17:
RX SJ Tolerance, 1.00 Gb/s
RX Sinusoidal Jitter Test, 1.00 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
126
1
RPT056_c3_10_052307
Min
Max
Average
Std Dev
Units
0.400
0.800
0.718
0.114
UI
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RX Sinusoidal Jitter Tolerance
RX Sinusoidal Jitter Tolerance Test Results for 1.25 Gb/s
Virtex-5 GTP RX Jitter Tolerance 1.25 Gb/s (125 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
140
Number of Data Points
120
100
80
60
40
20
RX Jitter Tolerance (U.I.)
Figure 3-14:
Table 3-18:
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
RPT056_c3_11_040708
RX SJ Tolerance, 1.25 Gb/Sec
RX Sinusoidal Jitter Test, 1.25 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.42
0.80
0.652
0.094
UI
RX Sinusoidal Jitter Tolerance Test Results for 2.0 Gb/s, 100 MHz REFCLK
Virtex-5 GTP RX Jitter Tolerance 2.0 Gb/s (100 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
1200
Number of Data Points
1000
800
600
400
200
RX Jitter Tolerance (U.I.)
Figure 3-15:
Table 3-19:
1
0.95
0.9
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c3_12_052307
RX SJ Tolerance, 2.0 Gb/s, 100 MHz REFCLK
RX Sinusoidal Jitter Test, 2.00 Gb/s, 100 MHz REFCLK
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.461
0.510
0.510
0.005
UI
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RX Sinusoidal Jitter Tolerance Test Results for 2.488 Gb/s
Virtex-5 GTP RX Jitter Tolerance 2.488 Gb/s (155.25 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
RX Jitter Tolerance (U.I.)
Figure 3-16:
Table 3-20:
1
0.95
0.9
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c2_112_052307
RX SJ Tolerance, 2.488 Gb/s
RX Sinusoidal Jitter Test, 2.488 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.351
0.544
0.529
0.048
UI
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 62.5 MHz REFCLK
Virtex-5 GTP RX Jitter Tolerance 2.5 Gb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
2500
Number of Data Points
2000
1500
1000
500
RX Jitter Tolerance (U.I.)
Figure 3-17:
Table 3-21:
1
0.95
0.9
RPT056_c3_14_052307
RX SJ Tolerance, 2.5 Gb/s, 62.5 MHz REFCLK
RX Sinusoidal Jitter Test, 2.5 Gb/s, 62.5 MHz REFCLK
Parameter
RX Sinusoidal Jitter Tolerance
128
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
Min
Max
Average
Std Dev
Units
0.488
0.544
0.544
0.002
UI
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RX Sinusoidal Jitter Tolerance
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 100 MHz REFCLK
Virtex-5 GTP RX Jitter Tolerance 2.5 Gb/s (100 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
1000
900
Number of Data Points
800
700
600
500
400
300
200
100
RX Jitter Tolerance (U.I.)
Figure 3-18:
Table 3-22:
1
0.9
0.95
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c3_15_052307
RX SJ Tolerance, 2.5 Gb/s, 100 MHz REFCLK
RX Sinusoidal Jitter Test, 2.5 Gb/s, 100 MHz REFCLK
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.331
0.547
0.512
0.058
UI
RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 125 MHz REFCLK
Virtex-5 GTP RX Jitter Tolerance 2.5 Gb/s (62.5 MHz & 125 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
2500
Number of Data Points
2000
1500
1000
500
RX Jitter Tolerance (U.I.)
Figure 3-19:
Table 3-23:
1
0.9
0.95
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c3_16_052307
RX SJ Tolerance, 2.5 Gb/s, 125 MHz REFCLK
RX Sinusoidal Jitter Test, 2.5 Gb/s, 125 MHz REFCLK
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.488
0.544
0.544
0.002
UI
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RX Sinusoidal Jitter Tolerance Test Results for 2.50 Gb/s, 250 MHz REFCLK
Virtex-5 GTP RX Jitter Tolerance 2.5 Gb/s (250 MHz)
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
RX Jitter Tolerance (U.I.)
Figure 3-20:
Table 3-24:
1
0.9
0.95
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c3_17_052307
RX SJ Tolerance, 2.5 Gb/s, 250 MHz REFCLK
RX Sinusoidal Jitter Test, 2.5 Gb/s, 250 MHz REFCLK
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.475
0.564
0.563
0.007
UI
RX Sinusoidal Jitter Tolerance Test Results for 3.125 Gb/s
Virtex-5 GTP RX Jitter Tolerance 3.125 Gb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
900
Number of Data Points
800
700
600
500
400
300
200
100
RX Jitter Tolerance (U.I.)
Figure 3-21:
Table 3-25:
1
0.95
0.9
RPT056_c3_18_052307
RX SJ Tolerance, 3.125 Gb/s
RX Sinusoidal Jitter Test, 3.125 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
130
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
Min
Max
Average
Std Dev
Units
0.353
0.684
0.616
0.056
UI
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RX Sinusoidal Jitter Tolerance
RX Sinusoidal Jitter Tolerance Test Results for 3.2 Gb/s
Virtex-5 GTP RX Jitter Tolerance 3.2 Gb/s
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
500
450
Number of Data Points
400
350
300
250
200
150
100
50
RX Jitter Tolerance (U.I.)
Figure 3-22:
Table 3-26:
1
0.95
0.9
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0
RPT056_c3_19_052307
RX SJ Tolerance, 3.2 Gb/s
RX Sinusoidal Jitter Test, 3.2 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.431
0.702
0.564
0.045
UI
RX Sinusoidal Jitter Tolerance Test Results for 3.75 Gb/s
Virtex-5 GTP RX Jitter Tolerance 3.75 Gb/s
(Units = TT, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
1400
Number of Data Points
1200
1000
800
600
400
200
RX Jitter Tolerance (U.I.)
Figure 3-23:
Table 3-27:
1
0.95
0.9
0.85
0.800
0.750
0.700
0.650
0.600
0.550
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.05
0.000
0
RPT056_c3_81_040708
RX SJ Tolerance, 3.75 Gb/s
RX Sinusoidal Jitter Test, 3.75 Gb/s
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.337
0.649
0.482
0.049
UI
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Chapter 3: PMA Receiver Characterization
Conclusion
Table 3-28 shows a summary of the RX sinusoidal jitter tolerance.
Table 3-28:
RX Sinusoidal Jitter Tolerance Summary Results
Parameter
RX Sinusoidal
Jitter Tolerance
Rate
Min
Max
Average
Std Dev
Units
100 Mb/s (OS)
0.300
0.500
0.498
0.020
UI
500 Mb/s (OS)
0.400
0.600
0.508
0.044
UI
500 Mb/s
0.400
0.700
0.610
0.047
UI
1.0 Gb/s
0.400
0.800
0.718
0.114
UI
1.25 Gb/s
0.420
0.800
0.652
0.094
UI
2.0 Gb/s at 100 MHz
0.461
0.510
0.510
0.005
UI
2.488 Gb/s
0.351
0.544
0.529
0.048
UI
2.5 Gb/s at 62.5 MHz
0.488
0.544
0.544
0.002
UI
2.5 Gb/s at 100 MHz
0.331
0.547
0.512
0.058
UI
2.5 Gb/s at 125 MHz
0.488
0.544
0.544
0.002
UI
2.5 Gb/s at 250 MHz
0.475
0.564
0.563
0.007
UI
3.125 Gb/s
0.353
0.684
0.616
0.056
UI
3.2 Gb/s
0.431
0.702
0.564
0.045
UI
3.75 Gb/s
0.337
0.649
0.482
0.049
UI
RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Test Description
This test measured the tolerance to sinusoidal jitter (SJ) at the RX input with a clock-data
recovery (CDR) offset. This test is similar to the test described in “RX Sinusoidal Jitter
Tolerance,” page 122. This test applies sinusoidal jitter but also offsets the RX data from the
nominal data rate by ±1000 ppm.
Test Setup
RX sinusoidal jitter tolerance with clock data recovery (CDR) data was collected using
ATE. Figure 3-9, page 124 illustrates the equipment used for this test.
Agilent ParBERT 13.5 Gb/s ATE equipment was used to measure RX jitter on all twelve
GTPs simultaneously. A ParBERT analyzer was used to measure the BER of each of the
GTP TX outputs. Temperature control was achieved through forced-air cooling/heating
using a programmable Thermionics unit. Twelve GTP channels were characterized
simultaneously in a single pass.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-29 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
132
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Table 3-29:
RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
RX Sinusoidal Jitter Tolerance - CDR Freq. Offset Test, PLL Parameters
Data Rate
PLL Freq
(GHz)
REFCLK Freq
PLL_DIVSEL_FB
PLL_DIVSEL_REF
(MHz)
and DIV
Post
Divider (1)
Oversample
500 Mb/s (OS)
1.25
125
1
2 * 5 = 10
1
5
500 Mb/s
1.00
100
1
2 * 5 = 10
4
1
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
125
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each transceiver was set up with the settings in
Table 3-30. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-30: RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
All
1: 10-bit datapath
INTDATAWIDTH
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 500 Mb/s (OS)
FALSE
500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 3-31.
Table 3-31: RX Sinusoidal Jitter Tolerance with CDR Freq. Offset
Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
Junction Temperature
All 12 Locations
–40°C, 0°C, 100°C
Power Supplies
±5%
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Chapter 3: PMA Receiver Characterization
Table 3-31: RX Sinusoidal Jitter Tolerance with CDR Freq. Offset
Test Conditions (Continued)
Test Parameter
Test Value
Test Board
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
Various (see Table 3-29)
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_20_042007
Figure 3-24:
134
RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Tests
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RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
Results
RX SJ Tolerance with CDR Frequency Offset Results, 500 Mb/s (Oversampled)
Virtex-5 GTP RX ± 1000 ppm + SJ JT, OS 500 Mb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
RX ±1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-25:
Table 3-32:
0.7
0.8
RPT056_c3_21_052307
RX SJ Tolerance w/ CDR Frequency Offset, 500 Mb/s (OS)
RX SJ Tolerance with CDR Frequency Offset, 500 Mb/s (OS)
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.300
0.500
0.398
0.020
UI
RX SJ Tolerance with CDR Frequency Offset Results, 500 Mb/s
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 500 Mb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
RX ±1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-26:
Table 3-33:
0.7
0.8
RPT056_c3_22_052307
RX SJ Tolerance w/ CDR Frequency Offset, 500 Mb/s
RX SJ Tolerance with CDR Frequency Offset, 500 Mb/s (OS)
Parameter
RX Sinusoidal Jitter Tolerance
Min
Max
Average
Std Dev
Units
0.400
0.500
0.494
0.027
UI
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Chapter 3: PMA Receiver Characterization
RX SJ Tolerance with CDR Frequency Offset Results, 1.00 Gb/s
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 1.0 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1400
Number of Data Points
1200
1000
800
600
400
200
0
0
0.2
0.4
0.6
RX ±1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-27:
Table 3-34:
0.8
RPT056_c3_23_052307
RX SJ Tolerance w/ CDR Frequency Offset, 1.00 Gb/s
RX SJ Tolerance w/ CDR Frequency Offset, 1.00 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.400
0.600
0.540
0.098
UI
RX SJ Tolerance with CDR Freq. Offset Results, 2.0 Gb/s, 100 MHz REFCLK
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 2.00 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2500
Number of Data Points
2000
1500
1000
500
0
0.03
0.05
0.08
0.1
0.13
0.15
0.18
0.2
0.23
0.25
0.28
0.3
0.33
0.35
0.38
0.4
0.43
0.45
0.48
0.5
0.53
0.55
0.58
0.6
0.63
0.65
0.68
0.7
0.73
0.75
0.78
0.8
0
RX ± 1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
136
RPT056_c3_24_052307
Figure 3-28:
RX SJ Tolerance w/ CDR Frequency Offset, 2.0 Gb/s, 100 MHz REFCLK
Table 3-35:
RX SJ Tolerance w/ CDR Frequency Offset, 2.00 Gb/s, 100 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.335
0.480
0.472
0.017
UI
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RX Sinusoidal Jitter Tolerance with CDR Frequency Offset
RX SJ Tolerance with CDR Freq. Offset Results, 2.50 Gb/s, 62.5 MHz REFCLK
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 2.50 Gb/s (62.5 MHz), I-Grade
600
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
Number of Data Points
500
400
300
200
100
0
0.03
0.05
0.08
0.1
0.13
0.15
0.18
0.2
0.23
0.25
0.28
0.3
0.33
0.35
0.38
0.4
0.43
0.45
0.48
0.5
0.53
0.55
0.58
0.6
0.63
0.65
0.68
0.7
0.73
0.75
0.78
0.8
0
RX ± 1000 ppm + SJ JT 20 MHz Sinusoidal (UI) RPT056_c3_25_052307
Figure 3-29:
RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 62.5 MHz REFCLK
Table 3-36:
RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 62.5 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.317
0.592
0.486
0.039
UI
RX SJ Tolerance with CDR Freq. Offset Results, 2.50 Gb/s, 125 MHz REFCLK
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 2.50 Gb/s (125 MHz), I-Grade
800
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
Number of Data Points
700
600
500
400
300
200
100
0
0.03
0.05
0.08
0.1
0.13
0.15
0.18
0.2
0.23
0.25
0.28
0.3
0.33
0.35
0.38
0.4
0.43
0.45
0.48
0.5
0.53
0.55
0.58
0.6
0.63
0.65
0.68
0.7
0.73
0.75
0.78
0.8
0
RX ± 1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-30:
Table 3-37:
RPT056_c3_26_052307
RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 125 MHz REFCLK
RX SJ Tolerance w/ CDR Frequency Offset, 2.5 Gb/s, 125 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.372
0.592
0.522
0.039
UI
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Chapter 3: PMA Receiver Characterization
RX SJ Tolerance with CDR Frequency Offset Results, 3.2 Gb/s
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 3.20 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
450
Number of Data Points
400
350
300
250
200
150
100
50
0
0.03
0.05
0.08
0.1
0.13
0.15
0.18
0.2
0.23
0.25
0.28
0.3
0.33
0.35
0.38
0.4
0.43
0.45
0.48
0.5
0.53
0.55
0.58
0.6
0.63
0.65
0.68
0.7
0.73
0.75
0.78
0.8
0
RX ± 1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-31:
Table 3-38:
RPT056_c3_27_052307
RX SJ Tolerance w/ CDR Frequency Offset, 3.2 Gb/s
RX SJ Tolerance w/ CDR Frequency Offset, 3.2 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.317
0.730
0.524
0.083
UI
RX SJ Tolerance with CDR Frequency Offset Results, 3.75 Gb/s
Virtex-5 GTP RX ± 1000 ppm + SJ JT, 3.75 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
225
Number of Data Points
200
175
150
125
100
75
50
25
0
0.03
0.05
0.08
0.10
0.13
0.15
0.18
0.20
0.23
0.25
0.28
0.30
0.33
0.35
0.38
0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
0.73
0.75
0.78
0.80
0
RX ± 1000 ppm + SJ JT 20 MHz Sinusoidal (UI)
Figure 3-32:
Table 3-39:
138
RPT056_c3_82_041008
RX SJ Tolerance w/ CDR Frequency Offset, 3.75 Gb/s
RX SJ Tolerance w/ CDR Frequency Offset, 3.75 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
RX SJ Tolerance with CDR Freq. Offset
0.318
0.736
0.531
0.101
UI
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RX CDR Frequency Tolerance
Conclusion
Table 3-40 shows a summary of the RXsinusoidal jitter tolerance with CDR frequency
offset test results.
Table 3-40:
RX SJ Tolerance with CDR Frequency Offset Summary Results
Parameter
Rate
RX SJ Tolerance with
CDR Freq offset
Min
Max
Average
Std Dev
Units
500 Mb/s (OS)
0.300
0.500
0.398
0.020
UI
500 Mb/s
0.400
0.500
0.494
0.027
UI
1.0 Gb/s
0.400
0.600
0.540
0.098
UI
2.0 Gb/s at 100M
0.335
0.480
0.472
0.017
UI
2.5 Gb/s at 62.5M
0.317
0.592
0.486
0.046
UI
2.5 Gb/s at 125 M
0.372
0.592
0.522
0.039
UI
3.2 Gb/s
0.317
0.730
0.524
0.083
UI
3.75 Gb/s
0.318
0.736
0.531
0.101
UI
RX CDR Frequency Tolerance
Test Description
In a typical application, the TX and RX channels use separate clock domains resulting in
frequency differences between the TX and RX sides. This test measured the BER with
various fixed data rates on the TX channel while increasing/decreasing the data rate on the
RX channel.
Test Setup
The ATE system normally operates with the TX and RX channels operating at the same
data rate (synchronously). For the RX CDR frequency tolerance test, the system was
programmed to use a fixed data rate for the TX and a differing data rate for the RX channel.
Agilent ParBERT 13.5 Gb/s ATE equipment was used to measure RX jitter on all twelve
GTPs simultaneously. A ParBERT analyzer was used to measure the BER of each of the
GTP TX outputs. Temperature control was achieved through forced-air cooling/heating
using a programmable Thermionics unit. Twelve GTP channels were characterized
simultaneously in a single pass.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-41 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 3-41:
RX CDR Offset Test PLL Parameters
PLL_DIVSEL_FB
Post Divider (1)
and DIV
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
1.25
1.25
125
1
2 * 5 = 10
2
1
2.0
1.00
100
1
2 * 5 = 10
1
1
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Oversample
139
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Chapter 3: PMA Receiver Characterization
Table 3-41:
RX CDR Offset Test PLL Parameters (Continued)
PLL_DIVSEL_FB
Post Divider (1)
and DIV
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
2.488
1.244
155.52
1
2*4=8
1
1
2.5
1.25
62.5
1
4 * 5 = 20
1
1
2.5
1.25
125
1
2 * 5 = 10
1
1
2.5
1.25
250
1
1*5=5
1
1
3.125
1.5625
156.25
1
2 * 5 = 10
1
1
3.2
1.60
320
1
1*5=5
1
1
3.75
1.875
187.5
1
2 * 5 = 10
1
1
Oversample
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-42. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-42:
RX CDR Offset Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTPs for this test. Conditions relevant to
this test are contained in Table 3-43
Table 3-43:
RX CDR Offset Test Conditions
Test Parameter
Loopback Mode
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, FS, SF
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
140
Test Value
Virtex-5 LXT FF1136 Test Fixture
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RX CDR Frequency Tolerance
Table 3-43:
RX CDR Offset Test Conditions (Continued)
Test Parameter
Test Value
FR-4 Length
3.25 inches
REFCLK and PLL Rates
Various (see Table 3-41)
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
FR4
PCB
12
Pair
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_28_042107
Figure 3-33:
ATE Test Setup for RX CDR Offset Tests
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Chapter 3: PMA Receiver Characterization
Results
RX CDR Offset at 1.25 Gb/s, 125 MHz REFCLK
Virtex-5 GTP CDR Offset, 1.25 Gb/s, I-Grade
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-34:
Table 3-44:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_29_052307
RX CDR Offset at 1.25 Gb/s, C and I Grade, 125 MHz REFCLK
RX CDR Offset at 1.25 Gb/s Data Rate, 125 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–1600
–6400
–5362
1131
ppm
RX CDR Offset, Plus
1600
6400
3817
1218
ppm
RX CDR Offset at 2.0 Gb/s, 100 MHz REFCLK
Virtex-5 GTP CDR Offset, 2.00 Gb/s, I-Grade
(Units = TT, SF, FF, FS, SS, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-35:
Table 3-45:
7000
6000
RPT056_c3_30_052307
RX CDR Offset at 2.0 Gb/s, C and I Grade, 100 MHz REFCLK
RX CDR Offset at 2.0 Gb/s Data Rate, 100 MHz REFCLK
Parameter
142
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–2000
–6900
–6045
570
ppm
RX CDR Offset, Plus
2000
7000
4011
923
ppm
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RX CDR Frequency Tolerance
RX CDR Offset at 2.488 Gb/s, 155.5 MHz REFCLK
Virtex-5 GTP CDR Offset, 2.488 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1200
Number of Data Points
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-36:
Table 3-46:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_31_052307
RX CDR Offset at 2.488 Gb/s, C and I Grade, 155.5 MHz REFCLK
RX CDR Offset at 2.488 Gb/s Data Rate, 155.5 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–3215
–8038
–7121
1131
ppm
RX CDR Offset, Plus
2411
8841
6450
1470
ppm
RX CDR Offset at 2.5 Gb/s, 62.5 MHz REFCLK
Virtex-5 GTP CDR Offset, 2.50 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-37:
Table 3-47:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_32_052307
RX CDR Offset at 2.5 Gb/s, C and I Grade, 62.5 MHz REFCLK
RX CDR Offset at 2.5 Gb/s Data Rate, 62.5 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–3000
–6900
–6007
540
ppm
RX CDR Offset, Plus
2000
7000
3886
1121
ppm
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Chapter 3: PMA Receiver Characterization
RX CDR Offset at 2.5 Gb/s, 125 MHz REFCLK
Virtex-5 GTP CDR Offset, 2.50 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-38:
Table 3-48:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_33_052307
RX CDR Offset at 2.5 Gb/s, C and I Grade, 125 MHz REFCLK
RX CDR Offset at 2.5 Gb/s Data Rate, 125 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–3000
–6900
–6015
527
ppm
RX CDR Offset, Plus
2000
7000
3835
1125
ppm
RX CDR Offset at 2.5 Gb/s, 250 MHz REFCLK
Virtex-5 GTP CDR Offset, 2.50 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-39:
Table 3-49:
7000
6000
5000
RPT056_c3_34_052307
RX CDR Offset at 2.5 Gb/s, C and I Grade, 250 MHz REFCLK
RX CDR Offset at 2.5 Gb/s Data Rate, 250 MHz REFCLK
Parameter
144
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–3200
–6400
–6301
414
ppm
RX CDR Offset, Plus
2000
6400
3640
1015
ppm
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RPT056 (v1.1) May 20, 2008
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RX CDR Frequency Tolerance
RX CDR Offset at 3.125 Gb/s, 156.25 MHz REFCLK
Virtex-5 GTP CDR Offset, 3.125 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-40:
Table 3-50:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_35_052307
RX CDR Offset at 3.125 Gb/s, C and I Grade, 156.25 MHz REFCLK
RX CDR Offset at 3.125 Gb/s Data Rate, 156.25 MHz REFCLK, Minus
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–1920
–6400
–6102
692
ppm
RX CDR Offset, Plus
1920
7040
4029
1260
ppm
RX CDR Offset at 3.2 Gb/s, 320 MHz REFCLK
Virtex-5 GTP CDR Offset, 3.20 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1400
Number of Data Points
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-41:
Table 3-51:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_36_052307
RX CDR Offset at 3.2 Gb/s, C and I Grade, 320 MHz REFCLK
RX CDR Offset at 3.2 Gb/s Data Rate, 320 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–3000
–6900
–4472
1105
ppm
RX CDR Offset, Plus
2000
7000
2801
786
ppm
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Chapter 3: PMA Receiver Characterization
RX CDR Offset at 3.75 Gb/s, 187.5 MHz REFCLK
Virtex-5 GTP CDR Offset, 3.75 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
1400
Number of Data Points
1200
1000
800
600
400
200
CDR Offset (ppm)
Figure 3-42:
Table 3-52:
7000
6000
5000
4000
3000
2000
1000
0
-1000
-2000
-3000
-4000
-5000
-6000
-7000
0
RPT056_c3_82_041008
RX CDR Offset at 3.75 Gb/s, C and I Grade, 187.5 MHz REFCLK
RX CDR Offset at 3.2 Gb/s Data Rate, 320 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX CDR Offset, Minus
–2000
–6900
–3890
934
ppm
RX CDR Offset, Plus
2000
5000
2665
759
ppm
Conclusion
Table 3-53 provides a summary of the RX CDR offset test results where the CDR offset was
minus PPM. Table 3-54 provides a summary of the RX CDR offset test results where the
CDR offset was plus PPM.
Table 3-53:
RX CDR Offset Test Summary Results, Minus
Parameter
RX CDR Offset,
Minus
146
Rate
Min
Max
Average
Std Dev
Units
1.25 Gb/s
–1600
–6400
–5362
1331
ppm
2.0 Gb/s at 100 MHz
–2000
–6900
–6045
570
ppm
2.488 Gb/s
–3215
–8038
–7121
1131
ppm
2.5 Gb/s at 62.5 MHz
–3000
–6900
–6007
540
ppm
2.5 Gb/s at 125 MHz
–3000
–6900
–6015
527
ppm
2.5 Gb/s at 250 MHz
–3200
–6400
–6301
414
ppm
3.125 Gb/s
–1920
–6400
–6102
692
ppm
3.2 Gb/s
–3000
–6900
–4473
1105
ppm
3.75 Gb/s
–2000
–6900
–3890
934
ppm
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Table 3-54:
RX Input Sensitivity
RX CDR Offset Test Summary Results, Plus
Parameter
RX CDR Offset,
Plus
Rate
Min
Max
Average
Std Dev
Units
1.25 Gb/s
1600
6400
3817
1218
ppm
2.0 Gb/s at 100 MHz
2000
7000
4011
923
ppm
2.488 Gb/s
2411
8841
6450
1470
ppm
2.5 Gb/s at 62.5 MHz
2000
7000
3886
1121
ppm
2.5 Gb/s at 125 MHz
2000
7000
3835
1125
ppm
2.5 Gb/s at 250 MHz
2000
6400
3640
1015
ppm
3.125 Gb/s
1920
7040
4029
1260
ppm
3.2 Gb/s
2000
7000
2801
786
ppm
3.75 Gb/s
2000
5000
2665
759
ppm
RX Input Sensitivity
Test Description
This test measured the receiver’s input sensitivity on the data input of the PMA RX side.
Test Setup
RX input sensitivity data was collected using ATE. Figure 3-43 illustrates the equipment
used for this test. The RX input sensitivity test was designed to measure a given amplitude
with a BER limit at 1E–12. To accomplish this, the test sweeps across the RX input
amplitude starting at 400 mV and decreasing in 15 mV steps until failure occurs. The
histograms record the last step in which the RX input was error-free for that particular
measurement. Measurements were made across the conditions listed in Table 3-57.
ATE was used to measure RX input sensitivity on all 12 GTP transceivers simultaneously.
A ParBERT analyzer was used to measure the BER of each of the GTP RX inputs. The ATE
measures these errors and records them as a set of histogram points across the data rates
tested.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-55 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 3-55:
RX Input Sensitivity Test PLL Parameters
Data Rate
PLL_DIVSEL_FB
PLL Freq REFCLK Freq
Post Divider (1) Oversample
PLL_DIVSEL_REF
and DIV
(GHz)
(MHz)
100 Mb/s (OS)
1.00
100
1
2 * 5 = 10
4
5
500 Mb/s (OS)
1.25
125
1
2 * 5 = 10
1
5
500 Mb/s
1.00
100
1
2 * 5 = 10
4
1
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
1.25 Gb/s
1.25
125
1
2 * 5 = 10
2
1
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Chapter 3: PMA Receiver Characterization
Table 3-55:
RX Input Sensitivity Test PLL Parameters (Continued)
Data Rate
PLL_DIVSEL_FB
PLL Freq REFCLK Freq
Post Divider (1) Oversample
PLL_DIVSEL_REF
and DIV
(GHz)
(MHz)
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
1.5625
156.25
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
3.125 Gb/s
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-56. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-56:
RX Input Sensitivity Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 3-57.
Table 3-57:
RX Input Sensitivity Test Conditions
Test Parameter
Loopback Mode
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
148
Test Value
Various (see Table 3-55)
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RX Input Sensitivity
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_37_042107
Figure 3-43:
ATE Test Setup for RX Input Sensitivity Tests
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Chapter 3: PMA Receiver Characterization
Results
RX Input Sensitivity at 100 Mb/s Using Oversampling
Virtex-5 GTP RX Sensitivity (DIFF), 0.100 Gb/s OS
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
400
Number of Data Points
350
300
250
200
150
100
50
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
RPT056_c3_38_052307
Figure 3-44: RX Input Sensitivity at 100 Mb/s, C and I Grade, Oversampled
Table 3-58:
RX Input Sensitivity at 100 Mb/s Data Rate, Oversampled
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
15
120
60
18
mV
RX Input Sensitivity at 500 Mb/s Using Oversampling
Virtex-5 GTP RX Sensitivity (DIFF), 0.500 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
350
Number of Data Points
300
250
200
150
100
50
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
RPT056_c3_39_052307
Figure 3-45: RX Input Sensitivity at 500 Mb/s, C and I Grade, Oversampled
Table 3-59:
TX Generation Measurement at 500 Mb/s Date Rate, Oversampled
Parameter
RX Input Sensitivity
150
Min
Max
Average
Std Dev
Units
15
105
60
18
mV
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RX Input Sensitivity
RX Input Sensitivity at 500 Mb/s
Virtex-5 GTP RX Sensitivity (DIFF), 0.500 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
350
Number of Data Points
300
250
200
150
100
50
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-46:
Table 3-60:
RPT056_c3_40_052407
RX Input Sensitivity at 500 Mb/s, C and I Grade
RX Input Sensitivity at 500 Mb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
15
105
60
18
mV
RX Input Sensitivity at 1.00 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 1.00 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
350
Number of Data Points
300
250
200
150
100
50
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-47:
Table 3-61:
RPT056_c3_41_052407
RX Input Sensitivity at 1.00 Gb/s, C and I Grade
RX Input Sensitivity at 1.00 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
15
120
60
18
mV
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Chapter 3: PMA Receiver Characterization
RX Input Sensitivity at 1.25 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 1.25 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
700
Number of Data Points
700
600
500
400
300
200
100
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-48:
Table 3-62:
RPT056_c2_141_052407
RX Input Sensitivity at 1.25 Gb/s, C and I Grade
RX Input Sensitivity at 1.25 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
30
135
60
18
mV
RX Input Sensitivity at 2.0 Gb/s, 100 MHz REFCLK
Virtex-5 GTP RX Sensitivity (DIFF), 2.0 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
200
180
Number of Data Points
160
140
120
100
80
60
40
20
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-49:
Table 3-63:
RX Input Sensitivity at 2.0 Gb/s, C and I Grade, 100 MHz REFCLK
RX Input Sensitivity at 2.0 Gb/s Data Rate
Parameter
RX Input Sensitivity
152
RPT056_c3_43_05240
Min
Max
Average
Std Dev
Units
30
135
60
18
mV
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RX Input Sensitivity
RX Input Sensitivity at 2.488 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 2.488 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-50:
Table 3-64:
RPT056_c3_44_052407
RX Input Sensitivity at 2.488 Gb/s, C and I Grade
RX Input Sensitivity at 2.488 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
30
135
75
18
mV
RX Input Sensitivity at 2.5 Gb/s, 125 MHz REFCLK
Virtex-5 GTP RX Sensitivity (DIFF), 2.5 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-51:
Table 3-65:
RPT056_c3_45_052407
RX Input Sensitivity at 2.5 Gb/s, C and I Grade, 125 MHz REFCLK
RX Input Sensitivity at 2.5 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
30
135
75
18
mV
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Chapter 3: PMA Receiver Characterization
RX Input Sensitivity at 3.125 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 3.125 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
900
Number of Data Points
800
700
600
500
400
300
200
100
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-52:
Table 3-66:
RPT056_c3_46_052407
RX Input Sensitivity at 3.125 Gb/s, C and I Grade
RX Input Sensitivity at 3.125 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
30
135
75
18
mV
RX Input Sensitivity at 3.2 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 3.2 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
180
Number of Data Points
160
140
120
100
80
60
40
20
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-53:
Table 3-67:
RX Input Sensitivity at 3.2 Gb/s, C and I Grade
RX Input Sensitivity at 3.2 Gb/s Data Rate
Parameter
RX Input Sensitivity
154
RPT056_c3_47_052407
Min
Max
Average
Std Dev
Units
15
120
75
18
mV
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RX Input Sensitivity
RX Input Sensitivity at 3.75 Gb/s
Virtex-5 GTP RX Sensitivity (DIFF), 3.75 Gb/s
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
900
800
Number of Data Points
700
600
500
400
300
200
100
0
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210
RX Sensitivity, mV Differential
Figure 3-54:
Table 3-68:
RPT056_c3_84_041108
RX Input Sensitivity at 3.75 Gb/s, C and I Grade
RX Input Sensitivity at 3.75 Gb/s Data Rate
Parameter
RX Input Sensitivity
Min
Max
Average
Std Dev
Units
45
165
92.28
18.73
mV
Conclusion
Table 3-69 provides a summary of the RX input sensitivity results.
Table 3-69:
RX Input Sensitivity Summary Results
Parameter
RX Input
Sensitivity
Rate
Min
Max
Average
Std Dev
Units
100 Mb/s (OS)
15
120
60
18
mV
500 Mb/s (OS)
15
105
60
18
mV
500 Mb/s
15
105
60
18
mV
1.0 Gb/s
15
120
60
18
mV
1.25 Gb/s
30
135
60
18
mV
2.0 Gb/s 100 MHz REFCLK
30
135
60
18
mV
2.488 Gb/s
30
135
75
18
mV
2.5 Gb/s 125 MHz REFCLK
30
135
75
18
mV
3.125 Gb/s
30
135
75
18
mV
3.2 Gb/s
15
120
75
18
mV
3.75 Gb/s
45
165
92.28
18.73
mV
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Chapter 3: PMA Receiver Characterization
RX Equalization
Test Description
The purpose of this test was to characterize the effectiveness of the GTP receiver equalizer
to filter out the channel-loss-related ISI component of deterministic jitter.
Test Setup
Two different setups were used for this test. The first was an RX bench setup illustrated in
Figure 3-55, page 158. The resultant data set for the RX bench setup is contained in
Table 3-73 and Table 3-74.
The second setup was the ATE setup illustrated in Figure 3-56, page 159. The resultant data
set for the ATE setup is contained in Figure 3-57 to Figure 3-62 and Table 3-75 to Table 3-79.
RX Equalization Bench Setup
The RX equalization bench test setup, shown in Figure 3-55, consists of the Agilent N4901B
Serial J-BERT with interference channel option, Xilinx Virtex-5 ML523 Characterization
Platform, Agilent 86100A DCA-J scope, power supplies, SMA cables, and a PC. J-BERT
data outputs were connected to the GTP DUT RX through the interference channel. The
Agilent J-BERT interference channel has several FR-4 trace length options that can be
inserted in the DUT’s receive data path. The DUT was placed in the RX-to-TX loopback
mode. Data errors were checked back at the J-BERT error detector. The Agilent DCA-J was
used to measure the passing traces’ amplitude loss and ISI jitter components.
The GTP RX equalizer was tested for each of the possible equalization settings and when
the equalization was disabled. The Agilent Serial J-BERT generates data that was passed
through the selected trace length from the interference channel. Data was looped from RX
to TX through the GTP under test, and bit errors were monitored back at the J-BERT error
detector. For each of the equalization settings, interference channel trace length was
increased in 4-inch steps until bit errors were first detected. When errors were detected, the
interference channel length was reverted back to the previous passing length, and the test
was run for fifteen minutes to make sure the link was solid and was passing with zero
errors. The test was repeated for each of the possible equalization settings and for the
equalizer disabled. The whole set of tests was repeated at one high-end, one middle-range,
and one lower-end data range frequency.
Once the passing trace length has been established for each case, trace length dB loss was
measured at one-half the frequency of each data rate tested. In addition, the ISI-related DJ
component of each passing trace length at each tested data rate was measured using an
Agilent DCA-J communications analyzer. CJPAT data pattern was used, which DCA-J can
easily and accurately resolve into jitter components. For lower data rate tests, additional
FR-4 trace length was required and added externally to the J-BERT interference channel
trace lengths using the Xilinx Nelco Quad Serial Loop board (NQSL).
RX Equalization ATE Setup
The RX equalization ATE setup, shown in Figure 3-56 measures the composite jitter
tolerance at various rates with various settings of the RX equalization using the Agilent
ParBERT. A specific amount of DJ and RJ were injected into the system and the resultant
composite jitter tolerance was measured.
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RX Equalization
A REFCLK was used to clock the GTP transceivers. The REFCLK was sourced from a
3.2 Gb/s data generator using a clock pattern. Table 3-70 shows the appropriate REFCLK
frequency, and PLL multiplier to create a proper PLL frequency for each of the tested data
rates
Table 3-70:
RX Equalization Test PLL Settings
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
PLL_DIVSEL_FB
Post Divider (1)
and DIV
1.25
1.25
125
1
2 * 5 = 10
2
1
2.5
1.25
100
2
5 * 5 = 25
1
1
2.5
1.25
125
1
5 * 4 = 20
1
1
2.5
1.25
250
1
2 * 5 = 10
1
1
3.125
1.5625
156.25
1
2 * 5 = 10
1
1
3.2
1.60
320
1
1*5=5
1
1
3.75
1.875
187.5
1
2 * 5 = 10
1
1
Oversample
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-71. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-71:
RX Equalization Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
N/A
N/A
N/A
GTP_DUAL Attribute Settings
Attribute
Rate Affected
Value
All
0 (enabled)
All
00, 01, 10, 11
All
0000
RXENEQB0
RXENEQB1
RXEQMIX0[1:0]
RXEQMIX1[1:0]
RXEQPOLE0[3:0]
RXEQPOLE1[3:0]
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Chapter 3: PMA Receiver Characterization
Various conditions were used to characterize the GTP transceivers. Conditions relevant to
this test are contained in Table 3-72.
Table 3-72:
RX Equalization Test Conditions
Test Parameter
Test Value
Loopback Mode
Fabric Loopback
Pattern
CJPAT, PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
ML523,
Test Boards
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
4.25 inches, 3.25 inches respectively
REFCLK and PLL Rates
Various (see Table 3-70)
IEEE-488 (GPIB)
Agilent
8648C
Signal
Generator
FR4
PCB
P/N
Pair
A
B
C
Rotary
Relay x2
A
SMAs
P/N
Pair
120
GTP_DUAL X0Y5
P/N
Pair
B
C
SMAs
Agilent
N4901B
Serial
BERT
PC
Splitter
FR4
PCB
Rotary
Relay x2
LPT2
PC
4
CLK
Agilent
6624A
Power
Supplies
122
GTP_DUAL X0Y0
D
P/N
Pair
D
FPGA
DUT
Xilinx Virtex-5 ML523 Characterization Platform
Agilent
34999B
Switch
Control
System
P/N
Pair
RPT056_c2_101_052107
Figure 3-55: RX Equalization Bench Setup
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RX Equalization
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_48_042107
Figure 3-56:
RX Equalization ATE Test Setup
Results
Test results for the bench testing are reported as a table of tested data rates, device types,
environmental/supply conditions, passing trace length, dB loss at one half the tested data
rate, and the DJ contribution of the selected passing trace length. These can be found in
Table 3-73. Additionally, Table 3-74 reports the results from a stress test run for 15 minute
using a CJPAT pattern and the specified FR-4 trace length.
Test results for the ATE testing are reported as a set of histograms and tables of total jitter
at 3.2 Gb/s rate and across various RX equalizer settings. Data is reported with 0.4 UI of DJ
and 0.17 of RJ added. Additionally, the RX equalizer was swept across 0%, 25%, 37.5%, 50%
and 67.5% equalization.
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Chapter 3: PMA Receiver Characterization
RX Equalization Test, Stress Test
Table 3-73:
Data Rate
1.25 Gb/s
2.5 Gb/s
3.2 Gb/s
3.75 Gb/s
RX Equalization Test Results
PLL Freq
1.25 GHz
1.25 GHz
1.60 GHz
1.87 GHz
RXENEQB0/1
Max Passed Min Passed
ISI (UI),
dB Loss
RXEQMIX0/1[1:0] (1) Trace Length Trace Length From DCA-J
(1/2 Data Rate)
(in)
(in)
@ PRBS7
1
00
76
69
0.34
–7.45
0
00
88
80
0.49
–9.68
0
01
84
76
0.43
–8.87
0
10
84
76
0.43
–8.87
0
11
92
88
0.55
–10.87
1
00
36
29
0.14
–6.09
0
00
48
44
0.38
–10.52
0
01
40
44
0.29
–9.42
0
10
40
36
0.22
–8.31
0
11
56
52
0.55
–12.73
1
00
20
16
0.14
–6.11
0
00
36
32
0.45
–10.90
0
01
32
24
0.30
–8.52
0
10
28
20
0.20
–7.03
0
11
44
40
0.63
–13.15
1
00
16
9
0.08
–4.08
0
00
32
24
0.36
–9.50
0
01
24
24
0.36
–9.50
0
10
20
16
0.19
–6.47
0
11
36
32
0.60
–12.15
Notes:
1. RXEQMIX0[1:0] and RXEQMIX1[1:0] set the wideband/high-pass mix ratio for the RX equalization circuit. Please see UG196,
Virtex-5 RocketIO GTP Transceiver User Guide, for details on their setting.
Table 3-74:
RX Stress Test, Various Rates, Various FR-4 Trace Lengths
Data Rate
PLL Freq
REFCLK
FR-4
RXENEQB0/1 RXEQMIX0/1[1:0] (1) Pattern
Conditions
Freq
Length
1.25 Gb/s
1.25 GHz
125 MHz
0
11
CJPAT
30 in
2.5 Gb/s
1.25 GHz
100 MHz
0
11
CJPAT
45 in
2.5 Gb/s
1.25 GHz
250 MHz
0
11
CJPAT
45 in
3.2 Gb/s
1.60 GHz
156.25
MHz
0
11
CJPAT
90 in
Per
Table 3-72
Time
Result
15 min
Passed
15 min
Passed
15 min
Passed
15 min
Passed
Notes:
1. RXEQMIX0[1:0] and RXEQMIX1[1:0] set the wideband/high-pass mix ratio for the RX equalization circuit. Please see UG196,
Virtex-5 RocketIO GTP Transceiver User Guide, for details on their setting.
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RX Equalization
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer Off
Virtex-5 GTP (Equalizer OFF) Composite Jitter Tolerance
(VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
160
Number of Data Points
140
120
100
80
60
40
20
Figure 3-57:
Table 3-75:
1
0.95
0.9
0.8
Total Jitter = 0.4 DJ + 0.17 RJ + SJ
0.85
0.7
0.75
0.6
0.65
0.55
0.5
0.4
0.45
0.3
0.35
0.2
0.25
0.15
0.1
0
0.05
0
RPT056_c3_50_052407
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = Off
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = Off
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.000
0.319
0.213
0.085
UI
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 25%
Virtex-5 GTP RX (Equalizer 25%) Composite Jitter Tolerance
(VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
160
Number of Data Points
140
120
100
80
60
40
20
Figure 3-58:
Table 3-76:
1
0.95
0.9
0.8
0.85
0.7
Total Jitter = 0.4 DJ + 0.17 RJ + SJ
0.75
0.65
0.6
0.55
0.5
0.4
0.45
0.3
0.35
0.25
0.2
0.15
0.1
0
0.05
0
RPT056_c3_51_052407
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 25%
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 25%
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.171
0.421
0.277
0.052
UI
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Chapter 3: PMA Receiver Characterization
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 37%
Virtex-5 GTP RX (Equalizer 37%) Composite Jitter Tolerance
(VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
90
Number of Data Points
80
70
60
50
40
30
20
10
Table 3-77:
1
0.95
0.9
0.8
Total Jitter = 0.4 DJ + 0.17 RJ + SJ
Figure 3-59:
0.85
0.7
0.75
0.6
0.65
0.55
0.5
0.4
0.45
0.3
0.35
0.2
0.25
0.15
0.1
0
0.05
0
RPT056_c3_52_052407
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 37%
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 37%
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.205
0.533
0.330
0.075
UI
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 50%
Virtex-5 GTP RX (Equalizer 50%) Composite Jitter Tolerance
(VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
100
90
Number of Data Points
80
70
60
50
40
30
20
10
Figure 3-60:
Table 3-78:
162
1
0.95
0.9
0.8
0.85
0.7
Total Jitter = 0.4 DJ + 0.17 RJ + SJ
0.75
0.65
0.6
0.55
0.5
0.4
0.45
0.3
0.35
0.25
0.2
0.15
0.1
0
0.05
0
RPT056_c3_53_042107
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 50%
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 50%
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.222
0.610
0.445
0.080
UI
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RX Equalization
RX Equalization Test, Composite Jitter Tolerance at 3.2 Gb/s, RX Equalizer 62%
Virtex-5 GTP RX (Equalizer 62%) Composite Jitter Tolerance
(VCC = VNOM, VNOM ± 5% V, Temp = –40°, 0°C, 100°C)
100
90
Number of Data Points
80
70
60
50
40
30
20
10
Total Jitter = 0.4 DJ + 0.17 RJ + SJ
Figure 3-61:
Table 3-79:
1
0.9
0.95
0.8
0.85
0.7
0.75
0.6
0.65
0.5
0.55
0.4
0.45
0.3
0.35
0.2
0.25
0.1
0.15
0
0.05
0
RPT056_c2_152_052407
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 62%
RX Equalization Test, CJ Tolerance at 3.2 Gb/s, RX EQ = 62%
Parameter
Min
Max
Average
Std Dev
Units
TJ, Total Jitter
0.330
0.660
0.523
0.073
UI
RX Equalization Test, Mean Sinusoidal Jitter Tolerance vs.
RX Equalizer Settings, 3.125 Gb/s
Virtex-5 GTP RX Equalizer Mean SJ Tolerance vs. Equalizer Setting
(In Addition to DJ = 0.4 UI, RJ = 0.17 UI, SJ = As Noted)
0.8
MEAN
0.7
Jitter Tolerance SJ (UI)
MIN
0.6
MAX
0.5
0.4
0.3
0.2
0.1
0
25%
37.5
50%
RX Equalizer High Frequency %
62.5
RPT056_c3_55_052407
Figure 3-62:
RX Equalization Test, Mean SJ Tolerance at 3.2 Gb/s vs. RX EQ Settings
Table 3-80:
RX Equalization Test, Mean SJ Tolerance at 3.2 Gb/s vs. RX EQ Settings
Parameter
Min
Max
Mean
Std Dev
Units
TJ, Total Jitter, 0% RX EQ
0.000
0.319
0.173
0.095
UI
TJ, Total Jitter, 25% RX EQ
0.171
0.421
0.274
0.052
UI
TJ, Total Jitter, 37.5% RX EQ
0.205
0.533
0.340
0.075
UI
TJ, Total Jitter, 50% RX EQ
0.222
0.610
0.438
0.080
UI
TJ, Total Jitter, 62.5% RX EQ
0.330
0.660
0.509
0.073
UI
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Chapter 3: PMA Receiver Characterization
RX OOB Signal Detect
Test Description
This test was designed to measure when the OOB signal was detected. The test measures
the voltage at which the OOB was detected across various settings of
OOBDETECT_THRESHOLD.
Test Setup
The RX OOB signal detect test was conducted using Automated Test Equipment (ATE).
Figure 3-63, page 165 illustrates the equipment used for this test.
ATE equipment was used to measure response of each of the 12 GTP transceivers
simultaneously. The Agilent ParBERT produces OOB signals and then checks to see if the
GTP transceiver responded to the OOB. The OOBDETECT_THRESHOLD_0(_1) were
changed from 000 to 111 while the ParBERT controlled the OOB amplitude and
measurements were made. The number of GTP transceivers that responded at a particular
OOB threshold voltage are plotted at the specific OOBx setting in Figure 3-64, page 166.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-81 shows the appropriate REFCLK
frequency, and PLL multiplier to create a proper PLL frequency for each of the tested data
rates.
Table 3-81:
RX OOB Signal Detect Test PLL Parameters
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
2.5
1.00
100
1
PLL_DIVSEL_FB
Post Divider (1)
and DIV
2 * 5 = 10
Oversample
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-82. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-82:
RX OOB Signal Detect Test Settings
GTP_DUAL Port Settings
Port
INTDATAWIDTH
Rate Affected
Value
All
1: 10-bit datapath
GTP_DUAL Attribute Settings
Attribute
OOBDETECT_THRESHOLD_0
OOBDETECT_THRESHOLD_1
OVERSAMPLE_MODE
164
Rate Affected
Value
All
000 to 111
All
FALSE
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RX OOB Signal Detect
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained inTable 3-83.
Table 3-83:
RX OOB Signal Detect Test Conditions
Test Parameter
Test Value
Loopback Mode
Fabric Loopback
Pattern
OOB Pattern
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Boards
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
Various (see Table 3-81)
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
12
Pair
FR4
PCB
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_56_042207
Figure 3-63:
ATE Test Setup for RX OOB Signal Detect Tests
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Results
Virtex-5 GTP RX OOB by Setting
(Temperature = 100°C, –40°C, 0°C; VCC = VNOM, VNOM ± 5%; Data Rate 2.50 Gb/s)
1400
OOB0
Number of Data Points
1200
OOB1
OOB2
1000
OOB3
OOB4
800
OOB5
OOB6
600
OOB7
400
200
0
0
20
40
60
80
100
120
140
160
OOB (mV)
180
200
RPT056_c3_57_052407
Figure 3-64: RX OOB Signal Detect Results by OOB Setting at 2.5 Gb/s
Table 3-84:
RX OOB Signal Detect Results by OOB Setting at 2.5 Gb/s
Parameter
Min
Max
Average
Std Dev
Units
RX OOB Threshold, OOB0
30.00
120.00
77.46
13.41
mV
RX OOB Threshold, OOB1
45.00
120.00
85.20
12.95
mV
RX OOB Threshold, OOB2
60.00
135.00
91.97
13.39
mV
RX OOB Threshold, OOB3
60.00
135.00
98.64
13.40
mV
RX OOB Threshold, OOB4
75.00
150.00
104.80
13.88
mV
RX OOB Threshold, OOB5
75.00
165.00
111.78
14.28
mV
RX OOB Threshold, OOB6
75.00
165.00
118.29
14.42
mV
RX OOB Threshold, OOB7
90.00
180.00
127.17
15.49
mV
Virtex-5 GTP RX OOB6, 2.50 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1200
Number of Data Points
100
800
600
400
200
0
0
30
60
90
120
150
180
210
240
270
RX OOB Threshold
Figure 3-65:
Table 3-85:
330
360
RX OOB Signal Detect Example Distribution, OOB
RX OOB6 Signal Detect Results at 2.5 Gb/s
Parameter
RX OOB Threshold, OOB6
166
300
RPT056_c3_58_052407
Min
Max
Average
Std Dev
Units
75.00
165.00
118.29
14.42
mV
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RX CID Run Length
RX CID Run Length
Test Description
This test was designed to identify when the RX side of the GTP transceiver starts to detect
bit errors when a consecutive identical digits (CID) pattern was being received. The test
was conducted on the ATE using the ParBERT to send a repetitive pattern. The pattern was
modified until a GTP transceiver begins to fail. Each failure it tallied and then presented in
a histogram to demonstrate the number of CID that the GTP transceiver can accept before
the RX begins to fail.
Test Setup
ATE equipment was used to measure the RX CID Run Length on all 12 GTP transceivers
simultaneously. A ParBERT analyzer was used to measure the BER of each of the GTP RX
inputs. The ParBERT was also used to transmit a specific pattern to the RX. This pattern
consists of five parts, as illustrated below. The first part was a PRBS31 pattern, which is
followed by a pattern of all ones, followed by another PRBBS31 pattern, then a pattern of
all zeros, and finally a padding to fill in the balance of ParBERT pattern memory. RX was
stressed with increasing CID run lengths until an error was detected. The repeated applied
pattern was:
PRBS31
(15K bits)
All 1s
(RUN-LENGTH)
PRBS31
(15K bits)
All 0s
(RUN-LENGTH)
PAD
The PAD section of the pattern was required for the ParBERT to put the pattern on a
memory boundary.
RX CID run length data was collected using ATE. Figure 3-66, page 169 illustrates the
equipment used for this test.
Two REFCLKs were used to clock the GTP transceivers. The REFCLKs were sourced from
a 3.2 Gb/s data generator using a clock pattern. Table 3-86 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested rates.
Table 3-86:
RX CID Run Length Test PLL Parameters
Data Rate
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
PLL_DIVSEL_FB
and DIV
Post
Divider (1)
Oversample
500 Mb/s
1.00
100
1
2 * 5 = 10
4
1
1.00 Gb/s
1.00
100
1
2 * 5 = 10
2
1
2.0 Gb/s
1.00
100
1
2 * 5 = 10
1
1
2.488 Gb/s
1.244
155.52
1
2*4=8
1
1
2.5 Gb/s
1.25
62.5
1
4 * 5 = 20
1
1
2.5 Gb/s
1.25
100
2
5 * 5 = 25
1
1
2.5 Gb/s
1.25
125
1
2 * 5 = 10
1
1
2.5 Gb/s
1.25
250
1
1*5=5
1
1
3.125 Gb/s
1.5625
156.25
1
2 * 5 = 10
1
1
3.2 Gb/s
1.60
320
1
1*5=5
1
1
3.75 Gb/s
1.875
187.5
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
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Chapter 3: PMA Receiver Characterization
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-87. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-87:
RX CID Run Length Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
INTDATAWIDTH
Value
All but 2.488 Gb/s
1: 10-bit datapath
2.488 Gb/s
0: 8-bit datapath
GTP_DUAL Attribute Settings
Attribute
OVERSAMPLE_MODE
Rate Affected
Value
All but 100 and 500 Mb/s (OS)
FALSE
100 and 500 Mb/s (OS)
TRUE
Various conditions were used to characterize the GTP transceivers for this test. Conditions
relevant to this test are contained in Table 3-88.
Table 3-88:
RX CID Run Length Test Conditions
Test Parameter
Loopback Mode
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF, SF, FS
GTP_DUAL Location Used
All 12 Locations
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Boards
Virtex-5 LXT FF1136 Test Fixture
FR-4 Length
3.25 inches
REFCLK and PLL Rates
168
Test Value
Various (see Table 3-86)
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RX CID Run Length
IEEE-488 (GPIB)
Clock
Generator
Power
Supply
PC
PC4
FR4
PCB
12
Pair
GTP
FR4
PCB
12
Pair
FPGA
DUT
Virtex-5 Characterization
Load Board
Agilent ParBERT
RPT056_c3_60_042207
Figure 3-66:
ATE Test Setup for RX CID Run Length Tests
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Chapter 3: PMA Receiver Characterization
Results
RX CID Run Length Test Results at 500 Mb/s, External AC
Virtex-5 GTP RX Run Length, 500 Mb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
400
800
1200
1600
2000
RX Run Length (UI)
Figure 3-67:
Table 3-89:
2400
RPT056_c3_61_052407
RX CID Run Length at 500 Mb/s, C & I Grades
RX CID Run Length Test at 500 Mb/s
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
RX CID Run Length Test Results at 1.00 Gb/s, External AC
Virtex-5 GTP RX Run Length, 1.00 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
800
Number of Data Points
700
600
500
400
300
200
100
0
0
400
800
1200
1600
RX Run Length (UI)
Figure 3-68:
Table 3-90:
2400
RPT056_c3_62_052407
RX CID Run Length at 1.00 Gb/s, C & I Grades
RX CID Run Length Test at 1.00 Gb/s
Parameter
RX CID Run Length
170
2000
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
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RX CID Run Length
RX CID Run Length Test Results at 2.0 Gb/s, 100 MHz REFCLK, External AC
Virtex-5 GTP RX Run Length, 2.00 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2000
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
400
800
1200
1600
RX Run Length (UI)
Figure 3-69:
Table 3-91:
2000
2400
RPT056_c3_63_052407
RX CID Run Length at 2.00 Gb/s, 100 MHz REFCLK, C & I Grades
RX CID Run Length Test at at 2.00 Gb/s, 100 MHz REFCLK, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
RX CID Run Length Test Results at 2.488 Gb/s, Internal AC
Virtex-5 GTP RX Run Length, 2.488 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1600
Number of Data Points
1400
1200
1000
800
600
400
200
0
72
80
128
256
750
RX Run Length (UI)
Figure 3-70:
Table 3-92:
1200
2000
RPT056_c3_64_052407
RX CID Run Length Test at 2.488 Gb/s, C & I Grades
RX CID Run Length Test at 2.488 Gb/s, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
750
2000
1544
459
UI
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Chapter 3: PMA Receiver Characterization
RX CID Run Length Test Results at 2.5 Gb/s, 62.5 MHz REFCLK, External AC
Virtex-5 GTP RX Run Length, 2.50 Gb/s (/20), I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2000
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
400
800
1200
1600
RX Run Length (UI)
Figure 3-71:
Table 3-93:
2000
2400
RPT056_c3_65_052407
RX CID Run Length at 2.5 Gb/s, 62.5 MHz REFCLK, C & I Grades
RX CID Run Length Test at 2.5 Gb/s, 62.5 MHz REFCLK, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
RX CID Run Length Test Results at 2.5 Gb/s, 100 MHz REFCLK, Internal AC
Virtex-5 GTP RX Run Length, 2.50 Gb/s (100 MHz Ref), I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
72
80
128
256
750
RX Run Length (UI)
2000
RPT056_c3_66_052407
Figure 3-72:
RX CID Run Length Test at 2.5 Gb/s, 100 MHz REFCLK, C & I Grades
Table 3-94:
RX CID Run Length Test at 2.5 Gb/s, 100 MHz REFCLK, C & I Grades
Parameter
RX CID Run Length
172
1200
Min
Max
Average
Std Dev
Units
128
2000
1328
524
UI
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RX CID Run Length
RX CID Run Length Test Results at 2.5 Gb/s, 125 MHz REFCLK, External AC
Virtex-5 GTP RX Run Length, 2.50 Gb/s (/10), I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2000
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
400
800
1200
1600
RX Run Length (UI)
Figure 3-73:
Table 3-95:
2000
2400
RPT056_c3_67_052407
RX CID Run Length at 2.5 Gb/s, 125 MHz REFCLK, C & I Grades
RX CID Run Length Test at 2.5 Gb/s, 125 MHz REFCLK, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
RX CID Run Length Test Results at 3.125 Gb/s, Internal AC
Virtex-5 GTP RX Run Length, 3.125 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
72
80
128
256
750
RX Run Length (UI)
Figure 3-74:
Table 3-96:
1200
2000
RPT056_c3_68_052407
RX CID Run Length at 3.125 Gb/s, C & I Grades
RX CID Run Length Test at 3.125 Gb/s, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
256
2000
1436
505
UI
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Chapter 3: PMA Receiver Characterization
RX CID Run Length Test Results at 3.2 Gb/s, External AC
Virtex-5 GTP RX Run Length, 3.20 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2000
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
400
800
1200
1600
2000
RX Run Length (UI)
Figure 3-75:
Table 3-97:
2400
RPT056_c3_69_052407
RX CID Run Length at 3.2 Gb/s, C & I Grades
RX CID Run Length Test at 3.2 Gb/s, C & I Grades
Parameter
RX CID Run Length
Min
Max
Average
Std Dev
Units
2000
-
2000
0
UI
RX CID Run Length Test Results at 3.75 Gb/s, External AC
Virtex-5 GTP RX Run Length, 3.75 Gb/s, I-Grade
(Units = TT, FF, SS, FS, SF, VCC = VNOM, VNOM ± 5% V, Temp = 0°C, –40°C, 100°C)
2000
1800
Number of Data Points
1600
1400
1200
1000
800
600
400
200
0
0
400
800
1200
1600
RX Run Length (UI)
Figure 3-76:
Table 3-98:
2400
RPT056_c3_85_041108
RX CID Run Length at 3.75 Gb/s, C & I Grades
RX CID Run Length Test at 3.75 Gb/s, C & I Grades
Parameter
RX CID Run Length
174
2000
Min
Max
Average
Std Dev
Units
2000
2000
2000
0
UI
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RX CID Run Length
Conclusion
Table 3-99 presents a summary of results for the RX CID Run Length test.
Table 3-99:
RX CID Run Length Test, Summary
Parameter
RX CID Run
Length
Rate
Int/Ext AC
Min
Max
Average
Std Dev
Units
500 Mb/s
Ext
2000
-
2000
0
UI
1.0 Gb/s
Ext
2000
-
2000
0
UI
2.0 Gb/s 100 MHz REFCLK
Ext
2000
-
2000
0
UI
2.488 Gb/s
Int
750
2000
1544
459
UI
2.5 Gb/s 62.5 MHz REFCLK
Ext
2000
-
2000
0
UI
2.5 Gb/s 100 MHz REFCLK
Int
128
2000
1328
524
UI
2.5 Gb/s 125 MHz REFCLK
Ext
2000
-
2000
0
UI
3.125 Gb/s
Int
256
2000
1436
505
UI
3.2 Gb/s
Ext
2000
-
2000
0
UI
3.75 Gb/s
Ext
2000
2000
2000
0
UI
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Chapter 3: PMA Receiver Characterization
RX Jitter Transfer Based on Data to Recovered Clock
Test Description
This test measured the amount of jitter presented on the recovered clock based upon jitter
present in the data. The results demonstrate the frequency response of the CDR to data
input jitter.
Test Setup
The GTP reference clock input was characterized for its input jitter tolerance as a function
of modulation frequency at three data rates: 1.00 Gb/s, 2.0 Gb/s, and 2.5 Gb/s. The
Agilent N4901B Serial BERT was used to provide RX input data test patterns and check for
errors after the input was looped through the device. For each test case, the jitter
modulation frequency was swept from 1 KHz to 300 MHz, and the jitter amplitude to the
passed points was plotted as a function of frequency.
Reference clock input jitter tolerance measurements were performed using the test setup as
shown in Figure 3-77.
IEEE-488 (GPIB)
Agilent
8648C
Signal
Generator
CLK
FR4
PCB
122
GTP_DUAL X0Y0
FPGA
DUT
Virtex-5 ML523 Characterization
Platform
SAMs
A
B
C
D
FR4
PCB
P/N
Pair
SAMs
P/N
Pair
120
GTP_DUAL X0Y5
LPT2
PC
PC4
Splitter
Rotary P/N
Relay x2 Pair
Agilent
M4901B
Serial
BERT
Agilent
6624A
Power
Supplies
Rotary
Relay x2
A
B
C
D
P/N
Pair
Agilent
34999B
Switch
Control
System
P/N Pair
RPT056_c2_167_041807
Figure 3-77:
176
RX Jitter Transfer to Recovered Clock Test Bench Setup
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RX Jitter Transfer Based on Data to Recovered Clock
A REFCLK was used to clock the GTP transceivers. The REFCLK was sourced from a
3.2 Gb/s data generator using a clock pattern. Table 3-100 shows the appropriate REFCLK
frequency and PLL multiplier to create a proper PLL frequency for each of the tested data
rates
Table 3-100:
RX Jitter Transfer to Recovered Clock Test PLL Settings
Data Rate
(Gb/s)
PLL Freq
(GHz)
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
PLL_DIVSEL_FB
and DIV
Post Divider (1)
Oversample
1.00
1.00
100
1
2 * 5 = 10
2
1
2.0
1.00
100
1
2 * 5 = 10
1
1
2.5
1.25
125
1
2 * 5 = 10
1
1
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-101. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-101:
RX Jitter Transfer to Recovered Clock Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
All
1: 10-bit datapath
INTDATAWIDTH
GTP_DUAL Attribute Settings
Attribute
Rate Affected
Value
All
FALSE
All
TRUE
All
TRUE
All
6C08040
OVERSAMPLE_MODE
RCV_TERM_GND_0
RCV_TERM_GND_1
RCV_TERM_MID_0
RCV_TERM_MID_1
PMA_CDR_SCAN_0
PMA_CDR_SCAN_1
Various conditions were used to characterize the GTP transceivers. Conditions relevant to
this test are contained in Table 3-102.
Table 3-102:
RX Jitter Transfer to Recovered Clock Test Conditions
Test Parameter
Loopback Mode
Test Value
Fabric Loopback
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
X0Y1, X0Y5
Junction Temperature
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
Various (see Table 3-100)
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Chapter 3: PMA Receiver Characterization
Results
RX Jitter Transfer to Recovered Clock Test, Trends
Virtex-5 GTP RX Jitter Transfer to Recovered Clock
(Temp = –40°C, 0°C, 100°C, MGTAVTTRX = 1.2V ± 5%, Split: SS, TT, FF)
3
JPP(Out) / JPP(In) (dB)
0
-3
-6
1 Gb/s
-9
2 Gb/s
2.5 Gb/s
-12
-15
-18
0.01
0.1
1
10
Modulation Frequency (MHz)
RPT056_c3_71_050508
Figure 3-78: RX Jitter Transfer to Recovered Clock, Trends
RX Jitter Transfer to Recovered Clock Test, 1.00 Gb/s
Virtex-5 GTP RX Jitter Transfer to Recovered Clock 1.0 Gb/s
(Split = SS, TT, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
90
Number of Data Points
80
70
60
50
40
30
20
10
–3 dB Frequency (MHz)
Figure 3-79:
Table 3-103:
5
4.5
4.75
4
RPT056_c3_72_050508
RX Jitter Transfer to Recovered ClockK, 1.00 Gb/s
RX Jitter Transfer to Recovered Clock, 1.00 Gb/s
Parameter
RX Transfer Jitter BW –3dB
178
4.25
3.5
3.75
3
3.25
2.5
2.75
2
2.25
1.75
1.5
1
1.25
0.5
0.75
0
0.25
0
Min
Max
Average
Std Dev
Units
0.644
1.750
0.909
0.179
MHz
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RX Jitter Transfer Based on Data to Recovered Clock
RX Jitter Transfer to Recovered Clock Test, 2.0 Gb/s
Virtex-5 GTP RX Jitter Transfer to Recovered Clock 2.0 Gb/s
(Split = SS, TT, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
60
Number of Data Points
50
40
30
20
10
–3 dB Frequency (MHz)
Figure 3-80:
Table 3-104:
5
4.5
4.75
4
4.25
3.5
3.75
3
3.25
2.5
2.75
2
2.25
1.5
1.75
1
1.25
0.5
0.75
0
0.25
0
RPT056_c3_73_050508
RX Jitter Transfer to Recovered Clock, 2.0 Gb/s, 100 MHz REFCLK
RX Jitter Transfer to Recovered Clock, 2.0 Gb/s, 100 MHz REFCLK
Parameter
Min
Max
Average
Std Dev
Units
RX Transfer Jitter BW –3dB
0.711
1.870
1.171
0.250
MHz
RX Jitter Transfer to Recovered Clock Test, 2.5 Gb/s
Virtex-5 LX50, RX Jitter Transfer to Recovered Clock 2.5 Gb/s
(Split = SS, TT, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
Number of Data Points
25
20
15
10
5
–3 dB Frequency (MHz)
Figure 3-81:
Table 3-105:
5
4.5
4.75
4
4.25
3.5
3.75
3
3.25
2.5
2.75
2
2.25
1.75
1.5
1
1.25
0.5
0.75
0
0.25
0
RPT056_c3_74_050508
RX Jitter Transfer to Recovered Clock, 2.5 Gb/s, 125 MHz REFCLK
RX Jitter Transfer to Recovered Clock, 2.5 Gb/s, 125 MHZ REFCLK
Parameter
RX Transfer Jitter BW –3dB
Min
Max
Average
Std Dev
Units
1.444
3.868
2.345
0.577
MHz
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Chapter 3: PMA Receiver Characterization
Conclusion
Table 3-106 presents a summary of results for the RX jitter transfer test.
Table 3-106:
RX Jitter Transfer to Recovered Clock Test, Summary
Parameter
180
Rate
Min
Max
Average
Std Dev
Units
RX Transfer Jitter
BW –3dB
1.0 Gb/s
0.644
1.750
0.909
0.179
MHz
RX Transfer Jitter
BW –3dB
2.0 Gb/s @
100 MHz
0.711
1.870
1.171
0.250
MHz
RX Transfer Jitter
BW –3dB
2.5 Gb/s @
125 MHz
1.444
3.868
2.345
0.577
MHz
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RX Termination DC Resistance
RX Termination DC Resistance
Test Description
This test measured the DC resistance of the RX pair.
Test Setup
RX termination resistance was measured across the RXP and RXN pair using a high
precision DVM after setting RREF to 50Ω ±1%, while also setting TERMINATION_CTRL
off (00000) and TERMINATION_OVERLOAD to FALSE. Measurements were taken
across PVT as well as differing GTP transceiver locations.
Figure 3-82, page 183 illustrates the equipment used for this test. Temperature forcing
equipment was used to precisely control the temperature of the DUT. Figure 3-83, page 184
illustrates how Virtex-5 LXT devices terminate both RX and TX.
Since this test was done at DC conditions, no REFCLKs were used. Table 3-107 reflects
these DC conditions.
Virtex-5 GTP transceivers support one common resistor calibration circuit block for
trimming the input termination resistor to match line impedance to minimize reflections.
Figure 3-83, page 184 shows the general block diagram for the resistor calibration macro. It
requires an external resistor that sets up a reference current for comparison. Current
through the external resistor was compared against the current through the internal
variable resistor R0, which was then adjusted accordingly by the finite state machine
(FSM).
An external precision resistor was specified at 50Ω with 1% tolerance. Measured resistance
was 49.9Ω to 50.1Ω, less than 1%.
Table 3-107:
RX Transfer Jitter Test PLL Settings
Data Rate PLL Freq
(Gb/s)
(GHz)
N/A
N/A
REFCLK Freq
(MHz)
PLL_DIVSEL_REF
N/A
N/A
PLL_DIVSEL_FB
Post Divider (1)
and DIV
N/A
Oversample
N/A
N/A
Notes:
1. The appropriate settings for PLL_TXDIVSEL_OUT_n, PLL_TXDIVSEL_COMM_OUT, and PLL_RXDIVSEL_OUT_n.
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Chapter 3: PMA Receiver Characterization
Additionally, a PC running ISE software was used to configure the FPGA and set the
parameters of the GTP transceivers. Each GTP transceiver was set up with the settings in
Table 3-108. Only those settings that differ from Appendix A, “General GTP_DUAL Test
Settings” or were otherwise important for this specific test are listed.
Table 3-108:
RX Transfer Jitter Test Settings
GTP_DUAL Port Settings
Port
Rate Affected
Value
N/A
N/A
N/A
GTP_DUAL Attribute Settings
Attribute
Rate Affected
Value
N/A
FALSE
TERMINATION_CTRL[4:0]
N/A
00000
TERMINATION_OVRD
N/A
FALSE
AC_CAP_DIS_0
AC_CAP_DIS_1
Various conditions were used to characterize the GTP transceivers. Conditions relevant to
this test are contained in Table 3-109.
Table 3-109:
RX Termination Resistance Test Conditions
Test Parameter
Loopback Mode
N/A
Pattern
PRBS31
Silicon Corner Used
SS, TT, FF
GTP_DUAL Location Used
Junction Temperature
All 12 Locations
–40°C, 0°C, 100°C
Power Supplies
±5%
Test Board
ML523
FR-4 Length
4.25 inches
REFCLK and PLL Rates
182
Test Value
Various (see Table 3-107)
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RX Termination DC Resistance
8060A DVM
RXP
MGTAVTTRX
RXN
RPT056_c3_75a_052807
Figure 3-82:
RX Termination Resistance Test Setup
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Chapter 3: PMA Receiver Characterization
RX/TX
Termination
Override/Offset
Code
Other GTP_DUAL Tiles North of the Center
BRcal
MGTRREF
Package Pin
RREF
External 50Ω
Precision Resistor
Comparator
MGTAVTTTX
rCtrl[0:4]
Internal Resistor
Network
“Master” GTP_DUAL Tile
for Resistor Calibration
Override/Offset
Code
RX/TX
Termination
Other GTP_DUAL Tiles South of the Center
RPT056_c3_76_042207
Figure 3-83:
184
RX Termination Resistor Calibration Macro
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RX Termination DC Resistance
Results
The device automatically calibrated its termination value each time the part was
configured; consequently, for each measurement, the device was reprogrammed ten times
and the Min and Max value of these ten trials was recorded. Table 3-110 summarizes the
results from these tests.
Virtex-5 GTP RX Impedance, Differential, I-Grade
(VNOM, VNOM ± 5% , All Splits, Temp = 0°C, 25°C, 100°C)
40
Number of Data Points
35
30
25
20
15
10
5
RX Termination DC Resistance
Figure 3-84:
Table 3-110:
123
125
121
119
117
115
113
111
109
107
105
103
99
101
97
95
93
91
89
87
0
RPT056_c3_77_052407
RX Termination DC Resistance Historgram
RX Termination DC Resistance Measurement
Parameter
RX Termination DC Resistance
Min
Max
Average
Std Dev
Units
102.10
116.40
108.20
2.85
Ω
Conclusion
Table 3-110 summarizes the results for RX termination resistor measurement across the
conditions listed in Table 3-107 through Table 3-109.
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Chapter 3: PMA Receiver Characterization
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Chapter 4
GTP_DUAL Transceiver Power
Consumption
GTP_DUAL Transceiver PMA Power Consumption (ATE
Measurement)
GTP_DUAL transceiver PMA power consumption is measured by recording the source
current values from the respective PMA power supplies when all 12 GTP transceivers in
the LX50T device are active. Measurement is repeated for all devices tested across process,
voltage and temperature combinations. Test conditions, devices, and setup for this test are
the same as described in the PMA ATE RX/TX tests in the previous sections. Table 4-1
provides the average and standard deviation power consumption values of all cases
tested, at the data rates specified in the table. The PMA power consumption numbers are
listed in the last two columns in mW, first for the GTP transceiver pairs (GTP_DUAL),
where both channels share the PLL, and the last column shows the single GTP transceiver
PMA plus the PLL power.
Table 4-1:
Average and Deviation Power Consumption
Description
Test Case
GTP Transceiver Power, mW
Method
The GTP transceiver is operated at the specified data rate, and
current is measured for each of the PMA analog power supplies
when all 12 GTP transceivers are active. Then PAVCCPLL is divided
by 6 and the rest of the supplies are divided by 12.
Power per GTP transceiver is calculated as:
PAVCCPLL + (PAVCC + PAVTTTX + PAVTTRX)/2
Configuration/
Standard
Data rates = 1.250/2.488/2.500/3.125 Gb/s
Pattern
PRBS31, Input Amplitude = 250mV S/E
Conditions
VCC = NOM, ±5%, Temp = –40°C to 100 C (I-Grade)
Results (2.500 Gb/s)
AVERAGE = 98mW, Std Dev = 10.4 mW,
AVERAGE + 3.5δ = 134 mW
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Chapter 4: GTP_DUAL Transceiver Power Consumption
Table 4-2:
Results
Power by Supply Rail (1)
Data Rate
1.25 Gb/s,
125 MHz
REFCLK
2.488 Gb/s,
155.52 MHz
REFCLK
2.5 Gb/s,
100 MHz
REFCLK
2.5 Gb/s,
250 MHz
REFCLK
3.125 Gb/s,
156.25 MHz
REFCLK
3.75 Gb/s,
187.50 MHz
REFCLK
Total Power
PMGTAVTTTX PMGTAVCCPLL PMGTAVTTRXC PMGTAVTTRX
PMGTAVCC
PGTP_DUAL PGTP_SINGLE
Units
AVG
416.6
207.8
0.1
0.3
295.4
153.4
94.0
mW
STDEV
53.7
36.4
0.1
0.1
71.2
17.9
9.8
mW
mW
MIN
244.4
90.7
0.0
0.1
205.7
112.3
69.0
MAX
504.1
334.8
0.5
0.6
554.0
210.0
121.9
mW
AVG
424.8
204.5
0.1
0.3
339.7
161.6
97.8
mW
STDEV
55.6
21.9
0.1
0.1
74.2
19.3
10.3
mW
MIN
248.0
90.7
0.0
0.1
207.3
116.5
69.8
mW
MAX
521.7
246.6
0.5
0.6
606.1
220.7
127.6
mW
AVG
428.1
202.4
0.1
0.3
337.9
161.5
97.6
mW
STDEV
55.0
31.8
0.1
0.1
75.6
19.0
10.4
mW
MIN
244.1
90.4
0.0
0.1
204.0
114.4
68.8
mW
MAX
514.2
342.9
0.4
0.6
602.3
217.1
125.3
mW
AVG
426.5
213.6
0.1
0.3
341.8
163.7
99.7
mW
STDEV
57.8
28.4
0.1
0.1
76.4
19.1
10.0
mW
MIN
240.4
176.6
0.0
0.2
249.1
115.5
74.6
mW
MAX
529.7
318.6
0.5
0.6
605.3
221.5
128.4
mW
AVG
430.2
245.6
0.1
0.3
365.3
173.6
107.2
mW
STDEV
57.5
28.6
0.1
0.1
76.3
20.1
10.9
mW
MIN
243.9
90.7
0.0
0.1
206.4
124.3
69.7
mW
MAX
530.9
298.4
0.4
0.6
632.4
231.5
136.1
mW
AVG
447.0
318.5
2.3
0.3
413.5
197.2
125.0
mW
STDEV
43.3
25.3
0.3
0.1
55.1
17.6
10.1
mW
MIN
365.2
253.8
1.8
0.1
317.1
166.7
106.7
mW
MAX
546.5
364.3
3.1
0.5
537.2
231.3
145.2
mW
Notes:
1. Cumulative power of six GTP_DUAL sites operating at the indicated rate.
Virtex-5 GTP Single Transceiver Power, I-Grade
(Units = TT, FS, SF, SS, FF, VCC = VNOM, VNOM ± 5% V, Temp = –40°C, 0°C, 100°C)
(Datarate/refclk = 2.5/250Mhz, 2.5/100Mhz, 3.125G/156Mhz, 2488G/155Mhz, 1.25G/125Mhz)
35
Number of Datapoints
30
25
1.25G
2.488G
2.5G_100
2.5G_250
3.125G
20
15
10
5
0
0
20
40
60
80
100
120
140
Power (mW)
Figure 4-1:
188
160
180
200
220
240
RPT056_c4_01_052407
GTP Single Transceiver Power Consumption at Differing Rates
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Appendix A
General GTP_DUAL Test Settings
Table A-1 and Table A-2 indicate relevant parameters that affect the results of the
characterization tests. Unless otherwise specified, the values listed in these tables apply to
every test. Table A-1 shows the how the ports are setup, while Table A-2 shows the
attributes for the GTP_DUAL model.
Table A-1:
Relevant GTP_DUAL Port Settings
Port
Dir
Description
Set Value
CLKIN
In
Reference clock input to the shared
PMA PLL.
REFCLK
CRCCLK
In
CRC clock.
Default
Sets the internal datapath width
for the GTP_DUAL tile.
INTDATAWIDTH
RXENEQB0
RXENEQB1
RXEQMIX0[1:0]
RXEQMIX1[1:0]
RXEQPOLE0[3:0]
RXEQPOLE1[3:0]
In
Enables receiver equalization
(active Low).
1
In
Sets the wideband/high-pass mix
ratio for the RX equalizer.
00
In
Sets high-pass filter pole location
for the RX equalizer.
0000
In
Controls the strength of the TX
pre-drivers. Tie this port to the
same value as TXDIFFCTRL.
100
In
Controls the operation of the TX
8B/10B encoder on a per-byte
basis.
In
Controls the transmitter
differential output swing.
000
In
Controls the relative strength of the
main drive and the pre-emphasis.
000
TXBYPASS8B10B0[1:0]
TXBYPASS8B10B1[1:0]
TXDIFFCTRL0[2:0]
TXDIFFCTRL1[2:0]
TXPREEMPHASIS0[2:0]
TXPREEMPHASIS1[2:0]
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Varies. See test
setup tables.
In
TXBUFDIFFCTRL0[2:0]
TXBUFDIFFCTRL1[2:0]
0: 8-bit internal datapath width
1: 10-bit internal datapath
width
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Appendix A: General GTP_DUAL Test Settings
Table A-2:
Relevant GTP_DUAL Attribute Settings
Attribute
Description
CHAN_BOND_1_MAX_SKEW_0
CHAN_BOND_1_MAX_SKEW_1
CHAN_BOND_2_MAX_SKEW_0
CHAN_BOND_2_MAX_SKEW_1
AC_CAP_DIS_0
AC_CAP_DIS_1
Sets the maximum amount of lane skew
allowed when using channel bonding.
Must be set less than 1/2 the minimum
distance between channel bonding
sequences.
Default
Disables built-in AC coupling capacitors
on receiver inputs when set to TRUE.
TRUE
CLK25_DIVIDER
Sets the divider used to divide CLKIN
REFCLK / 5
down to an internal rate close to 25 MHz.
CLKINDC_B
Must be set to TRUE. Oscillators driving
the dedicated reference clock inputs must
be AC coupled.
OOB_CLK_DIVIDER
Sets the squelch clock rate based on
CLKIN.
OOBDETECT_THRESHOLD_0
OOBDETECT_THRESHOLD_1
Sets the minimum differential voltage
between RXN and RXP before a signal is
considered a PCI electrical idle or a SATA
OOB signal.
TRUE
4
000
OVERSAMPLE_MODE
Enables 5X oversampling.
PLL_DIVSEL_FB
Controls the feedback divider of the
shared PMA PLL.
Varies. See
test setup
tables.
PLL_DIVSEL_REF
Controls the reference clock divider of the
shared PMA PLL.
Varies. See
test setup
tables.
PLL_RXDIVSEL_OUT_0
Defines the nominal line rate for the
receiver based on the shared PMA PLL
rate
PLL_RXDIVSEL_OUT_1
PLL_SATA_0
PLL_SATA_1
PLL_TXDIVSEL_COMM_OUT
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
190
Set Value
FALSE
Varies. See
test setup
tables.
Varies. See
test setup
tables.
Tie to FALSE. When FALSE, allows TX
SATA operations to work at the SATA1 or
SATA2 rate.
FALSE
Sets a common line rate divider for both
GTP transceivers in a tile. Can be used
instead of PLL_TXDIVSEL_OUT if both
transceivers are using the same TX
divider value.
1
Sets the divider for the TX line rate for
each GTP transceiver.
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tables.
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Table A-2:
Relevant GTP_DUAL Attribute Settings (Continued)
Attribute
Description
PMA_CDR_SCAN_0
Set Value
Allows direct control of the CDR
sampling point
6C08040
Adjusts CDR operation for oversampling
and PLL_RXDIVSEL_OUT settings. This
value enables the second-order loop filter.
0DCE089
Sets the RX termination voltage to GND.
Used with internal and external AC
coupling to support PCI Express
TXDETECTRX functionality.
FALSE
Activates the internal RX termination
voltage. Set to TRUE when RX built-in
AC coupling is used.
FALSE
Sets RX termination voltage to VTTRX.
FALSE
TERMINATION_CTRL[4:0]
Controls internal termination calibration
circuit.
10100
TERMINATION_OVRD
Selects whether the external 50Ω
precision resistor, connected to the
GTPRREF pin, or an override value is
used, as defined by
TERMINATION_CTRL.
FALSE
Changes the strength of the TX driver and
pre-emphasis buffers. When set to TRUE,
the pre-emphasis percentage is boosted
or increased. Please see UG196, Virtex-5
RocketIO GTP Transceiver User Guide, for
nominal differential swing and preemphasis values. Overall differential
swing is reduced when TX_DIFF_BOOST
is TRUE.
FALSE
PMA_CDR_SCAN_1
PMA_RX_CFG_0
PMA_RX_CFG_1
RCV_TERM_GND_0
RCV_TERM_GND_1
RCV_TERM_MID_0
RCV_TERM_MID_1
RCV_TERM_VTTRX_0
RCV_TERM_VTTRX_1
TX_DIFF_BOOST_0
TX_DIFF_BOOST_1
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