MAX5065/MAX5067 +0.6V +3.3V ________________________________

19-3035; Rev 1; 11/03
+0.6V
+3.3V
________________________________
MAX5065/MAX5067
♦ +4.75V
PWM
MAX5065/MAX5067
RDS(ON)
♦
♦
+28V
60A
♦
+5.5V
+8V
VOUT
+0.6V +3.3V (MAX5065)
+0.8V +3.3V (MAX5067)
MOSFET
+4.75V
(
+5.5V
MAX5065/MAX5067
________________________________
+12V
+24V
♦
+8V +28V
500kHz)
♦
♦
♦
MAX5065/MAX5067
CLKIN)
(CLKIN)
(
♦
(CLKOUT)
MAX5065/
MAX5067
+0.6V +3.3V
+0.8V +3.3V
MAX5065/MAX5067
MAX5065
28
QFN
44
MAX5037A
MOSFET
♦
MAX5065
MAX5067
4A
♦
250kHz
♦
125kHz
♦
(-40°C +85°C)
SSOP
MAX5067
44
VRM 9.0/VRM 9.1
VID
QFN
________________________________
DC-DC
600kHz
DC-DC
PLL
♦
♦ 28
SSOP
♦ 44
QFN
(MAX5065)
(MAX5067)
____________________________
PART
/
500kHz
1MHz)
(
TEMP RANGE
PIN-PACKAGE
MAX5065EAI
-40°C to +85°C
28 SSOP
MAX5067ETH
-40°C to +85°C
44 Thin QFN
RAID
________________________________________________________________Maxim Integrated Products
Maxim
Maxim
Maxim
Maxim
www.maxim-ic.com.cn
1
MAX5065/MAX5067
+0.6V
+3.3V
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ............762mW
44-Pin Thin QFN (derate 27.0mW/°C above+70°C) ...2162mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND ........................................................-0.3V to +35V
DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V]
DL_ to PGND ..............................................-0.3V to (VCC + 0.3V)
BST_ to LX_ ..............................................................-0.3V to +6V
VCC to SGND............................................................-0.3V to +6V
VCC, VDD to PGND ...................................................-0.3V to +6V
SGND to PGND .....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (VCC + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
8
28
4.75
5.50
Input Voltage Range
VIN
Quiescent Supply Current
IQ
EN = VCC or SGND
4
Efficiency
η
ILOAD = 52A (26A per phase)
90
Short IN and VCC together for +5V input
operation
10
V
mA
%
OUTPUT VOLTAGE
No load
MAX5065 No load, VCC = +4.75V to +5.5V
or VIN = +8V to +28V
SENSE+ to SENSE- Accuracy
(Note 4)
No load
MAX5067 No load, VCC = +4.75V to +5.5V
or VIN = +8V to +28V
0.5952
0.6
0.6048
0.594
0.6
0.6064
0.7936
0.8
0.8064
0.792
0.8
0.808
4.0
4.15
4.5
V
STARTUP/INTERNAL REGULATOR
VCC Undervoltage Lockout
UVLO
VCC rising
VCC Undervoltage Lockout
Hysteresis
200
VCC Output Accuracy
VIN = +8V to +28V, ISOURCE = 0 to 80mA
4.85
V
mV
5.1
5.30
V
1
3
Ω
MOSFET DRIVERS
Output Driver Impedance
RON
Output Driver Source/Sink
Current
IDH_, IDL_
Nonoverlap Time
tNO
Low or high output
CDH_/DL_ = 5nF
4
A
60
ns
OSCILLATOR AND PLL
Switching Frequency
fSW
PLL Lock Range
fPLL
PLL Locking Time
tPLL
2
CLKIN = SGND
238
250
262
CLKIN = VCC
475
500
525
125
600
200
_______________________________________________________________________________________
kHz
kHz
µs
+0.6V
+3.3V
(VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
CLKOUT Phase Shift
(At fSW = 125kHz)
CLKIN Input Pulldown Current
SYMBOL
φCLKOUT
MIN
TYP
MAX
PHASE = VCC
CONDITIONS
115
120
125
PHASE = unconnected
85
90
95
PHASE = SGND
55
60
65
5
7
ICLKIN
3
CLKIN High Threshold
VCLKINH
2.4
CLKIN Low Threshold
VCLKINL
tCLKIN
200
PHASE High Threshold
VPHASEH
4
PHASE Low Threshold
VPHASEL
PHASE Input Bias Current
IPHASEBIAS
VCLKOUTL
CLKOUT Output High Level
VCLKOUTH ISOURCE = 2mA (Note 2)
µA
V
ns
V
-50
CLKOUT Output Low Level
degrees
V
0.8
CLKIN High Pulse Width
UNITS
ISINK = 2mA (Note 2)
1
V
+50
µA
100
mV
4.5
V
CURRENT LIMIT
Average Current-Limit Threshold
VCL
CSP_ to CSN_
45
Reverse Current-Limit Threshold
VCLR
CSP_ to CSN_
-3.9
Cycle-by-Cycle Current Limit
VCLPK
CSP_ to CSN_ (Note 3)
Cycle-by-Cycle Overload
Response Time
tR
90
VCSP_ to VCSN_ = +150mV
48
112
51
mV
-0.2
mV
130
mV
260
ns
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
RCS_
4
kΩ
VCMR(CS)
-0.3
+3.6
V
VOS(CS)
-1
+1
mV
Amplifier Gain
AV(CS)
18
V/V
3dB Bandwidth
f3dB
4
MHz
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance
gmca
Open-Loop Gain
AVOL(CE)
No load
550
µS
50
dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range
VCMR(DIFF)
DIFF Output Voltage
VCM
Input Offset Voltage
VOS(DIFF)
Amplifier Gain
AV(DIFF)
3dB Bandwidth
f3dB
Minimum Output Current Drive
SENSE+ to SENSE- Input
Resistance
-0.3
VSENSE+ = VSENSE- = 0
+1.0
V
+1
mV
0.6
-1
0.997
CDIFF = 20pF
1
3
IOUT(DIFF)
1.0
RVS_
50
V
1.003
V/V
MHz
mA
100
kΩ
_______________________________________________________________________________________
3
MAX5065/MAX5067
ELECTRICAL CHARACTERISTICS (continued)
MAX5065/MAX5067
+0.6V
+3.3V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain
AVOL(EA)
70
dB
Unity-Gain Bandwidth
fUGEA
3
MHz
EAN Input Bias Current
IB(EA)
Error-Amplifier Output Clamping
Voltage
VEAN = +2.0V
VCLAMP(EA) With respect to VCM
-100
+100
nA
810
918
mV
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN
VOV
PGOOD goes low when VOUT is outside this
window
+6
+8
+10
VUV
PGOOD goes low when VOUT is outside this
window
-12.5
-10
-8.5
%VOUT
PGOOD Trip Level (MAX5067)
PGOOD Output Low Level
(MAX5067)
VPGLO
ISINK = 4mA
PGOOD Output Leakage Current
(MAX5067)
IPG
PGOOD = VCC
Phase Failure Trip Threshold
(MAX5067)
VPH
PGOOD goes low when CLP_ is higher
than VPH
OVPIN Trip Threshold (MAX5067)
OVPTH
OVPIN Input Resistance
(MAX5067)
ROVPIN
With respect to SGND
0.2
V
1
µA
2
V
0.792
0.8
0.808
V
190
280
370
kΩ
THERMAL SHUTDOWN
Thermal Shutdown
TSHDN
Thermal-Shutdown Hysteresis
150
°C
8
°C
EN INPUT
EN Input Low Voltage
VENL
EN Input High Voltage
VENH
3
IEN
4.5
EN Pullup Current
Note 1:
Note 2:
Note 3:
Note 4:
4
1
V
V
5
Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Guaranteed by design. Not production tested.
See Peak-Current Comparator section.
Does not include an error due to finite error amplifier gain. See the Voltage-Error Amplifier section.
_______________________________________________________________________________________
5.5
µA
+0.6V
+3.3V
f = 500kHz
60
VIN = +5V
VOUT = +1.8V
VIN = +5V
50
40
30
20
VOUT = +1.8V
fSW = 250kHz
VOUT = 1V
fSW = 250kHz
10
0
0 4 8 12 16 20 24 28 32 36 40 44 48 52
IOUT (A)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
90
60
50
40
30
VOUT = +1.5V
80
VOUT = +1.8V
30
30
VOUT = +1V
20
VIN = +12V
fSW = 250kHz
VIN = +12V
fSW = 500kHz
10
0
0
0
50
40
10
VOUT = +1.8V
60
40
20
VIN = +24V
VOUT = +1.8V
fSW = 125kHz
VOUT = +1.5V
70
VOUT = +1V
50
90
η (%)
80
100
MAX5065/67 toc05
MAX5065/67 toc04
100
MAX5065/67 toc06
0 4 8 12 16 20 24 28 32 36 40 44 48 52
IOUT (A)
60
0 4 8 12 16 20 24 28 32 36 40 44 48 52
0 4 8 12 16 20 24 28 32 36 40 44 48 52
0 4 8 12 16 20 24 28 32 36 40 44 48 52
IOUT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
VIN = +24V
100
90
80
100
250kHz
90
80
70
70
8.5
8.0
VIN = +12V
60
ICC (mA)
ICC (mA)
10.0
9.5
9.0
125kHz
50
EXTERNALCLOCK
NO DRIVER LOAD
100 150 200 250 300 350 400 450 500 550 600
FREQUENCY (kHz)
10
0
50
30
30
VIN = +5V
60
40
40
20
MAX5065/67 toc09
11.5
11.0
MAX5065/67 toc07
12.0
6.5
6.0
60
30
70
7.5
7.0
VIN = +12V
40
70
10.5
70
0 4 8 12 16 20 24 28 32 36 40 44 48 52
η (%)
η (%)
50
0
80
ICC (mA)
60
10
90
10
VIN = +5V
20
100
20
80
MAX5065/67 toc08
40
90
η (%)
η (%)
f = 250kHz
70
50
VIN = +12V
70
80
η (%)
90
80
100
MAX5065/67 toc02
90
100
MAX5065/67 toc01
100
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5065/67 toc03
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
20
VIN = +12V
CDL_ = 22nF
CDH_ = 8.2nF
-40
-15
VIN = +12V
fSW = 250kHz
10
0
10
35
TEMPERATURE (°C)
60
85
1
3
5
7
9
11
13
15
CDRIVER (nF)
_______________________________________________________________________________________
5
MAX5065/MAX5067
_______________________________________________________________
(Circuit of Figure 1. TA = +25°C, unless otherwise noted.)
+3.3V
____________________________________________________________
(
)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
OVERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
53
10
MAX5065/67 toc11
54
VOUT = +3.3V
51
50
49
PHASE 2
48
PHASE 1
VOUT = +3.3V
VUV (V)
52
VOV (V)
(VCSP_ - VCSN_) (mV)
10
MAX5065/67 toc10
55
UNDERVOLTAGE THRESHOLD (PGOOD)
vs. INPUT VOLTAGE
MAX5065/67 toc12
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
1
VOUT = +0.8V
1
VOUT = +0.8V
47
46
1.4
1.5
1.6
1.7
4.7
1.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
VOUT (V)
VIN (V)
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (RF/RIN)
DIFFERENTIAL AMPLIFIER BANDWIDTH
1.85
RF/RIN = 40
1.80
RF/RIN = 20
3.0
PHASE
GAIN (V/V)
1.70
1.65
RF/RIN = 7.5
1.5
0
0.01
0 4 8 12 16 20 24 28 32 36 40 44 48 52
VCC LOAD REGULATION
vs. INPUT VOLTAGE
1
0
0.150
-45
0.125
VIN = +12V
5.20
ICC = 0
5.15
0.050
-225
0.025
-270
0
4.95
4.90
4.85
DC LOAD
4.80
15 30 45 60 75 90 105 120 135 150
ICC (mA)
5.4
VCC LINE REGULATION
5.25
5.20
5.15
5.10
ICC = 40mA
5.05
5.00
5.05
5.00
4.95
4.95
4.90
4.90
4.85
4.85
4.80
4.80
ICC = 80mA
4.75
8
5.5
∆VSENSE (V)
4.75
0
5.3
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
10
VCC (V)
VIN = +8V
VCC (V)
5.00
5.2
0.075
-180
5.10
5.05
5.1
0.100
MAX5065/67 toc17
VIN = +24V
5.0
VIN = +12V
NO DRIVER
VCC LINE REGULATION
5.25
MAX5065/67 toc16
5.20
5.10
0.1
4.9
FREQUENCY (MHz)
ILOAD (A)
5.15
0.175
-135
GAIN
0.5
1.50
0.200
45
-90
1.0
1.55
90
2.0
RF/RIN = 10
1.60
4.8
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGE
MAX5065/67 toc14
2.5
1.75
4.7
VIN (V)
3.5
MAX5065/67 toc13
1.90
6
4.8
MAX5065/67 toc15
1.3
MAX5065/67 toc18
1.2
ERROR (%)
1.1
PHASE (deg)
1.0
VOUT (V)
0.1
0.1
45
VCC (V)
MAX5065/MAX5067
+0.6V
10 12 14 16 18 20 22 24 26 28
8
9
10
VIN (V)
_______________________________________________________________________________________
11
VIN (V)
12
13
+0.6V
+3.3V
(
)
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
80
70
60
50
40
30
20
10
0
DL_
DH_
VIN = +12V
fSW = 250kHz
1
6
11
16
21
26
31
36
MAX5065/67 toc21
MAX5065/67 toc20
MAX5065/67 toc19
120
110
100
90
tR (ns)
tR (ns)
120
110
100
90
HIGH-SIDE DRIVER (DH_)
SINK AND SOURCE CURRENT
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
80
70
60
50
40
30
20
10
0
DL_
DH_
1.6A/div
DH_
VIN = +12V
CDH_ = 22nF
VIN = +12V
fSW = 250kHz
1
CDRIVER (nF)
6
11
16
21
26
100ns/div
36
31
CDRIVER (nF)
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz MAX5065/67 toc23
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
MAX5065/67 toc22
CLKOUT
5V/div
350kHz
DL_
1.6A/div
PLLCMP
200mV/div
250kHz
0
VIN = +12V
CDL_ = 22nF
VIN = +12V
NO LOAD
100ns/div
100µs/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz MAX5065/67 toc24
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz MAX5065/67 toc25
CLKOUT
5V/div
CLKOUT
5V/div
250kHz
PLLCMP
200mV/div
500kHz
PLLCMP
200mV/div
150kHz
0
250kHz
VIN = +12V
NO LOAD
0
100µs/div
VIN = +12V
NO LOAD
100µs/div
_______________________________________________________________________________________
7
MAX5065/MAX5067
____________________________________________________________
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX5065/MAX5067
+0.6V
+3.3V
____________________________________________________________
(
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
HIGH-SIDE DRIVER (DH_)
FALL TIME
HIGH-SIDE DRIVER (DH_)
RISE TIME
MAX5065/67 toc27
MAX5065/67 toc26
DH_
2V/div
DH_
2V/div
VIN = +12V
CDH_ = 22nF
VIN = +12V
CDH_ = 22nF
40ns/div
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIME
LOW-SIDE DRIVER (DL_)
FALL TIME
MAX5065/67 toc28
MAX5065/67 toc29
DL_
2V/div
VIN = +12V
CDL_ = 22nF
DL_
2V/div
VIN = +12V
CDL_ = 22nF
40ns/div
40ns/div
OUTPUT RIPPLE
INPUT STARTUP RESPONSE
MAX5065/67 toc30
MAX5065/67 toc31
VPGOOD
1V/div
VOUT
1V/div
VOUT
(AC-COUPLED)
10mV/div
VIN
5V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
VIN = +12V
VOUT = +1.75V
IOUT = 52A
500ns/div
8
2ms/div
_______________________________________________________________________________________
)
+0.6V
+3.3V
(
)
ENABLE STARTUP RESPONSE
REVERSE CURRENT SINK
vs. TEMPERATURE
LOAD-TRANSIENT RESPONSE
MAX5065/67 toc33
2.8
VPGOOD
1V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
2.7
VEXTERNAL = +3.3V
IREVERSE (A)
VOUT
1V/div
MAX5065/67 toc34
MAX5065/67 toc32
VOUT
50mV/div
VEN
2V/div
2.6
2.5
VEXTERNAL = +2V
VIN = +12V
VOUT = +1.75V
ISTEP = 8A TO 52A
tRISE = 1µs
2.4
VIN = +12V
VOUT = 1.5V
R1 = R2 = 1.5mΩ
2.3
1ms/div
-40
40µs/div
-15
10
35
60
85
TEMPERATURE (°C)
REVERSE CURRENT SINK AT INPUT TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V)
REVERSE CURRENT SINK AT INPUT TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5065/67 toc36
MAX5065/67 toc35
REVERSE
CURRENT
10A/div
REVERSE
CURRENT
5A/div
0A
0A
R1 = R2 = 1.5mΩ
R1 = R2 = 1.5mΩ
200µs/div
200µs/div
REVERSE CURRENT SINK AT ENABLE TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V)
REVERSE CURRENT SINK AT ENABLE TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5065/67 toc37
R1 = R2 = 1.5mΩ
MAX5065/67 toc38
REVERSE
CURRENT
5A/div
REVERSE
CURRENT
10A/div
0A
0A
R1 = R2 = 1.5mΩ
200µs/div
200µs/div
_______________________________________________________________________________________
9
MAX5065/MAX5067
____________________________________________________________
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX5065/MAX5067
+0.6V
+3.3V
___________________________________________________________________
MAX5065
MAX5067
1, 13
39, 16
CSP2,
CSP1
2, 14
40, 17
CSN2,
CSN1
3
41
PHASE
4
42
PLLCMP
5, 7
43, 7
CLP2,
CLP1
6
5, 20, 35
SGND
8
10
SENSE+
9
11
SENSE-
10
12
DIFF
11
13
EAN
12
14
EAOUT
15
19
EN
16, 26
22, 34
BST1,
BST2
17, 25
23, 32
DH1,
DH2
18, 24
24, 31
LX1, LX2
19, 23
25, 30
DL1, DL2
10
20
27
VCC
21
28
IN
22
29
PGND
CSP_
CSN_
18
CSP_
PHASE
CLKOUT
90°
CLKIN/DH1
PHASE SGND
PHASE
60°
(
VCC
120°
)
RC
MAX5065
+0.8V
SENSE+
MAX5067
+0.6V
SENSESENSE-
VOUT-
PGND
DIFF
SGND
EN
5µA
BST_
FET
LX_
0.47µF
MOSFET
MOSFET
MOSFET
+5V
SGND
VCC
+5V
RC
VCC
IN
IN
VCC
IN
4.7µF
0.1µF
2.2Ω
0.1µF
MOSFET
______________________________________________________________________________________
PGND
+0.6V
+3.3V
MAX5065
MAX5067
27
36
CLKOUT
28
38
CLKIN
—
6
OVPIN
—
8
OVPOUT
—
9
PGOOD
—
1, 2, 3, 4,
15, 18,
21, 33,
37, 44
N.C.
—
26
VDD
CLKOUT CLKIN
MAX5065/MAX5067
CMOS
SGND
SGND
PHASE
125kHz
CLKIN
SGND
500kHz CLKIN
+0.8V
(
600kHz
)
CLKOUT
CLKIN
250kHz
VCC
VCC
5µA
OVPIN
VOUT
OVPOUT DH_
GND
OVPIN
DL_
EN
OVPOUT
(
SCR)
PGOOD
+8%
VCC
PGND
1Ω
MAX5065/MAX5067
buck
PWM
(
0.1µF
+3.3V (MAX5065)
+0.8V
+3.3V
VIN VCC VDD
)
60° (3
MAX5065/MAX5067
)
MAX5065/MAX5067
(ICC)
(IDD)
MAX5065/MAX5067
(VEA)
SENSE+
SENSE-
1µF
PGOOD
MAX5065/MAX5067
+5.5V
+8V +28V
+5V
(VCC)
V CC
VCC
+5V
4.7µF 0.1µF ESR
(
MAX5065/MAX5067
90° (
)
VDD
EN
VCC
+0.6V
(MAX5067)
____________________________
-10%
+4.75V
+8V
1
+5V
80mA
VCC SGND
2 3)
VCC
ICC
(IQ)
PD = VIN x ICC
ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4)
______________________________________________________________________________________
(1)
(2)
11
MAX5065/MAX5067
________________________________________________________________
MAX5065/MAX5067
+0.6V
+3.3V
___________________________________________________________________
EN
IN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
TO INTERNAL CIRCUITS
VCC
TO INTERNAL CIRCUITS
CSP1
CSN1
CSP1
DRV_VCC
SHDN
CSN1
CLP1
DH1
CLP1
CLK
SGND
BST1
LX1
PHASE 1
DL1
MAX5065
GMIN
PGND
PHASELOCKED
LOOP
CLKIN
RAMP1
PHASE
CLKOUT
PLLCMP
RAMP
GENERATOR
DIFF
SENSE-
0.6V
DIFF
AMP
PGND
SENSE+
EAOUT
EAN
ERROR
AMP
DRV_VCC
SHDN
CLK
VREF = 0.6V + VCM
PGND
RAMP2
GMIN
CLP2
CSN2
CSP2
12
PHASE 2
DH2
LX2
CLP2
CSN2
CSP2
______________________________________________________________________________________
DL2
BST2
+0.6V
+3.3V
(
)
EN
IN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
VCC
TO INTERNAL CIRCUITS
VDD
CSP1
CSP1
CSN1
DRV_VCC
SHDN
BST1
CSN1
CLP1
DH1
CLP1
CLK
SGND
LX1
PHASE 1
DL1
MAX5067
GMIN
PGND
PHASELOCKED
LOOP
CLKIN
RAMP1
PHASE
RAMP
GENERATOR
CLKOUT
CLP1
PLLCMP
DIFF
DIFF
CLP2
SENSE-
+0.6V
PGOOD
POWERGOOD
GENERATOR
N
PGND
VREF
DIFF
AMP
SENSE+
EAOUT
0.8V
EAN
OVPOUT
OVP
COMP
ERROR
AMP
DRV_VCC
SHDN
CLK
VREF = 0.8V + VCM
PGND
RAMP2
OVPIN
CLP2
CSN2
CSP2
GMIN
PHASE 2
DH2
LX2
CLP2
DL2
CSN2
BST2
CSP2
______________________________________________________________________________________
13
MAX5065/MAX5067
________________________________________________________________
1.
14
RB
RA
RX
C43
VCC
C44
VIN
Rf
RIN
C36
R12
EN
C32
VIN = +5V
______________________________________________________________________________________
C33
R5
R6
C35
CLP2
PLLCMP CLKIN
R4
C31
CLP1
EAOUT
EAN
DIFF
OVPIN
OVPOUT
VCC
VCC
IN
R13
C42
C34
PGND SGND PHASE PGOOD CSN2 CSP2
VCC
BST2
DL2
LX2
DH2
VDD
VCC
BST1
DL1
LX1
SENSE- SENSE+ CSN1 CSP1
DH1
C1, C2
MAX5067
IN
VIN = +5V
Q4
Q3
VIN
C39
R3
Q2
Q1
VIN
D2
C13
C8
C11
C40
D1
L2
C41
L1
R11
D4
D3
C12
PGOOD
C3–C7
R2
IN
R1
C38
C14
C15
C16
C25
C26,
C30,
C37
LOAD
RL
RH
VOUT = +0.8V TO
+3.3V AT 52A
MAX5065/MAX5067
+0.6V
+3.3V
2.
VRM
VIN = +8V
C44
RX
VCC
C43
Rf
RIN
C36
R12
C33
R5
R6
C35
CLP2
PLLCMP CLKIN
R4
C31
CLP1
EAOUT
EAN
DIFF
OVPIN
OVPOUT
EN
C32
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
RB
RA
VIN
VCC
C42
C34
VCC
BST2
DL2
LX2
DH2
VDD
VCC
BST1
DL1
LX1
SENSE- SENSE+ CSN1 CSP1
DH1
PGND SGND PHASE PGOOD CSN2 CSP2
MAX5067
IN
R13
C1, C2
VIN = +8V TO +28V
Q4
Q3
VIN
C39
R3
Q2
Q1
VIN
D2
C13
C8–
C11
C40
C41
D1
C12
PGOOD
C3–C7
R11
L2
C38
L1
D4
D3
R2
R1
C14,
C15
C16–
C25
C26–
C30,
C37
LOAD
RL
RH
VOUT = +1.8V AT 52A
MAX5065/MAX5067
VCC
+0.6V
+3.3V
+28V
______________________________________________________________________________________
15
MAX5065/MAX5067
+0.6V
+3.3V
SENSESENSE+
3
CSN1
PHASE
CSP1
9
8
14
13
VIN
15 EN
R1
VIN = +12V
C3–C7
21 IN
C1,
C2
C39
DH1
LX1
VCC
28
DL1
17
Q1
L1
18
19
C12
Q2
CLKIN
R2
D1
MAX5065
BST1 16
4
PLLCMP
R4
C25
D3
+1.8V AT 60A
VOUT
VCC 20
C34
C32
C31
RH
C26
R7
VCC
10
11
R8
RX
12
DIFF
D4
VIN C8–C11
EAN
EAOUT
R6
7
CLP1
C16–C24, LOAD
C33
RL
DH2 25
Q1
L2
LX2 24
C29
C14,
C15
DL2 23
R3
C13
Q2
D2
C30
5
C28
C27
BST2 26
CLP2
R5
1
6
22
SGND
PGND
CSP2
CSN2
2
3. MAX5065
16
______________________________________________________________________________________
+0.6V
MOSFET
)
+5V
VCC
f SW
IN
MAX5065/MAX5067
( 4)
VCC
(IPHASE1
(UVLO)/
MAX5065/MAX5067
UVLO
200mV
+4.0V
+4.5V
UVLO
+4V
UVLO
MAX5065/MAX5067
4mA
(CLP1
(CA_)
PWM
CA_
RS
CEA_
(EAOUT)
CLP1
CEA_
CPWM_
CEA_
PWM
C36)
R6)
IPHASE2)
+2V
0
CLP2)
(R5
(RS)
(CEA_)
(CPWM_)
18
CA_
CEA_
CA_
CLP2 RC
PWM
(C34
(C33 C35)
1
2) CLP_
CLP_
(DIFF AMP)
(
(VEA)
VEA
(EAN) VEA
MAX5067
+0.8V
+0.6V
MAX5065
250kHz
500kHz
CLKIN
(PWM)
PWM
CLKIN
SGND
CLKIN
VCC
(PLL)
180°
2VP-P
200ns
CLKOUT
120°
SGND
PLLCMP
PWM
(
VEA
4)
VEA
(
)
(CA_)
1mV
CMOS
CLKIN
CLKIN
MAX5065/MAX5067
QG1 QG2 QG3 QG4
I Q 4mA (
+3.3V
18
-0.3V
+3.6V
PWM
CLKOUT
CLKIN
PHASE
PHASE
VCC
PHASE
90°
PHASE
60°
CLKIN
(
)
(
5)
48mV
(48mV)
MAX5065/MAX5067
PLL
112mV
260ns
______________________________________________________________________________________
17
+3.3V
CLP_
(
MAX5065/MAX5067
(CEA_)
320µA
CLP1 CLP2
CLP1 CLP2
(
4)
CEA_
PWM
(
gm
(DIFF AMP)
PWM
(
4)
(
VEA
(DIFF)
3MHz
SENSE+ SENSEMAX5065
+0.6V
MAX5067
+0.8V
SENSE+
SENSE-
)
)
PWM
PWM
2VP-P
5)
550µs
R-S
(CPWM)
R-S
(DH_)
CCF
MAX5065/
MAX5067
CLP1
CSP1
CSN1
RCF
CCFF
CA1
RF*
VIN
IPHASE1
CEA1
SENSE+
CPWM1
DIFF
AMP
DRIVE 1
RS
RIN*
VEA
SENSE-
VOUT
VIN
COUT
CEA2
VREF
CPWM2
DRIVE 2
IPHASE2
RS
CLP2
CSP2
CA2
CSN2
MAX5065/MAX5067
+0.6V
CCF
RCF
*RF AND RIN ARE EXTERNAL.
CCCF
4. MAX5065/MAX5067
18
______________________________________________________________________________________
LOAD
+0.6V
+3.3V
MAX5065/MAX5067
MAX5065
VEA
(VREF)
VEA
VCM (+0.6V)
RX = [VCC − 1.2] ×
RF
0.6V
(4)
RX = [VCC − 1.4] ×
RF
0.8V
(5)
+0.9V
MAX5067
VEA
(18)
RF RIN
( 4)
 R  R +R 
L ×V
VOUT(NL) = 1 + IN  ×  H

REF
RF   RL 

RH RL
(
(MAX5065) 0.8V (MAX5067)
VOUT
1
2)
VEA
(3)
V REF = 0.6V
VOUT(NOM)
(VOUT(NOM))
VCC
ESR
RX
EAN
RX
DRV_VCC
PEAK-CURRENT
COMPARATOR
112mV
CLP_
CSP_
AV = 18
Gm =
500µS
CSN_
BST_
PWM
COMPARATOR
GMIN
S
Q
DH_
RAMP
LX_
2 x fs (V/s)
CLK
R
DL_
PGND
SHDN
5.
Q
(
1/2)
______________________________________________________________________________________
19
+3.3V
(1 / (R4 x C32))
VOLTAGE-POSITIONING WINDOW
MAX5065/MAX5067
+0.6V
VCNTR + ∆VOUT/2
VCNTR
VCNTR - ∆VOUT/2
R4 = 7.5kΩ
PLL
C31 = 4.7nF
C32 = 470pF
PLL
200µs
MAX5065/MAX5067
PLL
PLLCMP
PWM
MOSFET
FULL LOAD
1/2 LOAD
NO LOAD
LOAD (A)
(DH_)
MOSFET
(DH_
(DL_)
1 2 3)
MOSFET
(
DL_)
N
6.
(
VEA
(∆VOUT)
CPU
MOSFET (Q1
50%
6)
R DS(ON)
MOSFET (Q2 Q4)
Q3)
RDS(ON)
MAX5065/MAX5067
I
× RIN RH + RL
∆VOUT = OUT
×
RL
2 × GC × RF
MOSFET
(6)
60ns
BST_
MAX5067
GC =
RIN RF
RS
0.05
RS
VEA
ESR
VCC
GC
(
VCC
MOSFET
PWM
250kHz
CLKIN
PLL
V CC
CLKIN
SGND
500kHz
PLL
20µA
VDD
MOSFET
VDD
(7)
PLLCMP
(R4)
PLL
( 1)
(1 / [R4 x (C31 + C32)])
SGND
CA2)
BST_ LX_
0.47µF
4.7µF 0.1µF
ESR
SGND)
MAX5065/MAX5067
PC
VEA
VCM = +0.6V)
(
4)
(C31)
(C32)
20
50mV/RS
______________________________________________________________________________________
+0.9V (
(CA1
18
I LIMIT =
+0.6V
+3.3V
MAX5067
(UVP)
(OVP)
(MAX5067)
PGOOD
90%
1)
(
8)
108%
2)
(MAX5067)
OVP
OVPIN
+0.8V
MOSFET
OVPOUT
SCR
MAX5067
(
3) EN
(DIFF)
7)
1.08
0.9
OVP
MOSFET
OVP
(CLP_)
2.0V
PGOOD
10kΩ
SCR
SCR
VCC
0.2V
4mA
MOSFET
PGOOD
SCR
I2t
DIFF
OVPIN
RC
(
1 2)
OVP
SGND
 R 
VOVP = 1 + A  × 0.8V
 RB 
(8)
DIFF
8% OF VREF
PGOOD
VREF
RA
10% OF VREF
VOUT
OVPIN
RB
CLP1
MAX5067
DIFF
+2.0V
RIN
EAN
RF
EAOUT
CLP2
PHASE-FAILURE DETECTION
7. OVP
8. Power-Good
(MAX5067)
______________________________________________________________________________________
21
MAX5065/MAX5067
Power-Good
MAX5065/MAX5067
+0.6V
+3.3V
CSN1
CSP1
SENSE+
VIN
SENSEDH1
VCC
LX1
PHASE
DL1
VCC
CLKIN
VIN
VIN
MAX5065/
MAX5067
DH2
LX2
IN
DL2
DIFF
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
VIN
DH1
VCC
LX1
PHASE
DL1
MAX5065/
MAX5067
IN
VIN
DH2
DIFF
LX2
LOAD
DL2
VOUT = +0.6V (MAX5065)
VOUT = +0.8V (MAX5067)
EAN
CSP2
EAOUT
CSN2
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
VIN
DH1
VCC
LX1
PHASE
DL1
MAX5065/
MAX5067
IN
VIN
DH2
DIFF
LX2
DL2
EAN
EAOUT
CSP2
CSN2
PGND SGND CLKOUT
TO OTHER MAX5065/MAX5067s
9.
22
MAX5065/MAX5067
______________________________________________________________________________________
+0.6V
+3.3V
MAX5065/MAX5067
VIN = +12V
VIN
C1, C2
2 x 47µF
VCC
C31
R13
2.2Ω
C32
C43
R12
C42
0.1µF
R4
VIN
C3–C7
5 x 22µF
OVPOUT
PLLCMP CLKIN
IN
SENSE- SENSE+ CSN1 CSP1
Q1
DH1
L1
0.6µH
R1
1.35mΩ
LX1
DL1
C12
0.47µF
Q2
D1
D3
BST1
VCC
VCC
R3
C41
0.1µF
C38
4.7µF
C39
1µF
C40
1µF
D4
EN
VDD
OVPIN
R7
VIN
MAX5067
(MASTER)
DIFF
4 x 22µF
C8–C11
EAN
DH2
R8
Q3
L2
0.6µH
EAOUT
R2
1.35mΩ
LX2
DL2
C13
0.47µF
Q4
D2
CLP1
CLP2
PGND
SGND
CLKOUT
PHASE PGOOD
CSN2 CSP2
BST2
R11
R5
R6
C36
C34
PGOOD
VCC
C33
C35
R17
C16–C25,
C57–C60
2 x 270µF
VIN
C61
0.1µF
EN
PLLCMP
IN
C26–C30,
C37
6 x 10µF LOAD
C14, C15,
C44, C45
2 x 100µF
R24
2.2Ω
C70
C71
RA
RL
RB
VOUT = +0.8V TO
+3.3V AT 104A
C46–C50
5 x 22µF
CLKIN
RH
SENSE- SENSE+ CSN1 CSP1
L3
0.6µH
Q5
DH1
R14
1.35mΩ
LX1
DL1
C55
0.47µF
Q6
D5
D7
BST1
VCC
R16
OVPOUT
VDD
OVPIN
MAX5067
(SLAVE)
C65
4.7µF
C64
0.1µF
C62
1µF
C63
0.1µF
D8
R20
VIN
DIFF
C51–C54
4 x 22µF
EAN
DH2
R21
L4
0.6µH
Q7
EAOUT
R15
1.35mΩ
LX2
DL2
C56
0.47µF
Q8
D6
CLP1
CLP2
R19
R18
C66
SGND
PHASE
PGOOD
C69
C67
10.
PGND
CSN2 CSP2
BST2
VCC
C68
(VIN = +12V VOUT = +0.8V
+3.3V/104A)
______________________________________________________________________________________
23
MAX5065/MAX5067
+0.6V
+3.3V
(MAX5067)
1
/
±10%
CLP_
PWM
-
CLP_
(
MOSFET
(CLP1 CLP2)
CLP1 CLP2
1250
8)
2.0V
PGOOD
VIN = +12V
VOUT = +1.8V
IOUT(MAX) = 52A
FSW = 250kHz
-
(∆IL) = 10A
1
MAX5067
10)
RMS
90°
PHASE
)
SENSE+
NPH ≈ K/D
SGND
K=1
2
3
(9)
D = VOUT/VIN
K NPH
VOUT = +1.8V
CLKOUT
CLKOUT
SENSE-
VIN = +12V
25A
NPH = K/D
DIFF
DIFF (
)
MAX5067
+12V
(MAX5065) +0.8V
104A
10
+0.6V
+3.3V (MAX5067)
MAX5065/MAX5067
MAX5065/MAX5067
24
+3.3V
(
)
180A
9
CLKIN
CLKIN
2
-
MAX5065/
PLL
)
1)
3 MAX5065/
(
9
3
MAX5067
PHASE
(
60°
(
(
MOSFET
/
/
180°
______________________________________________________________________________________
+0.6V
+3.3V
MAX5065/MAX5067
1.
DESIGNATION
QTY
C1, C2
2
DESCRIPTION
47µF,16V X5R input-filter capacitors TDK C5750X5R1C476M
C3–C11
9
22µF, 16V input-filter capacitors TDK C4532X5R1C226M
C12, C13
2
0.47µF, 16V capacitors TDK C1608X5R1A474K
C14, C15
2
100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3
C16–C25
10
270µF, 2V output-filter capacitors Panasonic EEFUE0D271R
C26–C30, C37
6
10µF, 6.3V output-filter capacitors TDK C2012X5R05106M
C31
1
4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ
C32, C34, C36
3
470pF, 16V capacitors Murata GRM1885C1H471JAB01
C33, C35, C43
3
0.01µF, 50V X7R capacitors Murata GRM188R71H103KA01
C38
1
4.7µF, 16V X5R capacitor Murata GRM40-034X5R475k6.3
C39
1
0.1µF, 10V Y5V capacitor Murata GRM188F51A105
C40, C41, C42
3
0.1µF, 16V X7R capacitors Murata GRM188R71C104KA01
C44
1
100pF—OVPIN capacitor
D1, D2
2
Schottky diodes ON-Semiconductor MBRS340T3
D3, D4
2
Schottky diodes ON-Semiconductor MBR0520LT1
L1, L2
2
0.6µH, 27A inductors Panasonic ETQP1H0R6BFX
Q1, Q3
2
Upper-power MOSFETs Vishay-Siliconix Si7860DP
Q2, Q4
2
Lower-power MOSFETs Vishay-Siliconix Si7886DP
R1, R2
4
Current-sense resistors, use two 2.7mΩ resistors in parallel, Panasonic ERJM1WSF2M7U
R3, R13
2
2.2Ω ±1% resistors
7.5kΩ ±1% resistor
R4
2
R5, R6
2
1kΩ ±1% resistors
RIN
1
4.99kΩ ±1% resistor
Rf
1
37.4kΩ ±1% resistor
R11
1
10kΩ ±1% resistor
R12
1
10kΩ ±1% resistor
RA
1
See the Overvoltage Protection (MAX5067) section
RB
1
See the Overvoltage Protection (MAX5067) section
RH
1
See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections
RL
1
See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections
RX
1
Open circuit
2.
SUPPLIER
Murata
PHONE
FAX
770-436-1300
770-436-3030
WEBSITE
www.murata.com
ON Semiconductor
602-244-6600
602-244-3345
www.on-semi.com
Panasonic
714-373-7939
714-373-7183
www.panasonic.com
TDK
Vishay-Siliconix
847-803-6100
847-390-4405
www.tcs.tdk.com
1-800-551-6933
619-474-8920
www.vishay.com
______________________________________________________________________________________
25
MAX5065/MAX5067
+0.6V
+3.3V
IL _ PEAK =
-
0.051V ∆IL
+
2
RSENSE
(12)
RSENSE
MOSFET
/
MOSFET
VIN = +5V
250kHz
500kHz
VIN ≥ +12
MOSFET
RDS(ON)
-
MOSFET
(∆IL)
MOSFET
RMS
LMIN =
(VINMAX − VOUT ) × VOUT
(10)
VIN × fSW × ∆IL
∆IL
40%
MAX5065/MAX5067
DH1 DH2 DL1 DL2
MAX5067
VIN VCC VDD
(CV 2)
∆IL
VIN(MAX) = +13.2V VOUT = +1.8V ∆IL =
fSW = 250kHz
(13.2 − 1.8) × 1.8 = 0.6µH
13.2 × 250k × 10
MAX5065/MAX5067
26
(11)
I2R
PDMOS − HI = (QG × VDD × fSW ) +
(13)
 VIN × IOUT × ( t R + t F ) × fSW 
2

 + 1.4RDS(ON) × I RMS − HI
4


QG
LMIN =
/
MOSFET
MOSFET RDS(ON)
RMS
MOSFET
MOSFET
(PDMOS_)
∆IL
∆I L
10A
MAX5065/
RDS(ON) tR
+25°C
IRMS−HI =
tF
(I
MOSFET
)
D
2
2
DC + I PK + IDC × IPK ×
(14)
3
D = VOUT/VIN IDC = (IOUT - ∆IL)/2 IPK = (IOUT +
∆IL)/2
______________________________________________________________________________________
+0.6V
+3.3V
(15)
2
2×C

2
OSS × VIN × fSW + 1.4R
×
I
RMS − LO


DS(ON)
3


COSS
MOSFET
IRMS−LO =
-
-
(
)
I2DC + I2PK + IDC × IPK ×
(1− D)
(16)
∆VQ (
ESR
MOSFET RMS
MOSFET
25°C
ESR
(V OUT =
9.9A
70%
ESR
ESRIN =
TJ = PDMOS x θJ-A + TA
3.
(17)
(∆VESR )
 IOUT ∆IL 
+


 N
2 
(18)
IOUT
× D(1 − D)
CIN = N
∆VQ × fSW
-
NUMBER OF
PHASES (N)
∆VESR (
ESR
3
30%
+1.8V)
24.1A
)
)
DUTY
CYCLE (D)
EQUATION FOR ∆IP-P
2
< 50%
V (1 − 2D)
∆I = O
L × fSW
2
> 50%
∆I =
IOUT
(19)
N
VOUT = +1.8V
100mV
200µF
ESR
1mΩ
(VIN − VO )(2D − 1)
L × fSW
4
0 to 25%
V (1− 4D)
∆I = O
L × fSW
4
25% to 50%
V (1 − 2D)(4D − 1)
∆I = O
2 × D × L × fSW
4
> 50%
V (2D − 1)(3 − 4D)
∆I = O
D × L × fSW
6
< 17%
V (1− 6D)
∆I = O
L × fSW
-
RMS
ESR
3
-
(∆IP-P)
NPH = K / D
______________________________________________________________________________________
27
MAX5065/MAX5067
PDMOS − LO = (QG × VDD × fSW ) +
MAX5065/MAX5067
+0.6V
+3.3V
VCLR
ESR
(tRESPONSE)
ESR
IREVERSE =
SP
2 × VCLR
RSENSE
(24)
/
IREVERSE
(∆VOUT)
50%
ESR
ESR
ESROUT =
∆VESR
ISTEP
I
×t
COUT = STEP RESPONSE
∆VQ
ISTEP
(20)
(21)
MAX5067
4) IPHASE1
MAX5065/
(
VEA
IPHASE2
VEA
RF
RIN
VEA
RF
tRESPONSE
RF =
IOUT × RIN
N × GC × ∆VOUT
(25)
0.05
RS
(26)
MAX5065/MAX5067
MAX5065/MAX5067
(IL-PK)
45mV (
)
GC =
GC
0.045
RSENSE =
IOUT
N
PDR =
PDR
RSENSE
2.5 × 10−3
RSENSE
N
(
(22)
RCF
(23)
RCF ≤
5%
PC
2 × fSW × L × 102
VOUT × RSENSE
RCF
RSENSE = 1.35mΩ
CCF
RCF
fZ
VBUS
28
CEA
)
MAX5065/MAX5067
(fP)
______________________________________________________________________________________
(27)
12kΩ
+0.6V
CCFF
CCF =
7)
1
2 × π × fZ × RCF
CCFF =
VCC
MOSFET
V CC
MAX5065/MAX5067
(28)
1
2 × π × fP × RCF
(29)
MAX5065/MAX5067
CCF
+3.3V
MAX5065/MAX5067
PGND
MOSFET
8)
9)
PC
1)
VIN
VCC
MAX5065/MAX5067
10)
MOSFET
11)
4oz
PC
2)
MOSFET
____________________________
3)
MOSFET
4)
5)
6)
TRANSISTOR COUNT: 5451
PROCESS: BiCMOS
MOSFET
SGND
PC
PGND
CS+
CSSENSE+
SENSE-
____________________________
PART
OUTPUT
MAX5065
Adjustable +0.6V to +3.3V
MAX5067
Adjustable +0.8V to +3.3V with OVP, PGOOD,
Phase Failure Detector
______________________________________________________________________________________
29
+3.3V
CSP2 1
CSN2 2
27 CLKOUT
26 BST2
PLLCMP 4
25 DH2
CLP2 5
SGND 6
24 LX2
MAX5065
23 DL2
22 PGND
CLP1 7
BST2
SGND
N.C.
CLKOUT
CLKIN
CSN2
CSP2
PHASE
44 43 42 41 40 39 38 37 36 35 34
28 CLKIN
PHASE 3
CLP2
TOP VIEW
PLLCMP
N.C.
___________________________________________________________________
N.C.
1
33
N.C.
N.C.
2
32
DH2
N.C.
3
31
LX2
N.C.
4
30
DL2
SGND
5
29
PGND
OVPIN
6
28
IN
CLP1
7
27
VCC
OVPOUT
8
26
VDD
MAX5067
SENSE+ 8
21 IN
SENSE- 9
20 VCC
PGOOD
9
25
DL1
DIFF 10
19 DL1
SENSE+
10
24
LX1
EAN 11
18 LX1
SENSE-
11
23
DH1*
EAOUT 12
17 DH1
CSP1 13
16 BST1
CSN1 14
15 EN
28 SSOP
N.C.
BST1
SGND
EN
N.C.
CSN1
N.C.
CSP1
EAOUT
EAN
12 13 14 15 16 17 18 19 20 21 22
DIFF
MAX5065/MAX5067
+0.6V
44 THIN QFN*
*CONNECT THE THIN QFN EXPOSED PAD TO SGND GROUND PLANE.
30
_____________________________________________________________________________________
+0.6V
+3.3V
www.maxim-ic.com/packages )
SSOP.EPS
2
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
D
0.20
0.09
0.004 0.008
SEE VARIATIONS
E
0.205
e
0.212
0.0256 BSC
5.20
MILLIMETERS
INCHES
D
D
D
D
D
5.38
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
A1
L
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
______________________________________________________________________________________
1
31
MAX5065/MAX5067
___________________________________________________________________
(
+3.3V
_______________________________________________________________
(
)
www.maxim-ic.com/packages )
(
32, 44, 48L QFN.EPS
MAX5065/MAX5067
+0.6V
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
E
CL
(NE-1) X e
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
A1
A2
e
DALLAS
A
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
C
1
2
DALLAS
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L THIN QFN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
Maxim
Maxim
REV.
C
2
2
Maxim
32 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2003 Maxim Integrated Products
Printed USA
Maxim Integrated Products, Inc.