Evaluates: MAX3680 MAX3680 Evaluation Kit _______________General Description ____________________________Features

19-1212; Rev 0; 3/97
MAX3680 Evaluation Kit
The MAX3680 evaluation kit (EV kit) simplifies evaluation of the MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The EV kit requires only a +3.3V supply, and
includes all the external components necessary to interface with 3.3V PECL/TTL logic. The board can be connected directly to the output of a clock-and-data-recovery circuit (such as the MAX3675) and to the TTL input
of an overhead termination circuit. It can also be used
with a signal generator and an oscilloscope to evaluate
the MAX3680’s basic functionality.
____________________________Features
♦ Single +3.3V Supply
♦ Inputs Terminated for Interfacing with 3.3V PECL
♦ Outputs Configured for 50Ω or High-Impedance
Interface
♦ Fully Assembled and Tested
______________Ordering Information
PART
MAX3680EVKIT-SO
TEMP. RANGE
-40°C to +85°C
BOARD TYPE
Surface Mount
____________________Component List
DESIGNATION QTY
DESCRIPTION
4
0.1µF ceramic capacitors
_______________Detailed Description
C5
1
33µF, 10V tantalum capacitor
AVX TAJC336K010 or
Sprague 293D336X0010C2
C6
1
2.2µF tantalum capacitor
AVX TAJA225K010 or
Sprague 293D225X0010A2
The MAX3680 EV kit simplifies evaluation of the
MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The
EV kit operates from a single +3.3V supply and
includes all the external components necessary to interface with 3.3V PECL/TTL logic.
C7–C12
6
100pF ceramic capacitors
J3–J16
14
SMA connectors (PC edge mount)
L1
1
56nH inductor
Coilcraft 0805CS-560-XKBC
R1, R3, R5, R7
4
82Ω, 5% resistors
R2, R4, R6, R8
4
130Ω, 5% resistors
C1–C4
R9–R17
9
2.4kΩ, 5% resistors
+3.3V, GND
JR9–JR17
11
2-pin headers
U1
1
MAX3680EAI
None
1
MAX3680 data sheet
The TTL outputs (PCLK, PD_) can interface to either
50Ω or high-impedance inputs. To interface to 50Ω
inputs, connect the inputs directly to the SMA connectors labeled PCLK and PD0–PD7. This configuration
forms a 50-to-1 voltage divider that maintains a highimpedance load to each TTL output while interfacing to
50Ω. To interface to high-impedance inputs, connect
the inputs to the 2-pin headers at R9–R17, which provide direct connections to the TTL outputs.
______________Component Suppliers
SUPPLIER
PHONE
Each PECL input (SCLK+, SCLK-, SD+, SD-) is terminated on the EV board with the Thevenin equivalent of
50Ω to (VCC - 2V). These inputs can be driven directly
by any 3.3V PECL device's output, such as a clockand-data-recovery circuit (e.g., the MAX3675). The synchronization input (SYNC) is a TTL input.
FAX
AVX
(803) 946-0690
(803) 626-3123
Coilcraft
(847) 639-6400
(847) 639-1469
Sprague
(603) 224-1961
(603) 224-1430
Please indicate that you are using the MAX3680 when contacting the above component suppliers.
_____________Layout Considerations
To minimize propagation-delay skew, all PECL input
signal lines are 50Ω transmission lines of equal length.
To allow accurate characterization of the parallel-clock
to data-output delay, the output data lines (prior to the
series 2.4kΩ termination resistors) are matched and
kept as short as possible. Excluding the series termination resistor, each output data line measures approximately 3pF at the 2-pin header (JR9–JR17).
________________________________________________________________ Maxim Integrated Products
1
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For small orders, phone 408-737-7600 ext. 3468.
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Evaluates: MAX3680
_______________General Description
2
SCLK+
SD+
J5
R6
130Ω
R2
130Ω
SCLK-
C3
0.1µF
SD-
C1
0.1µF
J6
VCC
R5
82Ω
J4
VCC
R1
82Ω
R8
130Ω
R4
130Ω
GND
+3.3V
C5
33µF
10V
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE ZO = 50Ω
VCC
J3
VCC
C6
2.2µF
10V
C4
0.1µF
C2
0.1µF
PCLK
L1
56nH
J8
J7
R7
82Ω
R3
82Ω
SYNC
VCC
SCLK-
VCC
PCLK
GND
GND
SYNC
GND
VCC
U1
MAX3680
C8
100pF
SCLK+
VCC
SD-
SD+
VCC
VCC
C7
100pF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
C9
100pF
PD0
GND
PD1
VCC
PD2
GND
PD3
PD4
GND
PD5
VCC
PD6
GND
PD7
28
C10
100pF
R10
2.4k
R12
2.4k
R14
2.4k
VCC
C11
100pF
JR8
JR6
JR4
JR2
R16
2.4k
PD0
PD2
PD4
PD6
C12
100pF
J16
J14
J12
J10
VCC
JR7
JR5
JR3
JR1
R11
2.4k
R13
2.4k
R15
2.4k
R17
2.4k
J15
J13
J11
J9
PD1
PD3
PD5
PD7
Evaluates: MAX3680
MAX3680 Evaluation Kit
Figure 1. MAX3680 EV Kit Schematic
_______________________________________________________________________________________
www.BDTIC.com/maxim
MAX3680 Evaluation Kit
Evaluates: MAX3680
1.0"
1.0"
Figure 2. MAX3680 EV Kit Component Placement Guide
1.0"
Figure 3. MAX3680 EV Kit PC Board Layout—Component
Side*
1.0"
Figure 4. MAX3680 EV Kit PC Board Layout—Bottom
Silkscreen*
Figure 5. MAX3680 EV Kit PC Board Layout—Solder Side*
*Not to scale
_______________________________________________________________________________________
www.BDTIC.com/maxim
3
Evaluates: MAX3680
MAX3680 Evaluation Kit
1.0"
1.0"
Figure 6. MAX3680 EV Kit PC Board Layout—GND Plane*
Figure 7. MAX3680 EV Kit PC Board Layout— Power Plane*
*Not to scale
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
4 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
www.BDTIC.com/maxim