DS33Z11 Demo Kit Features General Description

Rev: 080508
DS33Z11 Demo Kit
Features
General Description
The DS33Z11 demo kit is an easy-to-use evaluation
board for the DS33Z11 Ethernet transport-over-serial
link device. The DS33Z11DK contains an integrated
Ethernet PHY and serial link. The serial link is
complete with transceiver, transformers, and network
connections. Maxim’s ChipView software is provided
with the demo kit, giving point-and-click access to
configuration and status registers from a Windows®based_PC. On-board LEDs indicate receive loss-ofsignal, queue overflow, Ethernet link, Tx/Rx, and
interrupt status.
♦
Demonstrates Key Functions of DS33Z11
Ethernet Transport Chipset
♦
On-Board DS2155 T1E1 SCT, DS3170 T3E3
SCT, Transformers, BNC Adapter, and RJ48
Network Connectors and Termination
♦
Provides Support for Hardware and Software
Modes
♦
Device Driver Provides Automatic
Configuration for T1, E1, T3, and E3 Modes
♦
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
the DS33Z11, DS2155, and DS3170 Register
Sets
♦
All DS33Z11 Interface Pins are Easily
Accessible for External Data Source/Sink
♦
LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status
♦
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
♦
Integrated Power-Supply Interfaces with 5.0V
Wall Adapter
Windows is a registered trademark of Microsoft Corp.
Demo Kit Contents
DS33Z11DK Main Board
5.0V Wall Adapter
BNC Adapter (2-pin coax)
CD-ROM
ChipView Software and Manual
DS33Z11DK Data Sheet
Configuration Files
Ordering Information
PART
DS33Z11DK
TYPE
DS33Z11 demo kit
Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
www.BDTIC.com/maxim
_______________________________________________________________________________ DS33Z11DK
Table of Contents
1.
SYSTEM FLOORPLAN.................................................................................................................... 3
2.
PCB ERRATA .................................................................................................................................. 3
3.
BASIC OPERATION ........................................................................................................................ 3
3.1
3.2
3.3
4.
POWERING UP THE DEMO KIT ..........................................................................................................3
INSTALLING AND RUNNING THE SOFTWARE.......................................................................................4
FILE LOCATIONS ..............................................................................................................................4
BASIC DS33Z11 INITIALIZATION (USED FOR ALL QUICK SETUPS).........................................5
4.1
4.2
4.3
4.4
QUICK SETUP #1 (DEVICE DRIVER + T1 OR E1) ...............................................................................5
QUICK SETUP #2 (DEVICE DRIVER + T3 OR E3) ...............................................................................5
QUICK SETUP #3 (DS2155 T1E1)...................................................................................................6
QUICK SETUP #4 (DS3170 T3E3)...................................................................................................6
5.
MONITOR AND CAPTURE ETHERNET TRAFFIC .........................................................................6
6.
LEDS CONFIGURATION SWITCHES AND JUMPERS..................................................................7
7.
ADDRESS MAP ............................................................................................................................. 10
8.
DS33Z11 INFORMATION .............................................................................................................. 10
8.1
8.2
DS33Z11DK INFORMATION...........................................................................................................10
TECHNICAL SUPPORT ....................................................................................................................10
9.
COMPONENT LIST........................................................................................................................ 11
10.
SCHEMATICS ................................................................................................................................ 14
11.
REVISION HISTORY...................................................................................................................... 15
List of Figures
Figure 1. Serial Jumper Configuration ......................................................................................................................... 7
List of Tables
Table 1. Main Board PCB Configuration ..................................................................................................................... 7
Table 2. Overview of Daughter Card Address Map................................................................................................... 10
Table 3. Component List............................................................................................................................................ 11
Rev: 080508
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1. System Floorplan
HARDWARE
MODE
SWITCHES
FOR
DS33Z11
SYSTEM
POWER (5.0 V)
ETHERNET PHY
MAGNETIC LEDS
AND JUMPERS
SYSCLK
REFLCK
OSC AND
SELECTION
ADDRESS
DATABUS
TESTPOINTS
USB
SERIAL PORT
(57600-8N1)
MICROPROCESSOR
FPGA
HARDWARE
MODE
SWITCHES
FOR
DS33Z11
DS33Z11
SERIAL
SELECTION
JUMPERS
SDRAM
OnCe DEBUG
DS3170
TRANSFORMER AND NETWORK
CONNECTIONS (DS3170)
DS2155
TRANSFORMER AND NETWORK
CONNECTIONS (DS2155)
2. PCB Errata
•
The following errata apply to DS33Z11DK02A0:
o DS33Z11 RSER and TSER wires were crossed. The schematic has been corrected, and PCBs
have been reworked to match the schematic.
o Header J04 pins 1, 3, 5, 7, 9 were not connected to VCC. The schematic has been corrected, and
PCBs have been reworked to match the schematic.
3. Basic Operation
Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly
from the EV kit software. Text in bold and underlined refers to items from the Windows operating system.
3.1
•
•
•
•
•
Powering Up the Demo Kit
Connect PCB 5.0V wall adapter to the power jack. LED DS11 should light.
Connect RS232 serial cable, or USB cable between the host PC and demo kit.
Connect the Ethernet port to an ordinary PC, or network test equipment. Either a patch or crossover cable may
be used. The link LED should turn on after connecting the cable.
Set Jumpers for software mode as described in Table 1 (short description follows).
• Top bank all GND (DCEDTE ….. SCANEN), with exception for MODEC0 which is at VCC
• A2, A1, A0 Jumpered to pins 2+3
• Right Bank all to VCC (AFCS, FULLDS, H1OS)
Upon power-up, the processor FPGA Status LEDs (DS07 green) will be lit. Interrupt LEDs (DS09 red) will not
be lit. DS33Z11 Queue overflow LEDs (DS10 red) will not be lit. PHY LINK LED (DS02/DS01 green) should be
lit if the Ethernet is connected.
Rev: 080508
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3.2
Installing and Running the Software
ChipView is a general-purpose program that supports a number of Maxim demo kits. To install the ChipView
software, run SETUP.EXE from the disk included in the DS33Z11DK box or from the zip file downloadable on our
website at www.maxim-ic.com/DS33Z11DK.
After installation, run the ChipView program with the DS33Z11DK board powered up and connected to the PC. If
the default installation options were used, one easy way to run ChipView is to click the Start button on the
Windows toolbar and select Programs→ChipView→ChipView. In the opening screen, click the Register View
button. Select the correct serial (or USB) port in the Port Selection dialog box, then click OK.
Next, the Definition File Assignment window appears. This window has subwindows to select definition files for
up to four separate boards on other Maxim evaluation platforms. In the active subwindow, select the DS33Z11.DEF
definition file from the list shown, or browse to find it in another directory. Press the Continue button.
After selecting the definition file, the main part of the ChipView window displays the DS33Z11 register map. Other
definition files may be loaded, and navigated to using the menu marked “Def File Selection”. To select a register,
click on it in the register map. When a register is selected, the full name of the register and its bit map are displayed
at the bottom of the ChipView window. Bits that are logic 0 are displayed in white, while bits that are logic 1 are
displayed in green.
The ChipView software supports the following actions:
•
•
•
•
•
•
3.3
Toggle a bit. Select the register in the register map and then click the bit in the bit map.
Write a register. Select the register, click the Write button, and enter the value to be written.
Write all registers. Click the Write All button and enter the value to be written.
Read a register. Select the register in the register map and click the Read button.
Read all registers. Click the Read All button.
Navigate to def file. Select from the Def File Selection menu
File Locations
This demo kit relies upon several supporting files, which are provided on the CD and are available as a zip file from
the Maxim website at www.maxim-ic.com/DS33Z11DK.
All locations are given relative to the top directory of the CD/zip file.
•
DS33Z11 register definition files and configuration files:
o .\cfg_demo_gui\DS33Z11_cfg_demo_gui\DS33Z11.def
o .\DS33Z11_cfg_demo_gui\SU_LI_PORT1.def
o .\DS33Z11_cfg_demo_gui\basic_config.mfg
•
DS2155 register definition files and configuration files:
o .\DS33Z11_cfg_demo_gui\te1_ds2155\DS2155.def
o .\DS33Z11_cfg_demo_gui\te1_ds2155\e1_gapclk_crc4_hdb3_nocas.ini
•
DS3170 register definition files and configuration files:
o .\DS33Z11_cfg_demo_gui\te3_ds3170\ _DS3170_Global.def
o .\DS33Z11_cfg_demo_gui\te3_ds3170\ DS3170_Port_LIU.def
o ….. 6 other low level def files ….
o .\DS33Z11_cfg_demo_gui\te3_ds3170\70_t3_sct_needscoaxlb.mfg
Rev: 080508
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4. Basic DS33Z11 Initialization (Used for All Quick Setups)
This section covers four basic methods for configuring the DS33Z11. Any one of these initializations can be used
with the following Quick Setup examples:
1. Device driver based. If pins J04.1+J04.2 are jumpered, the on-board device driver provides a basic
configuration for the DS33Z11. This enables traffic to pass from the Ethernet port to the serial port. Consult
the device driver documentation for further details. Sections 4.1 and 4.2 describe specific device driver
based configurations. To load the GUI interface for the device drivers go to the ChipView register mode
Tools menu and select Tools→Plugins→DS33XW Device Driver Demo.
2. Register-Based Configuration. Launch ChipView.exe and select Register View. Sections 4.3 and 4.4
describe specific configurations.
3. Hardware Mode. Set switches as described in the section for powering up the demo kit, then change the
following: HWMODE←3.3V, A0←3.3VV, A1←3.3V, A2←0V. This sets the part for LSB first, scrambling off,
HDLC encapsulated. At this point traffic will pass from the Ethernet port to the serial port. In this mode
broadcast frames are not passed (i.e., ping).
4. EEPROM mode is available with the DK, but is beyond the scope of this manual.
4.1
•
•
•
•
•
•
•
Install jumpers to place the serial interface in T1E1 mode as shown in Figure 1.
Complete the hardware configuration and one of the basic DS33Z11 configurations as described in the
previous section. (Ensure jumpers for J04.1+J01.2 are installed to enable the device driver).
Remove jumper between J04.9 and J04.10:
Install jumper between J04.7 and J04.8 for E1 mode. Remove jumper between J04.7 and J04.8 for T1 mode.
Place a loopback connector at the DS2155 network side; RLOS LED DS13 should go out.
At this point any packets sent to the DS33Z11 are echoed back. Incoming packets (i.e., ping) should cause the
ACT LED to blink.
To interact with the device driver select from the drop down menu:
• Tools→Plugins→Load Plugins. When asked if DLLs have already registered select yes
• Select Tools→Plugins→DS33Z44/11/41 Device Driver Demo
• A new form called ‘Zchip Configuration’ pops up.
• Preload basic configuration for the GUI by selecting File→Load Settings (in the ‘Zchip Configuration’ form).
Select the file named ‘basic_Config.eset’
4.2
•
•
•
•
•
•
•
Quick Setup #1 (Device Driver + T1 or E1)
Quick Setup #2 (Device Driver + T3 or E3)
Install jumpers to place the serial interface in T3E3 mode as shown in Figure 1.
Complete the hardware configuration and one of the basic DS33Z11 configurations as described in the
previous section. (Ensure jumpers for J04.1+J01.2 are installed to enable the device driver).
Install jumper between J04.9 and J04.10:
Install jumper between J04.7 and J04.8 for E3 mode. Remove jumper between J04.7 and J04.8 for T3 mode.
Place jumpers to loopback the DS3170 network side; RLOS LED DS12 should go out.
At this point any packets sent to the DS33Z11 are echoed back. Incoming packets (i.e., ping) should cause the
ACT LED to blink.
To interact with the device driver select from the drop down menu:
• Tools→Plugins→Load Plugins. When asked if DLLs have already registered select yes
• Select Tools→Plugins→DS33Z44/11/41 Device Driver Demo
• A new form called ‘Zchip Configuration’ pops up.
• Preload basic configuration for the GUI by selecting File→Load Settings (in the ‘Zchip Configuration’ form).
Select the file named ‘basic_Config.eset’
Rev: 080508
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4.3
•
•
•
•
•
•
Install jumpers to place the serial interface in T1E1 mode as shown in Figure 1.
Complete the hardware configuration and one of the basic DS33Z11 configurations as previously described.
Launch ChipView.exe (or use existing session if its already open) and select Register View. When prompted
for a definition file, pick the file named DS33Z11.def. After the definition file loads, go to the File menu and
select File→Memory Config File→Load .MFG file. When prompted, select the file named basic_config.mfg.
Load the definition file for the DS2155 by going to the file menu and selecting File→Definition Config File and
select the definition file named DS2155.def. After the definition file loads, go to the File menu and select
File→Reg Ini File→Load Ini File. When prompted, pick the file named e1_gapclk_crc4_hdb3_nocas.ini.
Place a loopback connector at the DS2155 network side; RLOS LED DS35 should go out.
At this point any packets sent to the DS33Z11 are echoed back. Incoming packets (i.e., ping) should cause the
ACT LED to blink.
4.4
•
•
•
•
•
•
Quick Setup #3 (DS2155 T1E1)
Quick Setup #4 (DS3170 T3E3)
Install jumpers to place the serial interface in T3E3 mode as shown in Figure 1.
Complete the hardware configuration and one of the basic DS33Z11 configurations as previously described.
Launch ChipView.exe (or use existing session if its already open) and select Register View. When prompted
for a definition file, pick the file named DS33Z11.def. After the definition file loads, go to the File menu and
select File→Memory Config File→Load .MFG file. When prompted, select the file named basic_config.mfg.
Load the definition file for the DS3170 by going to the file menu and selecting File→Definition Config File and
select the definition file named ds3170_global.def. After the definition file loads, go to the File menu and
select File→Memory Config File→Load .MFG file. When prompted, select the file named
70_t3_sct_needscoaxlb.mfg.
Place a loopback connector at the DS3170 network side.
At this point any packets sent to the DS33Z11 are echoed back. Incoming packets (i.e., ping) should cause the
ACT LED to blink.
5. Monitor and Capture Ethernet Traffic
•
•
•
•
Although ping is mentioned, it is *not* recommended. The ping command goes through the computer’s TCPIP
stack, and sometimes will not be sent out the PC’s network connector (i.e., if the PCs’ ARP cache is out of
date). Additionally ping requires two PCs, as a PC with only one adapter can not ping itself (a local ping gets
sent to ‘local host’ instead of out the connector). With that said, ping is still a valuable test once the prototyping
stage is complete.
Generation and capture of arbitrary (raw) packets can be easily accomplished using CommView. A time-limited
demo is available at the website www.tamos.com/products/commview.
Wireshark is an excellent (and free) packet capture utility. Download is available at www.wireshark.org.
Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This allows
for end-to-end testing using a single PC. When using two adapters the PC will have a different IP address for
each adapter. Test equipment will allow selection of either adapter. Operating system based network traffic will
be sent out the default adapter, usually this is the adapter that has recently had connection to a live network.
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Figure 1. Serial Jumper Configuration
HARDWARE LOOPBACK
(Unused, requires external wire)
T3E3 MODE (DS3170)
T1E1 MODE (DS2155)
JP20 RSER
JP20 RSER
JP20 RSER
JP21 TSER
JP21 TSER
JP21 TSER
JP22 TCLKI
JP22 TCLKI
JP22 TCLKI
JP23 RCLKI
JP23 RCLKI
JP23 RCLKI
External
Oscillator
6. LEDs Configuration Switches and Jumpers
The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 1 provides a
description of these components, given in order of appearance on the PCB. Component listing is given from left to
right, top to bottom, when the board is held with the Ethernet port at the top.
Table 1. Main Board PCB Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SW MODE
HW MODE
Installed
Installed
DESCRIPTION
J01
System Power
J02
Ethernet Connection
Installed
Installed
JP01
JP02
JP03
DP83848
AN0
AN1
AN_EN
Not
installed *
Not
installed*
DS02+DS01
DS04+DS03
DS06+DS05
Link (on for link)
Speed (on for 100)
Activity (blink for act)
On
On
Blink
On
On
Blink
JP12
DP83848 MDIX
VCC
VCC
JP14
DP83848 RMII
GND
GND
JP11
DS33Z11 mode pin;
DTE/DCE selection
DS33Z11 mode pin
RMII/MII selection
Low
Low
Low for DTE
Low
Low
High for RMII, low for MII
JP10
Rev: 080508
Power jack +5.0V to center post
Ethernet connection with MDIX, connect
with ether a patch or crossover cable
Configuration pins for DP83848 PHY.
These pins have internal pullups. Leaving
un-Jumpered or setting to VCC enables
auto-negotiation and advertise as 100/10
full/half duplex capable.
Status LEDs for DP83848 PHY. Each
status function has 2 LEDs to
accommodate the pin configuration
methods used by the PHY
Set to VCC to enable MDIX (automatic
crossing of RX/TX pair)
Set to GND to enable MII mode, VCC to
enable RMII mode. Note that the
DS33Z11 RMII pin needs to be Jumpered
to match this pin.
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_______________________________________________________________________________ DS33Z11DK
SILKSCREEN
REFERENCE
JP09
JP08
JP07
JP06
JP04
JP05
FUNCTION
DS33Z11 mode pin
CKPHA selection
DS33Z11 mode pin
MODEC0 selection
DS33Z11 mode pin
MODEC1selection
DS33Z11 mode pin
HWMODE selection
DS33Z11 mode pin
SCANMO selection
DS33Z11 mode pin
SCANEN selection
BASIC SETTING
SW MODE
HW MODE
Low
Low
SPI EEPROM hardware mode
configuration switch
High
Low
Software mode selected
Low
Low
Software mode selected
Low
Low
Hardware/software mode (software mode
selected)
Low
Low
Set low for normal operation
Low
Low
Set low for normal operation
J03
USB
User
decision
User
decision
J10
RS232 Serial
User
decision
User
decision
DS07
Status LED
On
On
DS08
Status LED
-
-
J04.1 + J04.2
Enable device driver
User
decision
—
J04.3 + J04.4
Enable callbacks
User
decision
—
J04.3 + J04.4
Looptime /
Sourcetime
User
decision
—
J04.7 + J04.8
J04.9 + J04.10
T1E1, T3E3 selection
Not installed
—
JP18
JP17
JP16
Addr2
Addr1
Addr0
J07
J06, J05
YB02
(Bottom side)
Rev: 080508
DESCRIPTION
Installed
Pins 2+3
See
DS33Z11
datasheet
JTAG
Ethernet Testpoints
—
—
—
—
Unused refclk OSC
—
—
System USB connector. Used with
ChipView host PC software (if RS232 is
not used)
System RS232 connector. Used with
ChipView host PC software (if USB is not
used). The RS232 connector may also be
used with any terminal emulator, settings
are 57.6K, 8N1, no flow control.
Displays kit status. This LED should
remain lit
Miscellaneous LED.
When installed the device driver will
configure the DS33Z11 and the
transceiver during power-up.
When installed the driver will respond to
interrupts.
When installed the driver will configure
the serial link for Looptime (TCLK driven
by RCLK). When not installed TCLK is
driven by scaled MCLK. Driver must be
enabled to make use of this setting.
When installed the driver will select a
transceiver and mode of operation as
shown below.
00 = DS2155 in T1 Mode
01 = DS3170 in T3 Mode
10 = DS2155 in E1 Mode
11 = DS3170 in E3 Mode
Driver must be enabled to make use of
these settings.
Address pin/EEPROM config switch.
Install on pins 2+3 to connect DS33Z11
address pins A2,A1,A0 to the processor.
Leave disconnected to allow pullup to pull
high. Connect pins 1+2 to pull low.
JTAG testpoints for DS33Z11
Testpoints for Ethernet interface
Unused oscillator. Could be used to drive
DS33Z11 refclk and PHY MCLK. Instead
this oscillator is not used, and the clocks
are provided by DS33Z11 RefClkO.
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SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SW MODE
HW MODE
DESCRIPTION
DS33Z11 RefClk output. Jumper pins 1+2
to drive with YB02. Jumper pins 2+3 to
drive with DS33Z11 RefClk output.
System Clock for DS33Z11. Must be set
for 100Mhz If RefClkO is used to drive
RefClkI and PhyClk.
JP24
RefClk / Phy Clock
selection
—
—
YB03
(Bottom side)
System Clock
—
—
—
—
SPI signals (for EEPROM memory)
High
Set high to enable auto flow control.
High
Set high to enable full duplex.
High
Set high to confg for 100Mb
Y01
(Not populated)
spi_cs, spi_ck,
spi_miso, spi_mosi
DS33Z11 mode pin
AFCS selection
DS33Z11 mode pin
FULLDS selection
DS33Z11 mode pin
H10S selection
HW mode
only
HW mode
only
HW mode
only
U04
Processor testpoints
--
--
J09
J08
Address Databus
—
—
J08.12+J08.14
FPGA
Tristate Jumper
—
—
TP02
SW01
DS11
J13
J12
TP05
TP06
RefClkIn Testpoint
System Reset
LED
Debug
JTAG
TDEN
RDEN
—
—
—
—
—
—
—
—
—
—
—
—
JP20
JP21
JP22
JP23
TSER
RSER
TCLKI
RCLKI
Jumpered,
See
Figure 1
Jumpered,
See
Figure 1
JP25
Testpoints
T3E3_OSC
—
—
OSC
—
—
Testpoint grid surrounding processor, all
processor pins are brought out.
Address databus for DS33Z11, DS2155,
DS3170. Unused chipselect CS_X4 are
provided to allow the DK to control
additional, external devices.
Setting the ‘tristate’ jumper will tristate the
FPGA. This provides the user with a
method for controlling the DK with an
external processor.
DS33Z11 RefClk input. Also see JP24.
Drives UB11 reset controller
Power OK LED
Connector for OnCe software debug
JTAG connector for Lattice FPGA
DS33Z11 TDEN RDEN testpoints.
Unused.
Jumper selection for serial interface.
Possible modes are: T1E1, T3E3,
Loopback (or wired to external system).
Note that loopback requires an external
oscillator to be wired in.
Testpoints for T3E3 Oscillator. Can be
used as TCLK/RCLK when in hardware
loopback
Oscillator for DS2155 MCLK
2-pin BNC Jumper
—
—
Jumper for connection to T1E1 BNC
J15
RJ45
—
—
T1E1 RJ45 connector
DS13
DS12
J18
J17
LED
LED
TX
RX
—
—
—
—
DS2155 RLOS LED
DS3170 GPIO LED
—
—
Jumper for connection to T3E3 BNC
JP13
JP15
JP19
YB04
J14
J16
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7. Address Map
Motorola resource card address space begins at 0x81000000. All offsets given below are relative to 0x81000000.
Table 2. Overview of Daughter Card Address Map
OFFSET
DEVICE
DESCRIPTION
0X0000 to 0X0087
FPGA
0X1000 to 0X1FFF
DS33Z11
0X2000 to 0X2FFF
DS2155
T1E1 transceiver. Uses CS_X2
0X3000 to 0X3FFF
DS3170
T3E3 transceiver. Uses CS_X3.
0X4000 to 0X4FFF
Unused
Unused chipselect for controlling external device. Uses CS_X4.
Processor board identification
DS33Z11. Uses CS_X1.
Registers in the DS33Z11, DS2155, and DS3170 can be easily modified using the ChipView host-based userinterface software with the definition files previously mentioned.
8. DS33Z11 Information
For more information about the DS33Z11, consult the DS33Z11 data sheet available on our website at
www.maxim-ic.com/DS33Z11.
8.1
DS33Z11DK Information
For more information about the DS33Z11DK, including software downloads, consult the DS33Z11DK data sheet
available on the our website at www.maxim-ic.com/DS33Z11DK.
8.2
Technical Support
For additional technical support, go to www.maxim-ic.com/support.
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9. Component List
Table 3 shows the component list for the DS33Z11DK.
Table 3. Component List
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
C01, C02, C03, C04, C05,
C06, C07, CB22, CB28, CB73
, C14, C16, C20, CB44, CB56
15
1206 CERAM 10uF 10V 20%
Panasonic
ECJ-3YB1A106M
See next row (begins with
C08)
34
L_0603 CERAM .01uF 50V 10% X7R
AVX
06035C103KAT
C08, C17, C22, C27, C29, C36, C37, C40, C41, C42, CB05, CB11, CB17, CB18, CB19, CB27, CB35, CB40, CB46, CB47,
CB54, CB57, CB59, CB65, CB69, CB78, CB80, CB82, CB84, CB90, CB91, CB94, CB97, CB99
31
L_0603 CERAM .1uF 16V 20% X7R
AVX
0603YC104MAT
C09, C18, C24, C38, C39, C45, CB08, CB13, CB29, CB32, CB33, CB34, CB37, CB39, CB45, CB50, CB55, CB58, CB60,
CB63, CB67, CB70, CB71, CB74, CB76, CB86, CB87, CB88, CB93, CB95, CB96
C10, C11
2
L_0603 CERAM 22pF 25V 5% NPO
AVX
06033A220JAT
C12, C13 , C44
3
L_1206 CERAM 1uF 16V 10%
Panasonic
ECJ-3YB1C105K
See next row (begins with
0603 CERAM 4.7uF 6.3V
C15)
MULTILAYER
51
UNK
ECJ-1VB0J475M
C15, C21, C23, C25, C26, C28, C30, C31, C32, C33, C34, C35, C43, C46, C47, CB09, CB10, CB15, CB20, CB21, CB24,
CB25, CB26, CB30, CB31, CB36, CB38, CB41, CB42, CB43, CB48, CB49, CB51, CB52, CB53, CB61, CB62, CB64, CB66,
CB68, CB72, CB75, CB77, CB79, CB81, CB83, CB85, CB89, CB92, CB98, CB100
C19, CB04, CB06, CB07,
CB14, CB16, CB23
CB01, CB02, CB03, CB12
7
4
0603 CERAM 0.1uF 16V 10%
L_D CASE TANT 68uF 16V 20%
Phycomp
Panasonic
06032R104K7B20D
ECS-T1CD686R
DB01
DS01, DS02, DS07 , DS11
DS03, DS04
1
4
2
SCHOTTKY DIODE, 1 AMP 40 VOLT
L_LED, GREEN, SMD
LED, AMBER, SMD
International
Rectifier
Panasonic
Panasonic
10BQ040
LN1351C
LN1451C
DS05, DS06, DS13 , DS08,
DS09, DS10, DS12
7
LED, RED, SMD
Panasonic
LN1251C
GND_TP01, GND_TP02,
GND_TP03, GND_TP04,
GND_TP05, GND_TPB01
6
STANDARD GROUND CLIP
KEYSTONE
H01, H02, H03, H04, H05, H06
6
KIT, 4-40 HARDWARE, .50 NYLON
STANDOFF AND NYLON HEX-NUT
NA
4-40KIT4
1
CONN 2.1MM/5.5MM PWRJACK RT
ANGLE PCB, closed frame, high
current 24VDC@5A also requires 5V
ACDC adapter INPUT 100-240VAC 5060HZ 0.6A OUTPUT DC 5V 2.6A. PN
DMS050260-P5P-SZ. MODEL 3Z161WP05
CUI, INC
PJ-002AH
J02
J03
1
1
CONNECTOR, FASTJACK SINGLE, 8
PIN FOR NATIONAL PHY
TYPE B SINGLE RT ANGLE, BLACK
Halo
Electronics
MOL
HFJ11-2450E
NA
J04
1
TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT
NA
NA
J05, J06
2
L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT DO NOT POPULATE
DNP
DNP
J01
Rev: 080508
4954
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11 of 34
_______________________________________________________________________________ DS33Z11DK
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
2
L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT
Samtec
TSW-105-07-T-D
J08, J09
J10
J11
J13
2
1
1
1
NON POPULATED HEADER, 14 PIN,
DUAL ROW, VERT
L_CONN, DB9 RA, LONG CASE
100 MIL 2 POS JUMPER
100 MIL 2*7 POS JUMPER
Samtec
AMP
NA
NA
NOPOP-HDR-TSW-10714-T-D
747459-1
NA
NA
J14, J16, J17, J18
4
L_2 PIN HEADER, .100 CENTERS,
VERTICAL
Samtec
TSW-102-07-T-S
J15
1
L_RJ48 8 PIN SINGLE PORT
CONNECTOR
MOLEX
15-43-8588
See next row (begins with
JP01)
23
100 MIL 3 POS JUMPER
NA
NA
J07, J12
JP01, JP02, JP03, JP04, JP05, JP06, JP07, JP08, JP09, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19,
JP20, JP21, JP22, JP23, JP24
R01, R1, R2, R3, R4, R5, R6,
R7, R8, R9, R05, R15, R16,
R17, R18, RB06, RB16
17
RES 0603 2.2K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ222V
R02, RB25, RB26, RB29,
RB43 , RB24
6
L_RES 0603 330 Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ331V
See next row (begins with
R03)
19
RES 0603 30 Ohm 1/16W
Panasonic
ERJ-3GEYJ300V
R03, R04, R06, R07, RB32, RB36, RB37, RB38, RB39, RB40 , R13, RB19, RB21, RB23, RB41, RB42, RB48, RB53, RB54
R09
1
RES 0603 1.0M Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ105V
R10, R11, R12, R14
4
L_RES 0805 0.0 Ohm 1/10W 5%
Panasonic
ERJ-6GEY0R00V
RB01, RB02, RB03, RB04,
RB05, RB22, RB34
RB07
7
1
RES 0603 0.0 Ohm 1/16W 5%
RES 0603 4.87K Ohm 1/16W 1%
Panasonic
Panasonic
ERJ-3GEY0R00V
ERJ-3EKF4871V
RB18, RB20 , RB28, RB30,
RB35, RB51
RB33
6
1
RES 0603 10K Ohm 1/16W 5%
RES 0805 10K Ohm 1/10W 1%
Panasonic
Panasonic
ERJ-3GEYJ103V
ERJ-6ENF1002V
RB44, RB46
RB49, RB50
RB52
2
2
1
RES 0805 61.9 Ohm 1/10W 1%
RES 0603 332 Ohm 1/16W 1%
RES 0805 330 Ohm 1/10W 5%
Panasonic
Panasonic
Panasonic
ERJ-6ENF61R9V
ERJ-3EKF3320V
ERJ-6GEYJ331V
RP01
1
4 PACK RESISTOR 50 OHM 2 PCT
KOA
CN1J4TTD500G OR
CN1J4TTD49R9F
RP02, RPB01, RPB03,
RPB04, RPB05
5
4 PACK RESISTOR 2.2K OHM 5%
QUAD 0402
PANASONI
C
EXB-N8V222JX
4
4 PACK RESISTOR 30 OHM 5%
QUAD 0402
PANASONI
C
EXB-N8V300JX
RP03, RP04, RP05, RPB06
See next row (begins with
4 PACK RESISTOR 10K OHM 5%
PANASONI
RP06)
QUAD 0402
C
17
EXB-N8V103JX
RP06, RP07, RP08, RPB08, RPB09, RPB10, RPB11, RPB12, RPB13, RPB14, RPB16, RPB17, RPB18, RPB19, RPB20,
RPB21, RPB22
RPB02, RPB07, RPB15
SW01
T01
Rev: 080508
3
1
1
4 PACK RESISTOR 330 OHM 5%
QUAD 0402
L_SWITCH MOM 4PIN SINGLE POLE
XFMR 16P SMT
PANASONI
C
Panasonic
Pulse
EXB-N8V331JX
EVQPAE04M
TX1099
www.BDTIC.com/maxim
12 of 34
_______________________________________________________________________________ DS33Z11DK
DESIGNATION
QTY
DESCRIPTION
T02
1
XFMR, OCTAL T3/E3, 1 TO 2, SMT 32
PIN
Pulse
T3049
TP01, TP02, TP03, TP04,
TP05, TP06, TPB01, TPB02,
TPB03, TPB04
10
TESTPOINT, 1 PLATED HOLE, DO
NOT STUFF
NA
NA
U01
1
IC, DP83848C PHYTER 10/100
ETHERNET TRANSCEIVER, 48 PIN
TQFP
National
Semiconduct
or
DP83848C
U02
1
USB UART (USB - 8 bit FIFO), 32 PIN
LQFP
FTD
FT245BM
U03
U04
U05
U06, UB13
1
1
1
2
ELITE 10/100 ETHERNET
TRANSPORT OVER SERIAL LINK
14X14 CSBGA 169 PIN
MMC2107 PROCESSOR
IC, FPGA, 1.2V, 20X20 TQFP, 144 PIN
CYPRESS SRAM, LAB STOCK
Maxim
Motorola
LAT
NA
DS33Z11
MMC2107
LFEC3E-3T144C
NA
U07
1
DS3/E3 SCT, 11X11 CSBGA, 100 PIN
Maxim
DS3170
U08
1
T1/E1/J1 XCVR 100P QFP 0-70C
Maxim
DS2156L
UB01, UB02, UB03, UB04
UB05
4
1
IC, LINEAR REG 1.5W, 3.3V or Adj,
1A, 16TSSOP-EP
8-Pin uMax SOIC 1.8V or Adj
Maxim
Maxim
MAX1793EUE-33
MAX1792EUA18
UB06
UB07, UB12 , UB14
1
3
SPI SERIAL EEPROM 2M 8 PIN SOIC
2.7V to 3.6V
HIGH SPEED BUFFER
Atmel
FAIRCHILD
AT25F2048N-10SU-2.7
NC7SZ86
UB08
1
Dual RS-232 transceivers with 3.3V/5V
internal capacitors
Maxim
NA
1
IC, LDO REGULATOR WITH
RESET,1.20V OUTPUT 300 MA, 6 PIN
SOT23
Maxim
MAX1963EZT120-T
1
SYNCHRONOUS DRAM, 1MEGX32X4
BANKS, TSOP 86 PIN
Micron
MT48LC4M32B2TG-7
UB11
XB01
1
1
MICROPROCESSOR VOLTAGE
MONITOR, 3.08V RESET, 4PIN
SOT143
XTAL LOW PROFILE 8.0MHZ
Maxim
ECL
MAX811TEUS-T
EC1-8.000M
Y01
YB01
1
1
SPI SERIAL EEPROM 16K 8 PIN DIP
2.7V SOCKET ONLY
XTAL, LOW PROFILE, 6.00 MHZ
Atmel
Pletronics
AT25160A-10PI-2.7
LP49-26-6.00M
YB02
1
OSCILLATOR, CRYSTAL CLOCK,
3.3V socket
SaRonix
NA
YB03
1
OSCILLATOR, CRYSTAL CLOCK,
3.3V - 100.000 MHZ
SaRonix
NTH089A3-100.0000
YB04
1
OSCILLATOR, CRYSTAL CLOCK,
3.3V - 2.048 MHZ
SaRonix
NTH039A3-2.0480
1
OSCILLATOR, CRYSTAL CLOCK,
3.3V - 44.736 MHZ
SaRonix
NTH089AA3-44.736
UB09
UB10
YB05
Rev: 080508
SUPPLIER
PART
www.BDTIC.com/maxim
13 of 34
_______________________________________________________________________________ DS33Z11DK
10.
Schematics
The DS33Z11DK schematics are featured in the following pages. As this is a hierarchal schematic some
explanation is in order. The main board is composed of three hierarchal blocks: the processor block, the DS33Z11
block, and an Ethernet block inside the DS33Z11 block, which is a nested hierarchy block. The serial card consists
of two hierarchy blocks, one for each of the DS2155, and DS3170. These blocks are connected by jumpers to the
DS33Z11.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
ETHERNET PHY
PAGE 6 SYMBOL
SCHEMATIC
PAGES 08-09
µP BLOCK
PAGE 2 SYMBOL
DS33Z11 BLOCK
PAGE 2. SYMBOL
SCHEMATIC
PAGES 13-19
SCHEMATIC
PAGES 03-07
DS3170 BLOCK
PAGE 2 SYMBOL
SCHEMATIC PAGES 12-12
Rev: 080508
CPLD MUX
AND
SELECTION
JUMPERS
DS2155 BLOCK
PAGE 2 SYMBOL
SCHEMATIC PAGES 10-11
www.BDTIC.com/maxim
14 of 15
_______________________________________________________________________________ DS33Z11DK
11.
Revision History
REVISION
DATE
031405
042205
110106
080508
DESCRIPTION
Initial DS33Z11DK data sheet release.
Updated Basic DS33Z11 Initialization section; added step to Quick Setup #1
section; updated Table 2.
Updated schematics.
Reformatted data sheet to conform to newer template style; updated various
sections to include the DS33Z11DK01A0 revision.
PAGES
CHANGED
—
Rev: 080508
9, 11, 12
15–39
All
15 of 34
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
www.BDTIC.com/maxim
D
A
B
C
IN
8
NUMBER GIVEN
IS
IS
5
DESIGN
DS33Z11DK02A0
DS33Z11
6
DESIGN,
A GIVEN
DESIGN
BLOCK NAME:
ACCORDING TO ENTIRE
ARE REFERENCEING
7
THAN _TEMP_
IN
PINS
THE DESIGN
_ztopdn_.
5
NOT THE CURRENT BLOCK)
NET TO OTHER PAGES IN
THE BLOCK,
BLOCK_B_DN.
ON SYMBOLS DO).
BY BOTH THE PAGE NUMBER IN
DIFFERENT
THE ENTIRE
ARE LISTED
AND BY THE PAGE NUMBER WITHIN
CROSS REFERENCE INDICATORS
NUMBERS (BUT
BLOCK ARE LOCAL TO THAT BLOCK
BLOCK_A_DN
PAGE NUMBERS (BOTTOM RIGHT)
(PAGE
_DN.
BLOCKS DO NOT HAVE PIN
A HIERARCHY
_TEMP_
INSIDE
THE SIGNAL
6
HIERARCHY BLOCKS FOR DS33Z11,
DS2155,
DS3170,
MICROPROCESSOR
DS33Z11 AND ETHERNET PHY
HIERARCHY BLOCK FOR ETHERNET PHY
ETHERNET PHY
T1E1 WAN
T3E3 WAN
MICROPROCESSOR, RESET CONTROL AND POWER SUPPLY
7
BLOCK NAMES END IN
ON HIERARCHY
HIERARCHY
SIGNALS
PINS
ALL
8
CONTENTS:
PAGE 02:
PAGE 03-07:
PAGE 6:
PAGE 08-09:
PAGE 10-11:
PAGE 12:
PAGE 13-19:
NOTES:
www.BDTIC.com/maxim
4
KIT
4
3
3
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
2
PRINTED
2
Fri
Jun
20
02/06/2007
10:05:53
1
2008
1/19(TOTAL)
PAGE: 1/2(BLOCK)
DATE:
1
A
B
C
D
www.BDTIC.com/maxim
A
B
C
8
CS_X4
CS_X5
RD_DUT
WR_DUT
CS_X4
CS_X5
RD
WR
7
WR
RESET_SYS
T3_INT
WR
RESET_SYS
WAN_INT
_ztopdn_.
CS
CS_TE3
6
RD
ADDR<8..0>
DAT<7..0>
RD
DAT<7..0>
ADDR<8..0>
JTMS
JTCLK
JTDI
JTDO
JTRST
5
PAGES 12-12
HIERARCHICAL
BLOCK
_TE3WAN_DN
3
UB124
4
INT_Z11
2
JP22
DAT<7..0>
RESET_SYS
WR
UB14
NC7SZ86_U
CS_TE1
RD
3
4
INVERTER
2
3
TE1_RSER
JP20
1
TE1_TSER
ENGINEER:
STEVE SCULLY
2
PAGES 10-11
DS33Z11DK02A0
T1_INT
30
RB36
RB37
30
HIERARCHICAL
BLOCK
_TE1WAN_DN
RESET_AH
CS
WR
RD
ADDR<7..0>
DAT<7..0>
JTMS
JTCLK
JTDI
JTDO
JTRST
2
Z11_RDEN
Z11_TDEN
TE1_TGAPCLK
2
TDEN
TE1_RGAPCLK
3
TITLE:
1
JP21
WAN_INT
1
3
PAGES 03-07
HIERARCHICAL
BLOCK
_z11andlan_dn
ADDR<7..0>
JP23
2
1
INT
RESET_SYS
3
WR
RESET_SYS
WR
RD
CS
DAT<7..0>
ADDR<9..0>
RD
CS_Z11
DAT<7..0>
NC7SZ86_U
BUFFER
TE3_RGAPCLK
1
TE3_TGAPCLK
TE3_TSER
TE3_RSER
TE3_TGCLK
BLOCK NAME:
SPI_MISO
SPI_SCK
SPI_CS
SPI_MOSI
13-19
BLOCK
_motprocrescard_dn
RESET_SYS
CS_X3
CS_TE3
RESET_SYS
CS_X2
CS_TE1
D_DUT<7..0>
CS_X1
CS_Z11
A_DUT_<12..0>
INT5
INT5
ADDR<12..0>
INT4
INT4
DAT<7..0>
INT3
INT2
PAGES
WAN_INT
INT_Z11
HIERARCHICAL
ADDR<9..0>
4
30
I61
TE3_RSER
30
MICROPROCESSOR
5
TE3_TSER
30
RCLKI
Z11_RCLKI
RB40
TCLKI
Z11_TCLKI
RB39
RSER
Z11_RSER
RB38
TSER
Z11_TSER
RDEN
RGAPCLK
6
RSER
7
TGAPCLK
TSER
TP05
TP06
1
1
D
8
TE3_RGCLK
02/06/2007
4
V3_3
1
2/19(TOTAL)
PAGE: 2/2(BLOCK)
DATE:
5
3
2
7
6
1
8
10K
RPB12
1
A
B
C
D
A
B
V3_3
8
RB29
330
1
RED
2
DS10
4
MDIO
30
5
6
7
2
3
RPB06 8
1
MDC
TX_EN
D11
A11
D10
RXD2
RXD3
RXDV
4
TXD3
7
4UB07
BUFFER
NC7SZ86_U
1
COL_DET
3
2
TXD1
TXD2
1
TXD0
5
6
C13
C12
B13
E10
E9
D9
C9
B9
6
U03
LINE
IO
MASTER PORT
DS33Z11_U3
JTAG
MICRO PORT/SPI
_z11andlan_dn.
MDIO
MDC
COL_DET
TX_EN
TXD<3>
TXD<2>
TXD<1>
TXD<0>
TX_CLK
RXDV
RXD<3>
RXD<2>
RXD<1>
RXD<0>
RX_CLK
RX_ERR
RX_CRS/CRS_DV
REF_CLKO
OUT
BLOCK NAME:
INT
30
C11
RXD1
7
B11
RXD0
RP05 8
A10
RX_CLK
A8
B12
RX_ERR
TX_CLK
C8
RX_CRS
E13
PARENT BLOCK:
\_ztopdn_\
RED
1
4
ZMISO
ZSPISCK
A7
D<1>/MISO
D<2>/SPICK
4
330
9
7
5
VCC
TDO
TDI
8
3
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
V3_3
2
4
3
2
2
2
5
6
7
2
2.2K
RPB03 8
1
4
7
3
8
1
IN
V3_3
1
3/19(TOTAL)
PAGE: 1/5(BLOCK)
02/06/2007
2
1
0
10K
RB28
BLOCK
JP18
JP17
JP16
V3_3
DATE:
HIERARCHY
ZADDR2
ZADDR1
OF DS33Z11
JTDO
10
JTDI
JTCLK
6
4
JTMS
GND
HOLD*
WP*
VCC
AT25160A_U
CS*
2.7V
Y01
ZADDR0
1
6
ZSPICS
SO
2
ZMISO
ZSPISCK
SCK
SI
2
5
ZMOSI
DAT<7..0>
IO
BEGINNING
CONN_10P
GND
7
5
3
TCK
7
C6
D<7>
3
6
C5
D<6>
2
5
B7
D<5>
TMS
4
D<4>
1
3
B6
2
1
0
B5
J07
5
6
7
IN
ADDR<9..0>
D<3>
JTRST
2
A<9>
3
9
B4
A<8>
ZMOSI
8
A4
A<7>
A6
7
C3
A<6>
A5
6
B3
A<5>
RPB07
5
A3
8
4
C2
A<4>
1
3
B2
A<3>
ZADDR2
A2
HW MODE PINS ARE OUTPUTS FROM Z MODULE TO PROC
PROC (FPGA)
AUTOMATICALY IMPLEMENTS BUS MODE
5
2
A1 ZADDR0
B1 ZADDR1
1
DS09
3
A<2>
A<1>
A<0>
330
RB26
D<0>/MOSI
CS*
C1
REF_CLKO
B8
C
REF_CLK
SPI_CS*
D13
RD*/DS*
E1
F3
4
LED+TP
TP01
WR*/RW*
E2
IN
D8
A13
TP02
F7 JTMS
RST*
IN
www.BDTIC.com/maxim
IN
HWMODE
D5
RMIIMIIS
C4
REF_CLK
5
IN
G2
RCLKI
MODEC<0>
D6
FULLDS
A9
D
E4 JTDI
JTDI
IN
F1
TCLKI
MODEC<1>
D7
H10S
B10
DS33Z11
6
E5 JTDO
JTDO
IN
H1
RSER
WR
RD
ZSPICS
CS
INT
AFCS
7
(INPUT)
(OUTPUT)
INT*
PORTS
MII/RMII
D4 JTCLK
JTCLK
OUT
F2
TSER
DCEDTES
JTMS
E6 JTRST
JTRST
IN
H2
RDEN/RBSYNC
RCLKI
TCLKI
RSER
RB32 TSER
30
RDEN
IO
TDEN
F5
TDEN/TBSYNC
RESET_SYS
C10
RB30
8
SCAN/EN
E7
10K
ADDR<9..0>
C7
SCAN/MODE
E8
3
1
3
1
3
1
QOVF
CKPHA
F6
CKPHA
SCANMOD
SCANEN
AFCS
H10S
FULLDS
RMIIMIIS
DCEDTES
MODEC1
MODEC0
HWMODE
A
B
C
D
A
8
SDA<6>
SDA<7>
SDA<8>
SDA<9>
SDA<10>
SDA<11>
L9
L5
M5
M7
M8
N8
6
7
8
9
10
11
L6
N5
G13
K6
H4
M4
SD_DQM3
SD_CS
SD_CLKO
SD_CLKI
SD_RAS
SD_CAS
SD_WE
7
M9
SD_DQM2
TP04
TPB02
TPB01
SWE*
SCAS*
SRAS*
SYSCLKI
SDCLKO
SDCS*
6
SDMASK<3>
SDMASK<2>
SDMASK<1>
H8
9VDD3.3
H7
8VDD3.3
H6
7VDD3.3
H5
6VDD3.3
G10
5VDD3.3
G9
4VDD3.3
G8
3VDD3.3
G7
2VDD3.3
G6
1VDD3.3
G5
0VDD3.3
U03
SDRAM CONTROLLER SYSTEM
PWR/GND
DS33Z11_U3
H9
10VDD3.3
VSS12
J9
VSS11
K8
VSS10
J8
VSS9
K7
VSS8
J7
VSS7
J11
VSS6
J6
VSS5
K5
VSS4
J5
VSS3
F8
VSS2
K10
VSS1
K3
VSS0
D1
NC3
G3
NC2
G1
NC1
F9
PARENT BLOCK:
\_ztopdn_\
VSS13
K9
_z11andlan_dn.
VSS14
J10
4
VSS15
K12
5
VSS16
F12
BLOCK NAME:
Z41RSYNC
Z41TSYNC
NC_PINF9
G4
M10
SD_DQM1
D3
0VDD1.8
I228
NA
DS33Z11
D2
1VDD1.8
VSS17
F13
B
SDA<5>
L8
5
SDMASK<0>
SDA<4>
L7
4
E3
2VDD1.8
VSS18
A12
N6
SDA<3>
K11
3
F4
3VDD1.8
SDATA<31>
L10
31
SD_DQM0
SDA<2>
L11
2
J4
4VDD1.8
G11
30
SD_A<11..0>
SDA<1>
N10
1
K4
5VDD1.8
V1_8ZCHIP
L3
6VDD1.8
V3_3
H10
11VDD3.3
4
F10
7VDD1.8
5
E11
8VDD1.8
F11
29
C
SDA<0>
SBA<1>
SBA<0>
N9
N7
SD_BA1
0
M6
SD_BA0
6
E12
G12
28
7
D12
9VDD1.8
SDATA<30>
M13
10VDD1.8
SDATA<29>
L12
11VDD1.8
SDATA<28>
12VDD1.8
SDATA<27>
H12
27
D
8
1
1 1
www.BDTIC.com/maxim
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
N4
N3
L4
J3
M3
H3
J1
J2
K1
K2
L1
M12
H11
M11
N13
N11
L13
N12
K13
J13
J12
SDATA<5>
SDATA<6>
SDATA<7>
SDATA<8>
SDATA<9>
SDATA<10>
SDATA<11>
SDATA<12>
SDATA<13>
SDATA<14>
SDATA<15>
SDATA<16>
SDATA<17>
SDATA<18>
SDATA<19>
SDATA<20>
SDATA<21>
SDATA<22>
SDATA<23>
SDATA<24>
SDATA<25>
3
2
STEVE SCULLY
2
SD_DQ<31..0>
DS33Z11DK02A0
ENGINEER:
TITLE:
26
4
N2
SDATA<4>
H13
3
SDATA<3>
SDATA<26>
2
M2
1
0
SDATA<2>
L2
M1
N1
SDATA<1>
SDATA<0>
3
02/06/2007
1
4/19(TOTAL)
PAGE: 2/5(BLOCK)
DATE:
1
A
B
C
D
A
B
C
8
7
DQ<8>
DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<19>
DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>
DQ<25>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
76
77
79
80
82
83
85
31
33
34
36
37
39
40
42
45
47
48
50
51
53
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1
6
UB10
-
_z11andlan_dn.
1 MEG X 32
X 4 BANKS
PARENT BLOCK:
5
4
SD_BA0
SD_BA1
22
23
BA<0>
BA<1>
1
2
3
4
5
6
7
8
9
10
11
26
27
60
61
62
63
64
65
66
24
21
A<1>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
\_ztopdn_\
0
25
A<0>
SD_A<11..0>
SD_DQM3
59
DQM<3>
DQM<0>
SD_DQM2
16
RAS*
DQM<2>
SD_DQM0
19
SD_DQM1
SD_RAS
18
CAS*
71
SD_CAS
17
WE*
28
SD_WE
20
CS*
DQM<1>
SD_CS
67
CKE
SD_CLKO
FROM Z11
68
4
CLK
V3_3
SYNCHRONOUS DRAM
MT48LC4M32B2_TSOP_U
MT48LC4M32B2
BLOCK NAME:
DQ<7>
13
DQ<6>
11
6
74
DQ<5>
10
5
7
DQ<4>
8
4
VDD4
VSS4
DQ<3>
VDD3
VSS3
7
VDD2
VSS2
3
VDDQ8
VSSQ8
DQ<2>
VDDQ7
VSSQ7
5
VDDQ6
VSSQ6
2
VDDQ5
VSSQ5
SD_DQ<31..0>
VSSQ4
DQ<1>
5
VDDQ4
0
31
VSSQ3
6
VDDQ3
4
2
DQ<0>
DQ<31>
30 54
56
DQ<30>
VDDQ2
VSSQ2
D
7
43
29
15
1
VDD1
VSS1
86
72
58
44
8
81
75
55
49
41
35
9
3
VDDQ1
VSSQ1
84
78
52
46
38
32
12
6
www.BDTIC.com/maxim
3
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
V3_3
SYSCLKO
3
2
2
02/06/2007
1
5/19(TOTAL)
PAGE: 3/5(BLOCK)
DATE:
1
A
B
C
D
www.BDTIC.com/maxim
8
4
1
GND
1
OSC
YB03
OUT
VCC
5
8
7
V3_3
100.000MHZ_3.3V
BLOCK NAME:
SD_CLKI
_z11andlan_dn.
6
TXD_3_SNI_MODE
TXD3
5
TXD2
TXD2
\_ztopdn_\
TX_EN
PARENT BLOCK:
TX_EN
TX_CLK
TXD1
REF_CLK
REF_CLKO
4
R08
0.0
COL_PHYAD0
3
5
8
OUT
VCC
OSC
GND
1
MHZ
SOCKET
YB02
25.0
4
1
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
V3_3
COL_DET
RXDV
RX_ERR
RX_ER_MDIX_EN
RX_DV_MII_MODE
RX_CRS
RXD3
RXD_3_PHYAD4
CRS_DV_LED_CFG
RXD2
RXD_2_PHYAD3
RX_CLK
RXD1
RXD_1_PHYAD2
RX_CLK
RXD0
3
RXD_0_PHYAD1
BLOCK
_DP83848_WAN_DN
TXD0
TXD1
IN
TX_CLK
4
PAGES 08-09
HIERARCHICAL
TXD0
5
RESET_SYS
A
B
6
MDIO
C
7
MDC
D
8
30
PHY_CLK25M
MII_CLK
R06
RESET_SYS
30
MDIO
R07
MDC
2
2
02/06/2007
1
PAGE: 4/5(BLOCK)
6/19(TOTAL)
DATE:
1
A
B
C
D
A
CB17
.01UF
C30
4.7UF
8
CB21
4.7UF
CB52
4.7UF
1UF
C31
4.7UF
1
2
C13
CB36
4.7UF
B
V3_3
CB64
4.7UF
4
3
2
1
7
V1_8ZCHIP
SHDN
RST
IN
IN
GND
SET
OUT
OUT
UB05
MAX1792
6
BLOCK NAME:
5
6
7
8
CB40
.01UF
C
CB60
.1UF
2
C14
1
CB46
.01UF
D
C16
10UF
C23
4.7UF
10UF
6
C27
.01UF
7
CB63
.1UF
V1_8ZCHIP
CB15
4.7UF
_z11andlan_dn.
C29
.01UF
2
C12
1
CB49
4.7UF
CB18
.01UF
PARENT BLOCK:
5
5
R2
MODEC1
\_ztopdn_\
R3
R5
SCANEN
4
LOW
CKPHA
2.2K
R6
2.2K
HIGH
LOW
R4
2.2K
H10S
2.2K
LOW
RMIIMIIS
2.2K
LOW
LOW
R1
2.2K
HWMODE
4
2
2
2
JP09
FOR Z11
V3_3
2
3
R7
R16
2
2
2
2
1
7/19(TOTAL)
PAGE: 5/5(BLOCK)
DATE:
V3_3
02/06/2007
JP04
JP13
JP15
JP11
JP08
1
CONTROL
2
2
BLOCK
AUTO-FLOW
HIERARCHY
MBIT,
2.2K
SCANMOD
LOW
2.2K
R15
2.2K
R9
2.2K
R8
2.2K
LOW
AFCS
HIGH
FULLDS
LOW
DCEDTES
HIGH
MODEC0
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
END OF DS33Z11
SWITCHES
2
JP05
JP19
JP10
JP07
JP06
3
MODE (SHOWN BELOW SIGNAL)
RESULTS IN:
MOTOROLA NON-MUX, MII,
FULL DUPLEX, 100
CONFIG
2
2
3
1
3
1
3
1
3
3
1
3
1
3
1
3
1
3
1
1
3
1
3
1
8
CB39
.1UF
www.BDTIC.com/maxim
1UF
A
B
C
D
A
B
C
8
3
4
1
2
3
4
COL_PHYAD0
RXD_0_PHYAD1
RXD_1_PHYAD2
RXD_2_PHYAD3
RXD_3_PHYAD4
7
TX_CLK
2.2K
R01
5
6
7
30
5
TXD2
32
48
22
34
33
25
6
_dp83848_wan_dn.
TXD_3/SNI_MODE
TXD_2
TXD_1
TXD_0
TX_EN
TX_CLK
PWR_DOWN/INT
RXD_3/PHYAD4
RXD_2/PHYAD3
RXD_1/PHYAD2
RXD_0/PHYAD1
COL/PHYAD0
RX_ER/MDIX_EN
CRS/CRS_DV/LED_CFG
RX_DV/MII_MODE
RX_CLK
BLOCK NAME:
TXD_3_SNI_MODE
6
4
TXD1
2
3
30
1
7
46
45
44
43
42
41
40
39
38
TXD0
TX_EN
R03
5
6
7
RP03 8
30
RP04 8
R04
PWR_DWN
2
CRS_DV_LED_CFG
RX_ER_MDIX_EN
V3_3
1
30
RX_DV_MII_MODE
RX_CLK
26
27
V3_3
28
IOGND
IOGND
DGND
AGND
AGND
47
35
36
19
15
DP83848
TMS
RD_P
RD_N
20
17
16
14
13
RESERVED
TD +
TD -
RD +
RD -
AN_V3_3
4.87K
RB07
4
3
2
1
50
RP01
5
6
7
8
V3_3
CB33
.1UF
CB32
.1UF
\_z11andlan_dn\
4
RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY
TD_N
TD_P
2.2K
2.2K
RB16
RB06
21
RESERVED
RBIAS
23
18
37
24
RBIAS
3
V3_3
RBIAS RESISTOR MUST BE PLACED CLOSE TO PIN
EACH PFBIN PIN REQUIRES 0.1UF
CAP NEAR PIN
PFBOUT
U01
PFBOUT
PFBIN1
PFBIN2
PARENT BLOCK:
5
10
7
TCK
1 RP02 88
IN
2
1
2
31
TRST#
2.2K 11
6
0.1UF
1
IO
3
CB14
30
TDI
12
5
4
CB23
0.1UF
2
29
TDO
9
4
3
CB20
4.7UF
RB05
0.0
STEVE SCULLY
2
PRINTED
Fri
OF PHY HIERARCHY
0.1UF
C17
.01UF
DS33Z11DK02A0
ENGINEER:
TITLE:
BEGINNING
2
CB05
.01UF
CB26
4.7UF
CB10
4.7UF
5
CB06
6
1
2
7
0.1UF
CB04 1
www.BDTIC.com/maxim
2
D
8
1
0.1UF
AVDD33
0.1UF
IOVDD33
IOVDD33
C19
25MHz_OUT
X2
X1
2
LED_LINK/AN0
1
AN_V3_3
LED_SPEED/AN1
CB07
PHY_CLK25M
LED_ACT/COL/AN_EN
2
LED_LINK_AN0
MDC
02/06/2007
20
10:04:01
1
2008
1/2(BLOCK)
8/19(TOTAL)
PAGE:
DATE:
BLOCK
CB09
4.7UF
Jun
1
AN_V3_3
1
LED_SPEED_AN1
MDIO
CB11
.01UF
CB16
LED_ACT_COL_AN_EN
RESET_N
2
IN
RESET_SYS
MDIO
MDC
0.1UF
IN
A
B
C
D
D
A
B
C
OUT
OUT
RXD_1_PHYAD2
4
RXD_3_PHYAD4
STRAP OPTIONS
8
2.2K
5
5
6
7
RPB04 8
5
6
V3_3
10
8
6
4
2
2
2
7
10
8
6
4
2
6
IN
OUT
4
TX_EN
TX_CLK
4
3
_dp83848_wan_dn.
HAVE A 2.2K+330
LED_LINK_AN0
2
1
5
6
RPB01
1
1
6
2
2
AN0
DS04
2
AN1
AN_EN
\_z11andlan_dn\
4
OF 2.2K)
GREEN
2
DS02
1
2.2K
RPB01
INSTEAD
2
7
8
AMBER
1
3
2.2K
2
2
RED
1
2
2
2
PARENT BLOCK:
5
DS06
1
1
AMBER
STRAP RESISTOR
330
7
RPB02 8
1
RPB01
2.2K
1
JP01
V3_3
JP02
V3_3
JP03
V3_3
MUST BE PLACED THE SAME FOR EACH PORT TO
PHY CARD IF DESIRED.
PLACEMENT SHOULD ALLOW
LED_ACT_COL_AN_EN
LED_SPEED_AN1
(SOME PINS
BLOCK NAME:
DATASHEET
JP12
V3_3
OUT
OUT
OUT
OUT
OUT
PLACEMENT NOTE:
TESTPOINTS (SHOWN ABOVE)
ALLOW USE OF AN EXTERNAL
0.2 BETWEEN CONNECTORS.
RX_CLK
RX_ER_MDIX_EN
CRS_DV_LED_CFG
COL_PHYAD0
RX_DV_MII_MODE
JP14
V3_3
CONN_10P
9
7
5
3
1
HERE DO NOT FOLLOW THE DP83484
PHY MDIO ADDRESS (0X01)
2.2K
4
2.2K
I99
A0402_5PCT
EXB-N8V222JX
RPB01
3
RXD_2_PHYAD3
4
2
RXD_1_PHYAD2
COL_PHYAD0
1
RXD_0_PHYAD1
RX_ER_MDIX_EN
3
7
TXD_3_SNI_MODE 2
RX_DV_MII_MODE
RPB05 8
FOR RMII
9
RXD_3_PHYAD4
HIGH
7
RXD_2_PHYAD3
5
1
3
RXD_0_PHYAD1
1
LOW FOR MII,
V3_3
OUT
OUT
DS03
J06
3
1
3
5
9
7
5
3
1
10
8
6
4
2
TXD1
TXD2
10TXD0
8
6
4
V3_3
IN
IN
IN
IN
6
5
3
8
J02
SYM_1
3
ENGINEER:
STEVE SCULLY
DS33Z11DK02A0
2
END OF PHY HIERARCHY
TITLE:
SH2
J7,8
J4,5
J6
J3
J2
J1
SH1
BLOCK
1
02/06/2007
10
9
1
9/19(TOTAL)
PAGE: 2/2(BLOCK)
DATE:
CONN_HFJ11_2450_U
P8
P6
P5
P3
P2
P4
1
4
2
P1
V3_3
2
CAPS FOR XFRM CENTER TAP
SHOULD BE PLACED CLOSE TO XFRM
TD_N
TD_P
RD_N
RD_P
TXD_3_SNI_MODE
2
CONN_10P
9
7
5
3
1
J05
3
CB08
6
.1UF
CB13
7
GREEN
1
DS05
1
1
8
1
DS01
.1UF
3
1
3
1
3
1
1
RED
www.BDTIC.com/maxim
A
B
C
D
D
A
B
C
8
7
1
TTIP55
RRING55
RTIP55
1
TRING55
0.0
R11
0.0
R10
2
2
5
2
1
6
0.0
R12
0.0
BLOCK NAME:
1
R14
1UF
C44
2
2
_te1wan_dn.
1
14
15
16
11
10
9
1:0.8
1:1
1:1
1:0.8
1
4
3
2
5
6
7
8
PARENT BLOCK:
5
TE1 SINGLE
1
2
1
2
3
\_ztopdn_\
B
D
F
H
A
C
E
G
G
4
1
S
J16
G
CONN_RJ48
2
4
6
8
S
J15
1
J14
1
3
5
7
3
2
STEVE SCULLY
2
OF T1E1
DS33Z11DK02A0
ENGINEER:
TITLE:
BEGINNING
WAN BLOCK
4
2
6
R13
30
7
1
CB95
www.BDTIC.com/maxim
.1UF
61.9
2
8
T01
61.9
RB46
2
T01
RB44
/
HIERARCHY
02/06/2007
1
10/19(TOTAL)
PAGE: 1/2(BLOCK)
DATE:
BLOCK
1
A
B
C
D
A
B
4
IN
IN
IO
IN
88
RCLKI55
32
38
39
40
TRING55
TPOSI55
TNEGI55
TCLKI55
10
JTDO
8
OSC
OUT
VCC
4
JTCLK
YB04
7
JTDI
JTDO
JTCLK
JTDI
JTRST
JTMS
TCLKO
TNEGO
TPOSO
TCLKI
TNEGI
TPOSI
TRING
TTIP
LIUC
RCL
8XCLK
RCLKO
RNEGO
RPOSO
RCLKI
RNEGI
RPOSI
RRING
RTIP
RB51
5
2.048MHZ_3.3V
V3_3
10K
5
41
42
JTRST
8
29
TTIP55
43
12
6
13
89
90
LIUC55
JTMS
GND
1
87
RNEGI55
91
86
17
RRING55
RPOSI55
16
RTIP55
U08
V3_3
6
DS2156
TQFP
7
BLOCK NAME:
6
_te1wan_dn.
TVSS
RVSS1
RVSS2
RVSS3
DVSS1
DVSS2
DVSS3
DVSS4
30
19
20
24
45
60
80
84
C
IO
D
7
18
31
44
61
81
83
RVDD
TVDD
DVDD1
DVDD2
DVDD3
DVDD4
ESIBS<0>
ESIBS<1>
36
54
TCLKI
TLINK55
TSYNC55
TGAPCLK
TSYSCLK55
5
PARENT BLOCK:
5
D/AD<0>
D/AD<1>
D/AD<2>
D/AD<3>
D/AD<4>
D/AD<5>
D/AD<6>
D/AD<7>
CS*
INT*
RLOS/LOTC
RCHBLK
TCHBLK
\_ztopdn_\
IN
NC3
WR/RW*
RD/DS*
MUX
BTS
A<0>
A<1>
A<2>
A<3>
A<4>
A<5>
A<6>
ALE/AS/A<7>
RESET_AH
RSER 95
MCLK55 21
96
94
3
14
93
22
8
RCLK
RLINK
RSYNC
RCHCLK
RSYSCLK
RLCLK
RDATA
TCLKI
82 RB48
30
78
98 RSYNC55
92 RGAPCLK
100 RSYSCLK55
79
85
97
RFSYNC
UOP0
UOP1
UOP2
UOP3
8
9
15
23
TDATA55
TSSYNC55
TSIG55
46
35
37
53
51
34
50
52
48
49
TCLK
TLINK
TSYNC
TCHCLK
TSYSCLK
TLCLK
TDATA
TSSYNC
TSIG
TESO
RSER
MCLK
RMSYNC
RSIG
BPCLK
TSTRST
RSIGF
XTALD
ESIBRD
TSER
ESIBRD5576
47
TSER
IN
NC1
NC2
26
27
5
4
3
2
0
7
6
5
4
3
2
1
0
BTS55
MUX55
RD
WR
64
63
62
59
58
57
56
73
72
71
70
69
68
67
66
11
55
74
77
4
6
65
28
7
1
CS
75
IN
IN
ADDR<7..0>
DAT<7..0>
IN
OUT
T1_INT
25
IO
RLOS_LOTC55
RGAPCLK
TGAPCLK
99
33
4
IN
www.BDTIC.com/maxim
OUT
330
DS13
RED
3
2
2
STEVE SCULLY
2
4
I94
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
I93
10K
5
6
7
V3_3
V3_3
02/06/2007
JTDO
1
1
11/19(TOTAL)
PAGE: 2/2(BLOCK)
DATE:
5
6
7
8
RPB22
10K
I98
RPB18 8
10K
I97
RPB20
10K
I96
RPB21
10K
I95
RPB19
10K
RP08
4
3
2
BLOCK
JTDI
3
2
JTCLK
JTMS
1
JTRST
RSYSCLK55
1
4
3
TSYSCLK55
MUX55
2
4
TPOSI55
TCLKI55
3
RNEGI55
1
2
RPOSI55
TNEGI55
1
4
TSYNC55
ESIBRD55
3
RSYNC55
1
2
BTS55
RCLKI55
4
3
TLINK55
TSIG55
LIUC55
1
TSSYNC55
HIERARCHY
DS33Z11DK02A0
ENGINEER:
TITLE:
END OF T1E1
IN
IO
RB52
3
A
B
C
D
4
A
B
C
2
3
4
JTCLK
JTMS
JTDI
10K
I85
5
5
6
7
8
8
V3_3
IO
IN
1
D<7>/SPI_CPOL
K8
4
7
RPB16
5
6
D<15>
G8
6
BLOCK NAME:
D<14>
H10
D<13>
H9
7
2
3
D<12>
H8
10K
D<11>
J10
8
D<10>
J9
5
6
7
8
D<9>
D<6>/SPI_CPHA
H7
6
1
10K
D<5>/SPI_SWAP
J7
5
D<8>
D<4>
K7
4
G6
D<3>
H6
3
J8
D<2>/SPI_SCLK
J6
2
7
D<1>/SPI_MOSI
D<0>/SPI_MISO
J5
0
K9
A<8>
H5
8
1
A<7>
J4
7
5
A<6>
A<4>
J3
4
6
A<3>
H3
3
A<5>
A<2>
K2
2
K3
A<1>
J2
1
H4
A<0>/BSWAP
K5
0
4
3
2
RPB17
DAT<7..0>
ADDR<8..0>
T3MCLK
JTDO
RP07
JTAG TESTPOINTS
1
JTRST
OUT
GND
_te3wan_dn.
2.2K
R17
2.2K
R18
JTCLK
JTCLK
VSS1
8
JTMS
JTMS
VSS2
VCC
CS*
MODE
JTDI
JTDI
VSS3
1
VSS4
V3_3
RD*/DS*
WIDTH
OUT
JTDO
JTDO
JTRST
A5
B3
C4
D5
E5
V3_3
U07
5
RED
DS12
1
RB43
PARENT BLOCK:
2
HIZ,TEST,ALE
DS3170_BGA_U
JTRST*
VSS5
1
OSC
VDD1
YB05
VDD2
AVSSR
D
VDD3
AVSST
44.736MHZ_3.3V
RDY*
VDD4
AVSSJ
V3_3
\_ztopdn_\
330
V3_3
GPIO<2>
5
AVDDR
GPIO<3>
6
AVDDT
GPIO<4>
7
AVDDJ
GPIO<5>
8
4
4
3
T3MCLK
V3_3
B6
C9
F8
C10
A9
ROH
ROHCLK
ROHSOF
TCLKI
TSOFI
TSOFO/TDEN
TE3_RGCLK
A6
B8
RCLKO/RGCLK
RSOFO/RDEN
3
IN
OUT
IN
IN
2
OF T3E3
TPB04
TPB03
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
BEGINNING/END
TE3_RSOFO_RDEN
TE3_RSER
C6
RSER
TE3_TSOFO_TDEN
C8
TCLKO/TGCLK
TE3_TSER
TE3_RXN
TE3_TGCLK
TE3_TXP
TE3_TXN
TE3_RXP
B9
B10
G9
TOHSOF
TSER
D7
TOH
TOHCLK
C7
RXN
E10
A3
RXP
TOHEN
A4
F9
RLCLK
RNEG/RLCV
A8
TXN2
30
F2
TXN1
F10
F1
TXP2
RPOS/RDAT
RB42
E2
TE3_TCLKI
SMT0603_5PCT
ERJ-3GEYJ300V
E1
TE3_TCLKI
SMT0603_5PCT
ERJ-3GEYJ300V
RB41
TXP1
30
1
26
28
2:1
T02
2:1
6
5
S
G
1
G
1
12/19(TOTAL)
PAGE: 1/1(BLOCK)
02/06/2007
BLOCK
S
J18
OHM 2P
RREF1
DATE:
1
J17
OHM 2P
TREF1
75
8
7
HIERARCHY
27
25
T02
75
TRANSFORMERS AND CONNECTORS)
D9
E9
B7
SCT,
2
TE3 WAN BLOCK
TNEG
TPOS/TDAT
TLCLK
(DS3170
DS33Z11
NO TPDENO?
GPIO<6>
ALE
INT*
OUT
GPIO<7>
G4
A1 CS
B2 RD
C2 WR
WR*/RW
SPI
J1
D8
T3_INT
F3
MODE
H2
WIDTH
C3
VSS6
C1
K1
K6
G10
A10
A2
REFCLK
GPIO<8>
VDD5
AVSSC
C5
F4
E3
G3
AVDDC
TEST*
B1
D1
K4
K10
D10
A7
B5
E4
D2
G1
H1
G2
CLKO
HIZ*
VDD6
GPIO<1>
D6
NC
E8
E7
F7
G7
F6
G5
D3
D4
RST*
F5
B4
E6
RESET_SYS
www.BDTIC.com/maxim
IN
1
1
IN
RB50
332
IN
RB49
332
IN
RB53
30
IN
2
IN
RB54
30
IN
2
IN
A
B
C
D
A
B
C
54
55
56
57
58
61
ICOC21
ICOC20
ICOC13
ICOC12
ICOC11
ICOC10
70
SCI1_IN
8
69
68
SCI2_IN
SCI1_OUT
66
SCI2_OUT
TEST 63
53
ICOC22
GND
52
ICOC23
TIM_16H_8L
EB3*
INT5*
84
INT7*
89
INT6*
ICOC10
ICOC11
ICOC12
ICOC13
ICOC20
ICOC21
ICOC22
RXD1
TXD1
RXD2
TXD2
MMC2107
CONTROL
82
96
EB2*
INT4
ICOC23
TEST
EB3
EB2
79
98
EB1*
INT3*
100
75
88
EB1
EB0
INT2*
7
USER_LED1
USER_LED2
INT3
INT4
RUN_KIT_USR
KIT_STATUS
INT2
YC0
80
U04
104
PQB3
INT1*
72
101
EB0*
PQB3
PQB2
PQB1
71
106
PQB1
PQB0
PQA4
90
D
CS0*
CS1*
CS2*
CS3*
TC1
TC2
CSE0
CSE1
6
BLOCK NAME:
6
PARENT BLOCK:
4
27
30
31
34
35
15
14
13
12
11
\_ztopdn_\
25
16
SPI_CS
94
22
21
17
18
20
ONCE_DE_B
OUT
OUT
19
17
16
15
12
10
7
5
4
3
143
93
SPI_SCK
PROC_RESET_OUT
20
120
21
RESET_SYS
CPUCLK_OUT
22
128
CS0
118
86
23
24
CS2
83
CS1
25
CS3
81
85
26
TC1
78
28
27
5
1
2
30
29
144
4
31
TC2
CSE1
CSE0
5
67
62
60
_motprocrescard_dn.
SS*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
PQA3
XTAL
124
7
PQA1
EXTAL
125
105
PQB2
INT0*
109
PQA3
110
PQA1
111
PQA0
133 ONCE_TDI
2107_TDO
130
107
PQB0
MOSI
OUT
135
TDI
108
PQA4
YCO
SPI_MOSI
SPI_MISO
91
MISO
IN
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
U04
3
MMC2107
PORT
3
ENGINEER:
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
V3_3
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
116
117
119
121
122
131
132
134
136
137
139
6
11
13
14
23
24
26
28
29
47
49
50
1
2
PRINTED
STEVE SCULLY
Fri
Jun
20
02/06/2007
BLOCK
10:02:20
1
2008
PAGE: 1/7(BLOCK)
13/19(TOTAL)
DATE:
OF PROCESSOR HIERARCHY
PD<31..0>
DS33Z11DK02A0
BEGINNING
TITLE:
VDDSYN
2
VSS1
RW
36
10
D10
95
37
9
D9
59
RW
OE
RCON
97
OE*
38
8
D8
99
SHS*
39
7
D7
40
6
D6
TA*
TA
TEA
102
TEA*
D5
41
5
VSSA
VRH
113
VRH
42
4
D4
43
D3
112
3
VSSF
92
VSTBY
FLASH_VPP
87
VRL
46
2
VSS4
VPP
D1
48
1
PQA0
115
VDDA
D0
51
TCLK
74
VDDF
0
TRST*
103
VDDH
114
142
123
VDDSYN
73
TDO
141
VDD8
VSSSYN
126
VSS8
140
TMS
129
VDD7
VSS7
127
VSS6
76
138
XTAL
OSC_MCU
ONCE_TCLK
ONCE_TRST_B
ONCE_TMS
77
VDD6
RB34
0.0
65
VDD5
VSS5
64
D2
CB70
.1UF
33
45
VDD4
32
VDD3
44
19
VDD2
VSS3
9
VDD1
VSS2
18
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8
8
PA<22..0>
A
B
C
D
A
B
C
W/ PLL
XTAL
31
3
28
4
25
23
26
27
2
3
4
5
6
7
8
9
8
PA<17..1>
2
1
ENABLE
A8
A9
A10
A11
A12
A13
A14
A15
A16
UB13
CY62128V
V3_3
BOOT
INTERN/EXTERN
FLASH
INTERNAL
DRIVE
FULL
MASTER MODE
1
2
3
PD<23>
PD<22>
PD<28>
PD<18>
PD<19>
CY62128V
7
IO0
IO1
IO2
IO3
IO4
IO5
IO6
4
PD<21>
IO7
3
PD<16>
RCON
2
PD<17>
3
30
29
28
27
26
25
24
20
19
18
17
15
14
13
5
6
7
V3_3
6
WHEN SET FOR
BOOT INTERNAL
D18 HAS A 10K
_motprocrescard_dn.
PD<31..24>
BLOCK NAME:
31
21
5
6
7
2
10K
RPB08 8
4
5
6
RPB13 8
10K
7
RPB10 8
10K
6
5
5
27
26
23
25
4
28
3
31
2
V3_3
A8
A9
A10
A11
A12
A13
A14
A15
A16
U06
CY62128V
4
4
\_ztopdn_\
PA<17..1>
PARENT BLOCK:
9
10
11
12
13
14
15
16
17
LOAD TO GND
RESET CONFIGURATION
1
4
1
PD<26>
32
5
10
D
7
1
VCC
A6
6
11
8
29
N_C
A5
7
12
A4
8
13
A3
9
A7
24
WE*
EB0
OE
30
OE*
CS0
22
CE2
A2
16
14
A7
CY62128V
5
8
GND
10
32
VCC
A6
6
7
CE1*
15
1
N_C
A5
7
6
A1
11
16
29
WE*
8
5
A4
9
4
A3
10
3
A0
12
17
24
OE*
EB1
OE
30
CE2
CS0
22
CE1*
A2
16
GND
A1
11
2
A0
12
1
www.BDTIC.com/maxim
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
22
21
20
19
18
17
16
20
19
18
17
15
14
13
3
2
IN
IN
IN
IN
WR_DUT
RD_DUT
CS_X1
CS_X2
CS_X3
CS_X4
CS_X5
RESET_SYS
2
D_DUT<7..0>
A_DUT_<12..0>
STEVE SCULLY
DS33Z11DK02A0
PD<23..16>
ENGINEER:
TITLE:
23
21
3
INT5
INT4
INT3
INT2
02/06/2007
1
14/19(TOTAL)
PAGE: 2/7(BLOCK)
DATE:
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
A
B
C
D
D
A
B
C
2
1
XB01
R09
8
8
PRT1_IN
PRT1_IN
PRT1_OUT
7
PRT1_OUT
5
4
3
2
1
2
330
1
RB24
E
D
C
B
A
J10
J
H
G
F
FORCEOFF*
VCC
R1IN
T1OUT
R1OUT
FORCEON
T1IN
T2IN
INVALID*
R2OUT
9
8
7
6
7
V+1
V+2
C1+
C1-
C2+
C2-
V-
GND
T2OUT
R2IN
UB08
MAX3233E
2
CONN_DB9P
10
9
6
5
4
3
2
1
V3_3
SCI1_IN
SCI1_OUT
1.0M
GREEN
KIT_STATUS
1
DS07
1
4
3
V3_3
XTAL
6
BLOCK NAME:
5
6
7
1
2
10K
RPB11 8
11
12
13
14
15
16
17
18
19
20
PLACE PADS FOR CAP
BUT DO NOT POPULATE
_motprocrescard_dn.
5
2
1
RB19
30
1
1
2
3
4
PARENT BLOCK:
V3_3
J03
USB
2
RESET_SYS
1
30
11
1
30
1
4
\_ztopdn_\
22PF
1
C11
22PF
C10
2
2
2
1
1
10K
5
6
7
RPB14 8
V3_3
V5_0
V3_3
U02
FT245BM_U
TXE_USB
RXF_USB
3
4
5
6
7
SI_WUUSB
PWREN_USB
22
21
20
19
18
16
15
14
12
11
10
D3
D4
D5
D6
D7
RD#
WR
TXE#
RXF#
PWREN#
2
WRUSB
2
23
D2
SI_WU
RD_USB
1
24
D1
STEVE SCULLY
1
02/06/2007
1
PAGE: 3/7(BLOCK)
15/19(TOTAL)
DATE:
D_DUT<7..0>
0
25
2
D0
DS33Z11DK02A0
ENGINEER:
TITLE:
3
EEDATA
2
TEST
EESK
1
31
EECS
RESET#
32
4
XTOUT
RSTOUT#
5
28
USBDP
7
XTIN
USBDM
8
27
3V3OUT
4
FLASH_VPP 3
6
1
14
13
J11
2
ONCE_TRST_B
12
V5_0
1
ONCE_DE_B
10
9
11
8
3
ALIGN KEY
ONCE_TMS
RB21
2
V5_0
RB23
5
7
4
3
2107_TDO
ONCE_TCLK
6
2
VDD
DATDAT+
GND
V3_3
CON14P
R05
2.2K
1
RB18
1
2
8.0MHZ
ONCE_TDI
4
C08
1
5
5
.01UF
OSC_MCU
6
2
1
2
1
7
10K
CB22
10UF
C09
2 R02
1
330
.1UF
8
CB28
10UF
USB
J13
CON14P
29
6.00MHZ
30
AVCC
AGND
YB01
3
VCC1
GND1
2
26
VCC2
9
1
13
VCCIO
GND2
17
www.BDTIC.com/maxim
A
B
C
D
A
PA<16..0>
8
PL14B
PL15A/LDQS15
PL15B
PL16A
PL16B
PL18A/VREF1_6
PL18B/VREF2_6
29
30
31
32
33
34
35
11
12
13
14
15
16
PL14A
27
9
39
10
PL13B
26
8
PL12B/LLM0_PLLC_FB_A
23
6
PL13A
PL12A/LLM0_PLLT_FB_A
22
5
25
PL11B/LLM0_PLLC_IN_A
21
4
7
PL11A/LLM0_PLLT_IN_A
20
PLL
INPUT
3
ENABLE_DRIVER_H
PB10A
B
PL9A/PCLKT7_0
8
PL9B/PCLKC7_0
PL8B
7
9
PL8A
6
1
2
PL7B
5
0
PB10B
40
7
PD<31..16>
BANK 5
PLL
INPUT
BANK 0
6
BLOCK NAME:
D_DUT<7..0>
U05
97_IO
I/O
PORT
LFEC_T144_U
42
7
C
PL7A
PL2B/VREF1_7
3
CPUCLK_OUT 4
PL2A/VREF2_7
2
PB11A
41
BANK 6
43
6
PB11B
45
5
D
31
142
PT10A
30
141
PT10B
29
140
PT12A
28
139
27
138
BANK 7
PT12B
26
137
PT13A
46
4
PB14A/BDQS14
47
3
PB14B
48
2
PB15A
49
1
PB13B
25
135
PT14A/TDQS14
24
134
PT14B
23
133
PT15A
22
132
50
0
PB16B/VREF1_5
PT15B
6
5
BANK 4
5
PLL
INPUT
BANK 1
_motprocrescard_dn.
A_DUT_<12..0>
100
PR9B/PCLKC2_0
TXE_USB
RXF_USB
82
81
79
PR13B/RLM0_PLLC_IN_A
PR14A/RLM0_PLLT_FB_A
PR14B/RLM0_PLLC_FB_A
PR16B
PARENT BLOCK:
INT5
\_ztopdn_\
4
INT2
2
1
3
4
RB22
5
6
7
RPB09 8
10K
330
V3_3
MEM_SCK
LOOP_SOURCETIME
0.0
ENABLE_CALLBACKS_H
INT3
INT4
INT5
75
PR16A
74
76
PR18A/VREF1_3
77
PR15B
78
WRUSB
83
PR13A/RLM0_PLLT_IN_A
PR15A/RDQS15
RD_USB
85
MEM_CS
1
DS08
RB25
V3_3
3
5
7
9
11
13
3
4
5
6
7
3
5
7
9
7
6
5
9
7
5
9
7
5
3
1
CS_X2
8
14
12
13
11
14
12
10
8
6
4
2
14
12
10
8
6
4
2
CONN_14P
13
9
7
5
3
1
J08
NOPOP
10
8
6
4
2
10
8
6
4
2
1
10K
2
RB35
FPGA
JMP04P10
JMP04P8
LOOP_SOURCETIME
ENABLE_CALLBACKS_H
ENABLE_DRIVER_H
FOR TQFP144
ENGINEER:
STEVE SCULLY
DS33Z11DK02A0
2
1
TRISTATE_AD_BUS
INT2
INT3
0
1
2
A_DUT_<12..0>
WR_DUT
RD_DUT
CS_X1
CS_X3
6
10
CS_X4
0
4
2
02/06/2007
V3_3
1
16/19(TOTAL)
PAGE: 4/7(BLOCK)
DATE:
NOTE: J04 PINS 1,3,5,7,9
WERE LEFT UNCONNECTED
THEY ARE NOW CONNECTED TO VCC BY REWORK WIRE
TITLE:
3
1
3
14
12
10
8
6
4
2
D_DUT<7..0>
CONN_10P
DRIVER / CALLBACKS / LOOPTIME
SIGNALS HAVE PULLDOWNS INSIDE
V3_3
I147
J04
13
11
9
7
5
3
1
J09
NOPOP
JUMPER PINS 12+14 TO TRISTATE
THE ADDRESS DATABUSS OF THE FPGA.
THIS ALLOWS THE USER TO
CONNECT A DIFFERENT PROCESSOR
3
11
1
12
8
4
2
CONN_14P
1
3
1
2
MEM_SCK MUST BE AT PIN77
TRISTATE_AD_BUS
PR12B/DI/CSSPI*
MEM_SI
MEM_SO
87
88
SI_WUUSB
101
PR9A/PCLKT2_0
PR11A/D7/SPID0
JMP04P10
102
PR8B
2
PWREN_USB
RD_DUT
103
PR8A
86
JMP04P8
WR_DUT
104
PR7B
PR12A/DOUT/CSO*
MISC_LED
105
106
PR2B/VREF1_2
INT2
PR7A
107
PR2A/VREF2_2
4
PR11B/BUSY/SISPI
PLL
INPUT
51
0
7
53
1
PB17A/PCLKT5_0
56
2
PB15B
131
PT16A/VREF2_0
21
130
PT16B/VREF1_0
PLL
INPUT
57
3
PB17B/PCLKC5_0
58
4
PB18A/WRITE*
59
5
PB16A/VREF2_5
129
PT17A/PCLKT0_0
20
127
PT17B/PCLKC0_0
19
124
PT18A
17
122
18
123
PT18B
16
121
PT19B/VREF2_1
PT19A/VREF1_1
PB20A/VREF2_4
60
6
PB18B/CS1*
120
PT20A
61
PB20B/D0/SPID7
62
7
PB19A/VREF1_4
119
PT20B
8
PB19B/CS*
118
PT21A
64
9
PB21A/D2/SPID5
65
8
PB23B/D4/SPID3
68
PT13B
CS_X1
CS_X2
69
116
66
10
BANK 3
PB24B/D5/SPID2
PT21B
OE
RW
CS0
115
PT22A/TDQS22
PB22B/D3/SPID4
11
PB21B/D1/SPID6
114
PT22B
PB23A
67
www.BDTIC.com/maxim
12
PB22A/BDQS22
112
CS1
113
PT23A
BANK 2
PT25A
CS2
EB0
EB1
111
PT25B
PB25B/D6/SPID1
70
PLL
INPUT
CS_X3
CS_X4
CS_X5
A
B
C
D
A
B
8
SCK
CS*
6
1
MEM_SCK
MEM_CS
2
3
1
UB06
2.7V
10
8
6
4
7
GND
SHDN*
IN
RST*
IC
4
5
4
7
3
8
V3_3
V3_3
V1_2
L_TDO
L_TDI
6
BLOCK NAME:
OUT
UB09
MAX1963
6
GND
HOLD*
WP*
VCC
AT25160A_U
SO
2
MEM_SO
SI
5
V3_3
VCC
TDO
TDI
CONN_10P
GND
7
5
MEM_SI
9
7
5
TCK
1
8 RP06
3
2
7
L_TCK
4
3
3
10K
L_TMS
CB56
CB44
10UF
10UF
C20
.1UF
_motprocrescard_dn.
5
PARENT BLOCK:
\_ztopdn_\
4
RESET_SYS
L_TMS
L_TDO
L_TDI
L_TCK
CFG1
CFG0
90
91
ALL LOW FOR
SPI3
MODE
PROGRAM*
CFG2
89
93
TMS
TDO
TDI
TCK
17
18
16
14
2
126
VCCAUX1
VCCAUX2
STEVE SCULLY
2
DONE
INIT*
97
95
94
54
VCCJ
CCLK
19
VCC3
10
99
VCC2
XRES
13
92
VCC1
V3_3
NEEDS 10K,1%
RESISTOR
PLACE CLOSE TO PIN
DS33Z11DK02A0
ENGINEER:
TITLE:
3
CONTROL
U05
LFEC_T144_U
97_IO
GND3A/GND4
72
2
GND3B
80
TMS
GND4
63
1
CB67
3
73
VCCIO3A
GND5
52
4
84
VCCIO3B
GND6A
28
1
5
55
VCCIO4A
GND6B/GND5
37
6
GND0
71
VCCIO4B
GND7/GND0
144
6
136
VCCIO0A
128
38
VCCIO5A
GND8
15
5
C18
143
VCCIO0B
GND1
44
VCCIO5B
GND9
96
J12
.1UF
110
VCCIO1A
117
24
VCCIO6A
GND10
98
7
.1UF
125
VCCIO1B
GND2/GND1
36
VCCIO6B
NC1
11
C
8
CB45
108
VCCIO2
109
1
VCCIO7
NC2
12
D
www.BDTIC.com/maxim
10K
02/06/2007
RB20
PAGE:
1
5/7(BLOCK)
17/19(TOTAL)
DATE:
MEM_SCK
RB33
V3_3
V1_2
1
10K
10UF
A
B
C
D
D
A
B
C
8
IN2
IN3
IN4
RST
SHDN
3
4
5
6
7
17
GND
IN2
IN3
IN4
RST
SHDN
3
4
5
6
7
GND
IN2
IN3
IN4
RST
SHDN
3
4
5
6
7
17
GND
7
REGULATOR1_OUTPUT
REGULATOR2_OUTPUT
REGULATOR3_OUTPUT
6
_motprocrescard_dn.
TRACES BETWEEN
BE LONG ENOUGH
TO ENSURE LOAD
TRACE GEOMETRY
REGULATOR4_OUTPUT
BLOCK NAME:
10
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
OUT1
1% REGULATOR
IN1
2
12
17
MAX1793_U
10
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
OUT1
3.3V
UB03
IN1
2
MAX1793_U
UB02
12
10
11
15
14
13
12
17
10
11
15
14
13
12
GND
SET
OUT4
OUT3
OUT2
OUT1
3.3V
1% REGULATOR
IN1
3.3V
REGULATOR_INPUT
REGULATOR_INPUT
3.3V
GND
GND
SET
OUT4
OUT3
OUT2
OUT1
MAX1793_U
2
3.3V
REGULATOR_INPUT
SHDN
7
UB04
RST
6
IN3
4
IN4
IN2
3
5
IN1
MAX1793_U
REGULATOR_INPUT 2
DB01
5V DC POWER SUPPLY AND
REVERSE BIAS PROTECTION
1
2
1
2
2.1MM/5.5MM
68UF
1
CB02
2
C04
10UF
UB01
C07
10UF
C06
10UF
RB01
0.0
RB02
0.0
RB03
0.0
RB04
0.0
V5_0
V3_3
V3_3
5
PARENT BLOCK:
\_ztopdn_\
4
REGULATOR OUTPUT AND V3.3
SHOULD
TO BUILD
0.06
OHM OF RESISTANCE
SHARING BETWEEN THE 3.3V
1% REGULATORS
FOR THIS IS:
1 INCH LONG, 10 MIL WIDE, 1 OZ COPPER
SUPPLY_OUTPUT
SUPPLY_OUTPUT
4
1
4
VCC
RESET*
REGULATOR_INPUT
GND
MR*
4
1
4
1
4
1
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
3
1
3
MAX811_U
UB11
3.08V
.50STANDOFF__NUT
3
4
68UF
2
1
4
1
H06 H05 H01 H02 H03 H04
2
1
SW01
C02
10UF
68UF
1
CB03
2
C05
10UF
68UF
1
CB01
2
1
2 CB12
2
C03
10UF
J01
3
C01
10UF
4
CB73
10UF
5
3
2
330
1
GREEN
5
6
7
02/06/2007
1
18/19(TOTAL)
PAGE: 6/7(BLOCK)
DATE:
RESET_SYS
DS11
RPB15
8
GND_TP02
GND_TP04
GND_TPB01
GND_TP03
4
2
4
1
V3_3
1
6
1
3.3V
1
7
1
8
1
1
1
2
www.BDTIC.com/maxim
A
B
C
D
A
B
C
V3_3
V3_3
C33
4.7UF
GND
V3_3
8
7/7(BLOCK)
I68
8
CB53
4.7UF
I67
C32
4.7UF
D
CB92
4.7UF
CB89
4.7UF
CB38
4.7UF
CB31
4.7UF
V3_3
www.BDTIC.com/maxim
CB79
4.7UF
CB68
4.7UF
CB77
4.7UF
CB66
4.7UF
CB81
4.7UF
CB51
4.7UF
CB41
4.7UF
7
CB76
.1UF
7
CB29
.1UF
CB71
.1UF
C24
.1UF
CB58
.1UF
CB55
.1UF
6
BLOCK NAME:
CB57
.01UF
CB47
.01UF
CB65
.01UF
CB97
.01UF
CB69
.01UF
CB99
.01UF
6
CB59
.01UF
C41
.01UF
_motprocrescard_dn.
C47
4.7UF
C26
4.7UF
C43
4.7UF
C35
4.7UF
CB85
4.7UF
C34
4.7UF
C46
4.7UF
CB72
4.7UF
5
CB61
4.7UF
CB30
4.7UF
5
PARENT BLOCK:
CB83
4.7UF
CB98
4.7UF
CB50
.1UF
C39
.1UF
CB74
.1UF
C38
.1UF
CB87
.1UF
CB34
.1UF
CB27
.01UF
4
C40
.01UF
4
\_ztopdn_\
CB84
.01UF
CB91
.01UF
CB94
.01UF
C22
.01UF
C42
.01UF
C37
.01UF
CB24
4.7UF
C21
4.7UF
CB75
4.7UF
C28
4.7UF
C15
4.7UF
C25
4.7UF
3
3
STEVE SCULLY
DS33Z11DK02A0
ENGINEER:
TITLE:
CB100
4.7UF
CB37
.1UF
CB96
.1UF
2
CB93
.1UF
2
END OF PROCESSOR HIERARCHY
CB25
4.7UF
CB43
4.7UF
CB62
4.7UF
CB42
4.7UF
CB48
4.7UF
C45
.1UF
CB88
.1UF
CB86
.1UF
CB82
.01UF
C36
.01UF
CB90
.01UF
CB54
.01UF
CB35
.01UF
CB80
.01UF
CB78
.01UF
1
02/06/2007
19/19(TOTAL)
PAGE:
DATE:
1
BLOCK
CB19
.01UF
A
B
C
D