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TP MS
Tire Pressure Monitoring Sensor
BDTIC
SP 37
Applic atio n N ote
LF Duty Cycle Measurement
Revision 1.0, 2011-10-11
Sens e & Con trol
www.BDTIC.com/infineon
BDTIC
Edition 2011-12-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
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SP37
LF Duty Cycle Measurement
confidential
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 1.0, 2011-10-11
Trademarks of Infineon Technologies AG
BDTIC
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2011-02-24
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SP37
LF Duty Cycle Measurement
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List of Tables
Table of Contents
1
Introduction ........................................................................................................................................ 5
2
Measurement setup ........................................................................................................................... 6
3
Measurement results ......................................................................................................................... 7
List of Figures
BDTIC
Figure 1
Figure 2
Figure 3
Figure 4
Manchester encoded signal. A: ideal signal, B: decreased duty cycle, C: increased duty cycle ......... 5
Measurement setup ............................................................................................................................. 6
Circuit for generating edge delay. S1 in position I: falling edge delayed, S1 in position II: rising edge
delayed. ................................................................................................................................................ 6
Error rate versus duty cycle ................................................................................................................. 7
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SP37
LF Duty Cycle Measurement
confidential
01
02
1
Introduction
Introduction
03
Apart from other timing parameters like baud rate the LF-telegram must comply with duty cycle requirements.
04 For a periodic rectangular signal duty cycle is defined as ratio of high-time to signal period. However, the LF
05 telegram is a non periodic, Manchester encoded binary signal. In fact both, the high time and low time, can be
half the bit time or full bit time, depending on transmitted bit pattern (see curve A in Figure 1). Therefore for this
06
kind of signal the duty cycle is changed by delaying all rising or all falling edges of the telegram by a constant
07 delay time. As a result the relative change of the short high periods is greater than of the long high periods.
08 Hence the duty cycle is defined as the ratio of the shortest high period and the bit time.
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BDTIC
0
0
1
1
0
1
0
A
B
C
Figure 1
Manchester encoded signal. A: ideal signal, B: decreased duty cycle, C: increased duty
cycle
30 Figure 1 illustrates the definition of duty cycle. Case A is the ideal signal. The shortest high period is half the bit
31 time. Hence the duty cycle is 50%. For case B all rising edges have been delayed by one quarter of the bit time.
So the shortest high period is one quarter of the bit time. Therefore the duty cycle is 25%. Finally, in case C all
32 falling edges have been delayed by one quarter of the bit time. The shortest high period is three quarter of a bit
33 time. Hence in case C duty cycle is 75%.
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SP37
LF Duty Cycle Measurement
confidential
Measurement setup
01
02
03
2
Measurement setup
04 In the test setup the telegrams were generated by PC software. A 125 kHz carrier was modulated with this
05 digital signal using the Agilent 33250A function generator. Since the used software could only provide
Manchester encoded telegrams with a 50% duty cycle, a circuit for delaying either the rising edges or the falling
06
edges was built between PC and function generator. Figure 2 shows the measurement setup and Figure 3 the
07 circuit for generating the edge delay.
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BDTIC
20 Figure 2
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Converter
RS232 to
Bitstream
RS232
Agilent
33250A
function
generator
Edge Delay
Circuit
SP37
Evaluation
Board
Measurement setup
+5V
4k7
TTL in
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I
2
3
1
II
S1
4
5
10
6
100k
SN74HC7002
SN74HC7002
2,2nF
9
8
6
SN74HC7002
5
D
SET
Q
1
I
II
3
CLR
4
Q
S1
TTL out
2
4013
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37 Figure 3
38
Circuit for generating edge delay. S1 in position I: falling edge delayed, S1 in position II:
rising edge delayed.
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SP37
LF Duty Cycle Measurement
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Measurement results
01
02
03
3
Measurement results
04 The error rate versus duty cycle was determined by counting the number of detected matching events (matching
05 of sync and P0 pattern) per time when periodically transmitting wakeup telegrams. The result is shown in Figure
4. For safe operation the duty cycle should stay in the interval of 40% to 60%. Anyhow, it is recommended to
06
design the LF transmitter for a duty cycle of 50%.
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BDTIC
SP37-A5
Figure 4
Error rate versus duty cycle
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