BDTIC www.BDTIC.com/infineon Sense & Control

BDTIC
TLE4961-2M
High Precision Automotive Hall Effect Latch
Data Sheet
Revision 1.0, 2013-01-19
Sense & Control
www.BDTIC.com/infineon
BDTIC
Edition 2013-01-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
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TLE4961-2M
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 1.0, 2013-01-19
15
Bhys values corrected
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
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ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
BDTIC
Other Trademarks
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FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2011-02-24
Data Sheet
3
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TLE4961-2M
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.5
2.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Default Start-up Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
3.1
3.2
3.3
3.4
3.5
Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical and Magnetic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electro Magnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
14
14
16
4
4.1
4.2
4.3
4.4
4.5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packing Information PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Footprint PG-SC59-3-5 and PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-SOT23-3-15 Distance between Chip and Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
18
5
Graphs of the Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
BDTIC
7
7
7
7
Graphs of the Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Sheet
4
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TLE4961-2M
List of Figures
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 5-1
Figure 5-2
Figure 5-3
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 6-8
Figure 6-9
Figure 6-10
Figure 6-11
Figure 6-12
Figure 6-13
Figure 6-14
Figure 6-15
Image of TLE4964-5M in the PG-SOT23-3-15 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration and Center of Sensitive Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Block Diagram TLE4964-5M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagram TLE4964-5M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Signal TLE4964-5M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Illustration of the Start-up Behavior of the TLE4964-5M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Circuit 1: With External Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application Circuit 2: Without External Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Definition of Magnetic Field Direction PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EMC Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PG-SOT23-3-15 Package Outline (All Dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Packing of the PG-SOT23-3-15 in a Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Footprint PG-SC59-3-5 and PG-SOT23-3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distance between Chip and Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Marking of TLE4964-5M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Point (BOP) of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Release Point (BRP) of the TLE4964-5M over Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hysteresis (BHys) of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power On Time tPON of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Signal Delay Time of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Supply Current of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current of the TLE4964-5M over Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Current Limit of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Current Limit of the TLE4964-5M over applied Pull-up Voltage . . . . . . . . . . . . . . . . . . . . . 22
Output Fall Time of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Fall Time of the TLE4964-5M over applied Pull-up Voltage . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Rise Time of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Rise Time of the TLE4964-5M over applied Pull-up Voltage . . . . . . . . . . . . . . . . . . . . . . . 23
Output Leakage Current of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Saturation Voltage of the TLE4964-5M over Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Saturation Voltage of the TLE4964-5M over Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Effective Noise of the TLE4964-5M Thresholds over Temperature . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Signal Jitter of the TLE4964-5M over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
BDTIC
Data Sheet
5
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TLE4961-2M
List of Tables
List of Tables
Table 1-1
Table 2-1
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description PG-SOT23-3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Rating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ESD Protection (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating Conditions Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Magnetic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Magnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electro Magnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BDTIC
Data Sheet
6
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TLE4961-2M
Product Description
1
Product Description
1.1
Overview
Characteristic
Supply Voltage
Supply Current
Sensitivity
Interface
Temperature
Bipolar Hall
Effect Latch
3.0~32 V
1.6 mA
High
BOP:5 mT
BRP:-5 mT
Open Drain
Output
-40°C to 170°C
BDTIC
Figure 1-1
1.2
•
•
•
•
•
•
•
•
•
•
Image of TLE4961-2M in the PG-SOT23-3-15 Package
Features
3.0 V to 32 V operating supply voltage
Operation from unregulated power supply
Reverse polarity protection (-18 V)
Overvoltage capability up to 42 V without external resistor
Output overcurrent & overtemperature protection
Active error compensation
High stability of magnetic thresholds
Low jitter (typ. 0.35 μs)
High ESD performance
Small SMD package PG-SOT23-3-15 (TLE4961-2M)
1.3
Target Applications
Target applications for the TLE496x Hall switch family are all applications which require a high precision Hall
Switch with an operating temperature range from -40°C to 170°C. Its superior supply voltage range from 3.0 V to
32 V with overvoltage capability (e.g. load-dump) up to 42 V without external resistor makes it ideally suited for
automotive and industrial applications.
The magnetic behavior as a latch and switching thresholds of typical ±5 mT make the device especially suited for
the use with a pole wheel for index counting applications as e.g. power closing and window lifter.
Table 1-1
Ordering Information
Product Name
Product Type
Ordering Code
Package
TLE4961-2M
Hall Latch
SP000997954
PG-SOT23-3-15
Data Sheet
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TLE4961-2M
Functional Description
2
Functional Description
2.1
General
The TLE4961-2M is an integrated Hall effect designed specifically for highly accurate applications with superior
supply voltage capability, operating temperature range and temperature stability of the magnetic thresholds.
2.2
Pin Configuration (top view)
BDTIC
Center of
Sensitive Area
3
0.65± 0.1
1
2
1.45± 0.1
SOT23
Figure 2-1
2.3
Pin Configuration and Center of Sensitive Area
Pin Description
Table 2-1
Pin Description PG-SOT23-3-15
Pin No.
Symbol
Function
1
VDD
Supply voltage
2
Q
Output
3
GND
Ground
Data Sheet
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TLE4961-2M
Functional Description
2.4
Block Diagram
VDD
To All Subcircuits
Voltage
Regulator
Oscillator and
Sequencer
Bias and
Compensation
Circuits
BDTIC
Spinning Hall
Probe
Amplifier
Demodulator
Chopper
Multiplexer
Reference
Q
Control
Low Pass
Filter
Comparator
with
Hysteresis
Overtemperature
& overcurrent
protection
GND
Figure 2-2
2.5
Functional Block Diagram TLE4961-2M
Functional Block Description
The chopped Hall IC switch comprises a Hall probe, bias generator, compensation circuits, oscillator and output
transistor.
The bias generator provides currents for the Hall probe and the active circuits. Compensation circuits stabilize the
temperature behavior and reduce influence of technology variations.
The active error compensation (chopping technique) rejects offsets in the signal path and the influence of
mechanical stress to the Hall probe caused by molding and soldering processes and other thermal stress in the
package. The chopped measurement principle together with the threshold generator and the comparator ensures
highly accurate and temperature stable magnetic thresholds.
The output transistor has an integrated overcurrent and overtemperature protection.
Data Sheet
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TLE4961-2M
Functional Description
B OP
Applied
Magnetic
Field
BR P
td
td
BDTIC
tf
tr
VQ
90%
10%
Figure 2-3
Timing Diagram TLE4961-2M
VQ
B
BRP
Figure 2-4
Data Sheet
0
BOP
Output Signal TLE4961-2M
10
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TLE4961-2M
Functional Description
2.6
Default Start-up Behavior
The magnetic thresholds exhibit a hysteresis BHYS = BOP - BRP. In case of a power-on with a magnetic field B within
hysteresis (BOP > B > BRP) the output of the sensor is set to the pull up voltage level (VQ) per default. After the first
crossing of BOP or BRP of the magnetic field the internal decision logic is set to the corresponding magnetic input
value.
VDDA is the internal supply voltage which is following the external supply voltage VDD.
This means for B > BOP the output is switching, for B < BRP and BOP > B > BRP the output stays at VQ.
VDDA
t Pon
3V
BDTIC
The device always applies
VQ level at start -up
Power on ramp
VQ
t
independent from the
applied magnetic field !
Magnetic field above threshold
B > BOP
t
VQ
Magnetic field below threshold
B < BRP
t
VQ
Magnetic field in hysteresis
BOP > B > BRP
t
Figure 2-5
Data Sheet
Illustration of the Start-up Behavior of the TLE4961-2M
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TLE4961-2M
Specification
3
Specification
3.1
Application Circuit
The following Figure 3-1 shows the basic option of an application circuit. Only a pull-up resisotor RQ is necessary.
An external series resistor for Vs is not needed. The resistor RQ has to be in a dimension to match the applied VS
to keep IQ limited to the operating range of maximum 25 mA.
e.g.: VS = 12 V and RQ=1200 Ω gives IQ= 12 V/1200 Ω = 10 mA.
Vs
BDTIC
VDD
TLE496x
R Q = 1.2kΩ
Q
GND
Figure 3-1
Basic Application Circuit #1: Only Pull-Up Resistor is necessary
Vs
CDD = 47nF
TLE496x
VDD
RQ = 1.2kΩ
Q
TVS diode
e.g. ESD24VS2U
GND
Figure 3-2
Enhanced Application Circuit #2: for extended ESD robustness
With an additional capacitor CDD and a transient voltage suppression (TVS) diode an extended ESD robstuness
of 15kV on system level is achieved (Figure 3-2). If an increased robustness for e.g. testpulse 1 is required a serial
resistor in the suppply needs to be added (see also Chapter 3.5).
Data Sheet
12
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TLE4961-2M
Specification
3.2
Absolute Maximum Ratings
Table 3-1
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min.
1)
VDD
Supply voltage
Output voltage
VQ
-0.5
-70
Junction temperature1)
-40
Note / Test Condition
Max.
-18
Reverse output current IQ
TJ
Typ.
Unit
32
42
V
32
V
10h, no external resistor required
mA
155
165
175
195
°C
150
°C
for 2000h (not additive)
for 1000h (not additive)
for 168h (not additive)
for 3 x 1h (additive)
BDTIC
Storage temperature
TS
Thermal resistance
Junction ambient
RthJA
300
K/W
for PG-SOT23-3-15 (2s2p)
Thermal resistance
Junction lead
RthJL
100
K/W
for PG-SOT23-3-15
-40
1) This lifetime statement is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Calculation of the dissipated power PDIS and junction temperature TJ of the chip (SOT23 example):
e.g. for: VDD = 12 V, IS = 2.5 mA, VQSAT = 0.5 V, IQ = 20 mA
Power dissipation: PDIS = 12 V x 2.5 mA + 0.5 V x 20 mA = 30 mW + 10 mW = 40 mW
Temperature ∆T = RthJA x PDIS = 300 K/W x 40 mW = 12 K
For TA = 150 °C: TJ = TA + ∆T = 150 °C + 12 K = 162 °C
Table 3-2
ESD Protection1) (TA = 25°C)
Parameter
Symbol
Values
Unit
Note / Test Condition
kV
R = 1.5 kΩ, C = 100 pF
Min.
2)
VESD
ESD voltage (HBM)
3)
+/- 1
ESD voltage (CDM)
ESD voltage (system level)
1)
2)
3)
4)
+/- 7
4)
+/- 15
with circuit shown in Figure 3-2
Characterization of ESD is carried out on a sample basis, not subject to production test.
Human Body Model (HBM) tests according to ANSI/ESDA/JEDEC JS-001.
Charge device model (CDM) tests according to JESD22-C101.
Gun test (2kΩ / 330pF or 330Ω / 150pF) according to ISO 10605-2008.
Data Sheet
13
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TLE4961-2M
Specification
3.3
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE4961-2M.
All parameters specified in the following sections refer to these operating conditions unless otherwise mentioned.
Table 3-3
Operating Conditions Parameters
Parameter
Symbol
Values
Min.
Typ.
Unit
Note / Test Condition
Max.
Supply voltage
VDD
3.0
321)
V
Output voltage
VQ
-0.3
32
V
Junction temperature
Tj
-40
170
°C
BDTIC
Output current
Magnetic signal input frequency
2)
IQ
0
25
mA
fSW
0
10
kHz
1) Latch-up test with factor 1.5 is not covered. Please see max ratings also.
2) For operation at the maximum switching frequency the magnetic input signal must be 1.4 times higher than for static fields.
This is due to the -3dB corner frequency of the internal low-pass filter in the signal path.
3.4
Electrical and Magnetic Characteristics
Product characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production and correspond to VDD = 12 V and
TA = 25°C. The below listed specification is valid in combination with the application circuit shown in Figure 3-1
and Figure 3-2
Table 3-4
General Electrical Characteristics
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
1.1
1.6
2.5
mA
Note / Test Condition
Supply current
IS
Reverse current
ISR
0.05
1
mA
for VDD = -18 V
Output saturation
voltage
VQSAT
0.2
0.5
V
IQ = 20 mA
0.24
0.6
V
IQ = 25 mA
Output leakage
current
IQLEAK
10
μA
Output current
limitation
IQLIMIT
30
56
70
mA
internally limited & thermal
shutdown
tf
0.17
0.4
1
μs
1.2 kΩ / 50 pF, see Figure 2-3
tr
0.4
0.5
1
μs
1.2 kΩ / 50 pF, see Figure 2-3
0.35
1
μs
For square wave signal with 1 kHz
15
30
μs
see Figure 2-3
150
μs
VDD = 3 V, B ≤ BRP - 0.5 mT or
B ≥ BOP + 0.5 mT
Output fall time1)
1)
Output rise time
1)2)
tQJ
Output jitter
Delay time
1)3)
td
1)4)
12
Power-on time
tPON
80
Chopper frequency1)
fOSC
350
1)
2)
3)
4)
kHz
Not subject to production test, verified by design/characterization.
Output jitter is the 1σ value of the output switching distribution.
Systematic delay between magnetic threshold reached and output switching.
Time from applying VDD = 3.0 V to the sensor until the output is valid.
Data Sheet
14
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TLE4961-2M
Specification
Table 3-5
Magnetic Characteristics
Parameter
Symbol
Operating point
BOP
Release point
BRP
Hysteresis
BHYS
T (°C)
Values
Unit
Min.
Typ.
Max.
-40
3.2
5.7
8.1
25
2.8
5
7.3
170
1.7
3.6
5.4
-40
-8.1
-5.7
-3.2
25
-7.3
-5
-2.8
170
-5.4
-3.6
-1.7
-40
8.5
11.3
14.1
25
7.5
10.0
12.5
170
5.3
7.1
8.9
Note / Test Condition
mT
mT
mT
BDTIC
Effective noise value of the
magnetic switching points1)
BNeff
Temperature compensation of
magnetic thresholds2)
TC
25
62
μT
-2000
ppm/K
1) The magnetic noise is normal distributed and can be assumed as nearly independent to frequency without sampling noise
or digital noise effects. The typical value represents the rms-value and corresponds therefore to a 1 σ probability of normal
distribution. Consequently a 3 σ value corresponds to 99.7% probability of appearance.
2) Not subject to production test, verified by design/characterization.
Field Direction Definition
Positive magnetic fields are defined with the south pole of the magnet to the branded side of package.
N
S
Figure 3-3
Data Sheet
Branded Side
Definition of Magnetic Field Direction PG-SOT23-3-15
15
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TLE4961-2M
Specification
3.5
Electro Magnetic Compatibility
Characterization of Electro Magnetic Compatibility is carried out on a sample basis from one qualification lot. Not
all specification parameters have been monitored during EMC exposure.
+5V
Vs
Rs
RQ = 1.2kΩ
TLE496x
VDD
BDTIC
CDD = 10nF
Q
CQ = 10nF
GND
Figure 3-4
EMC Test Circuit
Ref: ISO 7637-2 (Version 2004), test circuit Figure 3.4 (with external resistor, RS = 100 Ω)
Table 3-6
Magnetic Compatibility
Parameter
Symbol
Level / Type
Status
Testpulse 1
Testpulse 2a1)
Testpulse 2b
Testpulse 3a
Testpulse 3b
Testpulse 42)
Testpulse 5b3)
VEMC
-100 V
60 V/110 V
10 V
-150 V
100 V
-7 V / -5.5 V
US = 86.5 V / US* = 28.5 V
C
A/C
C
A
A
A
A
1) ISO 7637-2 (2004) describes internal resistance = 2 Ω (former 10 Ω).
2) According to 7637-2 for test pulse 4 the test voltage shall be 12 V +/- 0.2 V.
3) A central load dump protection of 42 V is used. Us* = 42 V-13.5 V.
Ref: ISO 7637-2 (Version 2004), test circuit Figure 3.4 (without external resistor, RS = 0Ω)
Table 3-7
Electro Magnetic Compatibility
Parameter
Symbol
Level / Type
Status
Testpulse 1
Testpulse 2a1)
Testpulse 2b
Testpulse 3a
Testpulse 3b
Testpulse 42)
Testpulse 5b3)
VEMC
-50 V
50 V
10 V
-150 V
100 V
-7 V / 5.5 V
US = 86.5 V / US* = 28.5 V
C
A
C
A
A
A
A
1) ISO 7637-2 (2004) describes internal resistance = 2 Ω (former 10 Ω).
2) According to 7637-2 for test pulse 4 the test voltage shall be 12 V +/- 0.2 V.
3) A central load dump protection of 42 V is used. Us* = 42 V-13.5 V.
Data Sheet
16
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TLE4961-2M
Package Information
4
Package Information
The TLE4961-2M is available in the small halogen free SMD package PG-SOT23-3-15.
Package Outline PG-SOT23-3-15
1.3 ±0.1
2.4 ±0.15
3
0.1 MAX.
10° MAX.
B
1 ±0.1
10° MAX.
2.9 ±0.1
0.15 MIN.
4.1
BDTIC
+0.1 1)
0.4 -0.05
1
2
C
0.95
0.08...0.1
5
A
0...8°
1.9
0.2
0.25 M B C
M
A
1) Lead width can be 0.6 max. in dambar area
Figure 4-1
4.2
PG-SOT23-3-15 Package Outline (All Dimensions in mm)
Packing Information PG-SOT23-3-15
4
0.2
8
2.65
2.13
0.9
Pin 1
3.15
1.15
SOT23-TP V02
Figure 4-2
Data Sheet
Packing of the PG-SOT23-3-15 in a Tape
17
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TLE4961-2M
Package Information
4.3
Footprint PG-SC59-3-5 and PG-SOT23-3-15
0.8
1.4 min
0.9
1.6
1.3
0.9
1.4 min
0.8
BDTIC
1.2
0.8
1.2
0.8
Reflow Soldering
Figure 4-3
Footprint PG-SC59-3-5 and PG-SOT23-3-15
PG-SOT23-3-15 Distance between Chip and Package
Figure 4-4
4.5
Distance between Chip and Package
Package Marking
M12
Figure 4-5
Data Sheet
ym
4.4
Wave Soldering
Year (y) = 0...9
Month (m) = 1...9,
o - October
n - November
d - December
Marking of TLE4961-2M
18
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TLE4961-2M
Graphs of the Magnetic Parameters
5
Graphs of the Magnetic Parameters
9,00
8,00
7,00
BOP[mT]
6,00
5,00
Typ
4,00
Min
3,00
Max
2,00
BDTIC
1,00
0,00
50,00
0,00
50,00
100,00
150,00
TA[°C]
Figure 5-1
Operating Point (BOP) of the TLE4961-2M over Temperature
0,00
1,00
2,00
BRP[mT]
3,00
4,00
Typ
5,00
Min
6,00
Max
7,00
8,00
9,00
50,00
0,00
50,00
100,00
150,00
TA[°C]
Figure 5-2
Release Point (BRP) of the TLE4961-2M over Temperature
16,00
14,00
BHys[mT]
12,00
10,00
8,00
Typ
6,00
Min
4,00
Max
2,00
0,00
50,00
0,00
50,00
100,00
150,00
TA[°C]
Figure 5-3
Data Sheet
Hysteresis (BHys) of the TLE4961-2M over Temperature
19
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TLE4961-2M
Graphs of the Electrical Parameters
6
Graphs of the Electrical Parameters
80
75
tPON_max [μs]
70
65
3V
60
55
BDTIC
50
50
30
10
10
30
50
70
90
110
130
150
T[°C]
Figure 6-1
Power On Time tPON of the TLE4961-2M over Temperature
15,5
15
tD [µs]
14,5
14
3V
12V
13,5
13
12,5
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-2
Data Sheet
Signal Delay Time of the TLE4961-2M over Temperature
20
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TLE4961-2M
Graphs of the Electrical Parameters
2
1,9
1,8
Vs=3V
1,7
IS [mA]
1,6
Vs=12V
1,5
Vs=32V
1,4
1,3
Vs=42V
1,2
BDTIC
1,1
1
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-3
Supply Current of the TLE4961-2M over Temperature
2
1,9
1,8
IS [mA]
1,7
1,6
-40°C
1,5
25°C
1,4
150°C
1,3
1,2
1,1
1
0
5
10
15
20
25
30
35
40
45
VS [V]
Figure 6-4
Data Sheet
Supply Current of the TLE4961-2M over Supply Voltage
21
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TLE4961-2M
Graphs of the Electrical Parameters
63,0
62,0
IQLIMIT [mA]
61,0
60,0
5V
59,0
12V
58,0
32V
57,0
56,0
55,0
54,0
50
30
10
10
30
50
70
90
110
130
150
BDTIC
T[°C]
Figure 6-5
Output Current Limit of the TLE4961-2M over Temperature
63,0
62,0
IQLIMIT [mA]
61,0
60,0
40°C
59,0
25°C
58,0
150°C
57,0
56,0
55,0
54,0
0
5
10
15
20
25
30
35
VQ [V]
Figure 6-6
Output Current Limit of the TLE4961-2M over applied Pull-up Voltage
700
600
tf [ns]
500
3V
12V
400
32V
300
200
100
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-7
Data Sheet
Output Fall Time of the TLE4961-2M over Temperature
22
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TLE4961-2M
Graphs of the Electrical Parameters
700
600
tf [ns]
500
-40°C
25°C
400
150°C
300
200
100
0
5
10
15
20
25
30
35
BDTIC
VQ [V]
Figure 6-8
Output Fall Time of the TLE4961-2M over applied Pull-up Voltage
700
600
tr [ns]
3V
12V
500
32V
400
300
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-9
Output Rise Time of the TLE4961-2M over Temperature
700
600
tf [ns]
500
-40°C
25°C
400
150°C
300
200
100
0
5
10
15
20
25
30
35
VQ [V]
Figure 6-10
Data Sheet
Output Rise Time of the TLE4961-2M over applied Pull-up Voltage
23
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TLE4961-2M
Graphs of the Electrical Parameters
10
IQLEAK [µA]
1
32V
0,1
0,01
BDTIC
0,001
80
90
100
110
120
130
140
150
160
170
180
T [°C]
Figure 6-11
Output Leakage Current of the TLE4961-2M over Temperature
400
350
300
VQSAT [mV]
10mA
250
15mA
200
20mA
150
25mA
100
50
0
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-12
Saturation Voltage of the TLE4961-2M over Temperature
400
350
VQSAT [mV]
300
250
-40°C
200
25°C
150°C
150
100
50
0
8
10
12
14
16
18
20
22
24
26
IQ [mA]
Figure 6-13
Data Sheet
Saturation Voltage of the TLE4961-2M over Output Current
24
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TLE4961-2M
Graphs of the Electrical Parameters
120
110
100
BNNeff [µT(rms)]
90
80
70
12V
60
50
40
30
20
BDTIC
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-14
Effective Noise of the TLE4961-2M Thresholds over Temperature
0,8
0,7
tQJ [µs(rms)]
0,6
0,5
0,4
12V
03
0,3
0,2
0,1
0
-50
-30
-10
10
30
50
70
90
110
130
150
T [°C]
Figure 6-15
Data Sheet
Output Signal Jitter of the TLE4961-2M over Temperature
25
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BDTIC
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