BDTIC

CoolS ET ™ F3R80
ICE3AR0680VJZ
BDTIC
30W 12V SMPS e va l uat ion boar d
wit h I CE3AR0 680VJ Z
AN-PS0079
Appl icat ion Not e AN - EVAL- 3AR06 80VJZ
V1.0, 2013-09-23
Po wer Manag em ent & Mult im ar k et
www.BDTIC.com/infineon
BDTIC
Edition 2013-09-23
Published by Infineon Technologies AG,
81726 Munich, Germany.
© 2013 Infineon Technologies AG
All Rights Reserved.
LEGAL DISCLAIMER
THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE
IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE
REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR
QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION
NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON
TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND
(INCLUDING WITHOUT LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN
THIS APPLICATION NOTE.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
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30W 12V SMPS evaluation board with ICE3AR0680VJZ
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Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™,
TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS
Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of
Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems
Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc.
SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software
Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™
of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™
of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
BDTIC
Application Note AN-EVAL-3AR0680VJZ
3
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30W 12V SMPS evaluation board with ICE3AR0680VJZ
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Revision History
Major changes since previous revision
Date
Version
Changed By
Change Description
23 Sep 2013
1.0
Kyaw Zin Min
Release of final version
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of our documentation.
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30W 12V SMPS evaluation board with ICE3AR0680VJZ
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Table of Contents
Revision History .............................................................................................................................................. 4
Table of Contents ............................................................................................................................................ 5
1
Abstract ........................................................................................................................................ 7
2
Evaluation board .......................................................................................................................... 7
3
List of features ............................................................................................................................. 9
4
Technical specifications .............................................................................................................. 9
BDTIC
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Circuit description ..................................................................................................................... 10
Introduction .................................................................................................................................. 10
Line input ..................................................................................................................................... 10
Start up ........................................................................................................................................ 10
Operation mode ........................................................................................................................... 10
Soft start ...................................................................................................................................... 10
RCD clamper circuit ..................................................................................................................... 10
Peak current control of primary current ......................................................................................... 10
Output stage ................................................................................................................................ 10
6
Circuit diagram........................................................................................................................... 11
7
7.1
7.2
PCB layout.................................................................................................................................. 12
Top side ....................................................................................................................................... 12
Bottom side .................................................................................................................................. 12
8
Component list ........................................................................................................................... 13
9
Transformer construction .......................................................................................................... 14
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Test results................................................................................................................................. 15
Efficiency ..................................................................................................................................... 15
Input standby power ..................................................................................................................... 16
Line regulation ............................................................................................................................. 16
Load regulation ............................................................................................................................ 17
Max. output power........................................................................................................................ 17
Electrostatic discharge/ESD test (EN6100-4-2)............................................................................. 17
Surge/Lightning strike test (EN61000-4-5) .................................................................................... 17
Conducted EMI ............................................................................................................................ 18
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
Waveforms and scope plots ...................................................................................................... 20
Start up at low and high AC line input voltage and maximum load................................................. 20
Soft start at low/high AC line input voltage and maximum load...................................................... 20
Frequency jittering........................................................................................................................ 21
Drain voltage and current at maximum load .................................................................................. 21
Load transient response (Dynamic load from 10% to 100%) ......................................................... 22
Output ripple voltage at maximum load......................................................................................... 22
Output ripple voltage during burst mode at 1 W load..................................................................... 23
Entering active burst mode ........................................................................................................... 23
Vcc over voltage protection (Odd skip auto restart mode) ............................................................. 24
Over load protection (Odd skip auto restart mode) ........................................................................ 24
Open loop protection (Odd skip auto restart mode) ....................................................................... 25
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11.12
11.13
VCC under voltage/Short optocoupler protection (Normal auto restart mode) ................................. 25
AC Line input OVP mode ............................................................................................................. 26
12
References ................................................................................................................................. 26
BDTIC
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Abstract
1
Abstract
This document is an engineering report of a universal input 30W 12V off-line flyback converter power supply
utilizing IFX F3R80 CoolSET™ ICE3AR0680VJZ. The application demo board is operated in Discontinuous
Conduction Mode (DCM) and is running at 100 kHz switching frequency. It has a single output voltage with
secondary side control regulation. It is especially suitable for small power supply such as DVD player, set-top
box, game console, charger and auxiliary power of white goods, server, PC and high power system, etc. The
ICE3AR0680VJZ is the latest version of the CoolSET™. Besides having the basic features of the F3R
CoolSET™ such as Active Burst Mode, propagation delay compensation, soft gate drive, auto restart protection
for major fault (Vcc over voltage, Vcc under voltage, over temperature, over-load, open loop and short optocoupler), it also has the BiCMOS technology design, selectable entry and exit burst mode level, adjustable AC
line input over voltage protection feature, built-in soft start time, built-in and extendable blanking time and
frequency jitter feature, etc. The particular features are the best-in-class low standby power and the good EMI
performance.
2
BDTIC
Evaluation board
This document contains the list of features, the power supply specification, schematic, bill of material and the
transformer construction documentation. Typical operating characteristics such as performance curve and
scope waveforms are showed at the rear of the report.
Figure 1A – EVAL3AR0680VJZ [Dimensions L x W x H: 105mm x 52mm x 27mm (4.13" x 2.04" x 1.06")]
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Evaluation board
BDTIC
Figure 1B – EVAL3AR0680VJZ (Top Side)
Figure 1C – EVAL3AR0680VJZ (Bottom Side)
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List of features
3
List of features
800V avalanche rugged CoolSET™ with Startup Cell
Active Burst Mode for lowest Standby Power
Selectable entry and exit burst mode level
100kHz internally fixed switching frequency with jittering feature
Auto Restart Protection for Over load, Open Loop, VCC Under voltage & Over voltage and Over
temperature
Over temperature protection with 50°C hysteresis
Built-in 10ms Soft Start
BDTIC
Built-in 20ms and extendable blanking time for short duration peak power
Propagation delay compensation for both maximum load and burst mode
Adjustable input OVP
Overall tolerance of Current Limiting < ±5%
BiCMOS technology for low power consumption and wide VCC voltage range
Soft gate drive with 50Ω turn on resistor
4
Technical specifications
Input voltage
85Vac~265Vac
Input OVP trigger/reset voltage
300/280Vac
Input frequency
50/60Hz
Input Standby Power
<100mW @ no load
Output voltage
12V +/- 2%
Output current
2.5A
Output power
30W
Active mode average efficiency
>84%
Output ripple voltage
≤ 50mVp-p
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Circuit description
5
Circuit description
5.1
Introduction
The EVAL-3AR0680VJZ demo board is a low cost off-line flyback switch mode power supply (SMPS) using the
ICE3AR0680VJZ integrated power IC from the CoolSET™-F3R80 family. The circuit shown in Figure 3, details
a 12V, 30W power supply that operates from an AC line input voltage range of 85Vac to 265Vac and line input
OVP detect/reset voltage is 300/282Vac, suitable for applications in enclosed adapter or open frame auxiliary
power supply for different system such as white goods, PC, server, DVD, LED TV, Set-top box, etc.
5.2
Line input
The AC line input side comprises the input fuse F1 as over-current protection. The choke L11, X-capacitors
C11, C14 and Y-capacitor C12 act as EMI suppressors. Optional spark gap device SG1, SG2 and varistor VAR
can absorb high voltage stress during lightning surge test. After the bridge rectifier BR1 and the input bulk
capacitor C13, a voltage of 90 to 424 VDC is present which depends on input line voltage.
BDTIC
5.3
Start up
Since there is a built-in startup cell in the ICE3AR0680VJZ, no external start up resistor is required. The startup
cell is connecting the drain pin of the IC. Once the voltage is built up at the Drain pin of the ICE3AR0680VJZ,
the startup cell will charge up the Vcc capacitor C16 and C17. When the Vcc voltage exceeds the UVLO at 17V,
the IC starts up. Then the Vcc voltage is bootstrapped by the auxiliary winding to sustain the operation.
5.4
Operation mode
During operation, the Vcc pin is supplied via a separate transformer winding with associated rectification D12
and buffering C16, C17. In order not to exceed the maximum voltage at Vcc pin due to poor coupling of
transformer winding, an external zener diode ZD11 and resistor R13 can be added.
5.5
Soft start
The Soft-Start is a built-in function and is set at 10ms.
5.6
RCD clamper circuit
®
While turns off the CoolMOS , the clamper circuit R11, C15 and D11 absorbs the current caused by transformer
leakage inductance once the voltage exceeds clamp capacitor voltage. Finally drain to source voltage of
®
CoolMOS™is lower than maximum break down voltage (V(BR)DSS = 800V) of CoolMOS .
5.7
Peak current control of primary current
The CoolMOS™ drain source current is sensed via external shunt resistors R14 and R14A which determine the
tolerance of the current limit control. Since ICE3AR0680VJZ is a current mode controller, it would have a cycleby-cycle primary current and feedback voltage control which can make sure the maximum power of the
converter is controlled in every switching cycle. Besides, the patented propagation delay compensation is
implemented to ensure the maximum input power can be controlled in an even tighter manner. The demo board
shows approximately +/-3.82% (refer to Figure 13).
5.8
Output stage
On the secondary side the power is coupled out by a schottky diode D21. The capacitor C22 & C23 provides
energy buffering following with the LC filter L21 and C24 to reduce the output voltage ripple considerably.
Storage capacitors C22 & C23 are selected to have a very small internal resistance (ESR) to minimize the
output voltage ripple.
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/Circuit diagram
6
Circuit diagram
BDTIC
Figure 3 – 30W 12V ICE3AR0680VJZ power supply schematic
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Application Note AN-EVAL-3AR0680VJZ
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PCB layout
N.B. : In order to get the optimized performance of the CoolSET™, the grounding of the PCB layout must be
connected very carefully. From the circuit diagram above, it indicates that the grounding for the CoolSET™ can
be split into several groups; signal ground, Vcc ground, Current sense resistor ground and EMI return ground.
All the split grounds should be connected to the bulk capacitor ground separately.
Signal ground includes all small signal grounds connecting to the CoolSET™ GND pin such as filter capacitor
ground, C17, C18, C19 and opto-coupler ground.
Vcc ground includes the Vcc capacitor ground, C16 and the auxiliary winding ground, pin 2 of the power
transformer.
Current Sense resistor ground includes current sense resistor R14 and R14A.
EMI return ground includes Y capacitor, C12.
7
PCB layout
BDTIC
7.1
Top side
Figure 4 – Top side component legend
7.2
Bottom side
Figure 5 – Bottom side copper & component legend
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Component list
8
Component list
No.
Designator
Component
Description
1
+12V
Connector
2
BR1
600V/2A
3
4
5
C11
C110
C12
220nF/305V
47pF/1kV
2.2nF/250V,Y1
6
C13
120uF/450V
7
8
9
10
11
12
13
14
C14
C16
C17
C18
C19,C25
C22, C23
C24
C26
100nF/305V
22uF/50V
100nF/50V
470pF/50V
220nF/50V
1000uF/16V
330uF/25V
1nF/50V
15
Com
Connector
16
17
18
19
20
D12
D21
DZD 11
F1
HS1
21
IC11
22
IC12
23
25
26
IC21
J1,J2,J3,
J4,J5
LN
L11
200V/0.2A
100V/30A
145V/200W
250V/1A
HS TO220
ICE3AR0680V
JZ
SFH617
A3(Optocouple
r)
TL431
27
L21
Footprint
Connector(3.
2diameter)
Bridge(2S)
Part Number
Manufacturer
5005
Quantity
1
D2SB60A
SHINDENGEN
1
MKT8/18/15
MKT2/7/5
MKT2/13/10
RB18X31.5H
orizontal
MKT5/18/15
RB5.5
0603
0603
0603
RB10.5
RB8
0603
Connector(3.
2diameter)
DIODE0.3
ITO-220AB
DIODE0.4
MKT4.3/8.4/5
HS TO220
B32922C3224
EPCOS
DE1E3KX222MA4BL01
MURATA
1
1
1
450QXW120MEFC18X31.5
RUBYCON
1
B329221C3104
50PX22MEFC5X11
EPCOS
RUBYCON
GCM1885C1H471FA16
MURATA
25ZL330MEFC8X16
RUBYCON
1
1
1
1
2
2
1
1
BDTIC
24
32
33
34
R12,
R12A
R14,
R14A
R15
R15A,R1
5B
R16
R16A
R22
35
36
R23
R24
28
29
30
31
5006
1
1N485B
VF30100SG
ST02D-140
VISHAY
SHINDENGEN
574502B03300G
AAVID
1
1
1
1
1
DIP7
ICE3AR0680VJZ
INFINEON
1
DIP4
SFH617 A3
1
TO92-TL431-
1
Jumper
AXIAL0.3
5
Connector
39mH/0.7A
Connector
EMI_C_U21
Axial
0.4_V_FB
B82732W2701B030
EPCOS
1
1
2743002111
Fair-Rite
1
3R3
0603
2
1R1/0.5W
1206R
3M
AXIAL0.4_15
1
3M/0.25W
1206R
2
43.2k
0R
820R
0603
0603
0603
1
1
1
1.2k
330k
0603
0603
1
1
ERJB2BF1R1V
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Application Note AN-EVAL-3AR0680VJZ
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Transformer construction
No.
Designator
Component
Description
Footprint
37
38
39
R25
R25A
R26
75k
1k
20k
AXIAL0.3
0603
0603
40
TR1
229µH(30:5:8)
ef25/10h
9
Part Number
Manufacturer
Quantity
2
1
2
750341900
Wurth
Electronics
Midcom
1
Transformer construction
Core and material: EF25/10/6(EF25), TP4A (TDG)
Bobbin: 070-2607(10-Pins, TH-H, Horizontal version)
Primary Inductance, Lp=229μH (±10%), measured between pin 4 and pin 5
Manufacturer and part number: Wurth Electronics Midcom (750341900)
BDTIC
Figure 6 – Transformer structure
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Test results
10
Test results
10.1
Efficiency
BDTIC
Figure 7 – Efficiency vs AC line input voltage
Figure 8 – Efficiency vs output power @ low and high line
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Test results
10.2
Input standby power
BDTIC
Figure 9 – Input standby power @ no load vs AC line input voltage (measured by Yokogawa WT210 power
meter - integration mode)
Figure 10 – Input standby power @ 0.5W, 1W, 2W and 3W vs AC line input voltage ( measured by Yokogawa
WT210 power meter - integration mode )
10.3
Line regulation
Figure 11 – Line regulation Vo @ full load vs AC line input voltage
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Test results
10.4
Load regulation
BDTIC
Figure 12 – Load regulation Vo vs output power
10.5
Max. output power
Figure 13 – Maximum output power (before over-load protection) vs AC line input voltage
10.6
Electrostatic discharge/ESD test (EN6100-4-2)
Pass (Special test voltage ±12kV for contact discharge)
10.7
Surge/Lightning strike test (EN61000-4-5)
Pass (Installation class 3, 2kV for line to earth)
Pass (Installation class 4, 4kV for line to earth by adding 5 ferrite beads EPCOS B64290P0035X038 at Pin 5
of IC11, 2 leads of C12, pin 4 and pin 5 of TR1)
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Test results
10.8
Conducted EMI
The conducted EMI was measured by Schaffner (SMR4503) and followed the test standard of EN55022 (CISPR
22) class B. The demo board was set up at maximum load (30W) with input voltage of 115Vac and 230Vac.
BDTIC
Figure 14 – Max. Load (30W) with 115 Vac (Line)
Figure 15 – Max. Load (30W) with 115 Vac (Neutral)
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Test results
BDTIC
Figure 16 – Max. Load (30W) with 230 Vac (Line)
Figure 17 – Max. Load (30W) with 230 Vac (Neutral)
Pass conducted EMI EN55022 (CISPR 22) class B with > 6dB margin.
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Waveforms and scope plots
11
Waveforms and scope plots
All waveforms and scope plots were recorded with a LeCroy 6050 oscilloscope
11.1
Start up at low and high AC line input voltage and maximum load
400ms
400ms
Entry/exit
burst
selection
Entry/exit
burst
selection
BDTIC
Channel
Channel
Channel
Channel
1; C1 : Drain voltage (VDrain)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Channel
Channel
Channel
Channel
1; C1 : Drain voltage (VDrain)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Startup time = 400ms
Startup time = 400ms
Figure 18 – Startup @ 85Vac & max. load
Figure 19 – Startup @ 265Vac & max. load
11.2
Soft start at low/high AC line input voltage and maximum load
9.7ms
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
9.7ms
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Soft Star time = 9.7ms
Soft Star time = 9.7ms
Figure 20 – Soft Start @ 85Vac & max. load
Figure 21– Soft Start @ 265Vac & max. load
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Waveforms and scope plots
11.3
Frequency jittering
BDTIC
Channel 1; C1 : Drain voltage (VDrain)
Channel F1 : Frequency track of C1
Channel 1; C1 : Drain voltage (VDrain)
Channel F1 : Frequency track of C1
Frequency jittering from 92 kHz ~ 100 kHz, Jitter
period is set at 4ms internally
Frequency jittering from 92kHz ~ 100 kHz, Jitter
period is set at 4ms internally
Figure 22 – Frequency jittering @ 85Vac and max.
load
Figure 23 – Frequency jittering @ 265Vac and
max. load
11.4
Drain voltage and current at maximum load
Channel 1; C1 : Drain voltage (VDrain)
Channel 2; C2 : Drain current (IDrain)
VDrain_peak = 311V
Figure 24 – Operation @ 85Vac and max. load
Channel 1; C1 : Drain voltage (VDrain)
Channel 2; C2 : Drain current (IDrain)
VDrain_peak = 581V
Figure 25 – Operation @ 265Vac and max. load
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Application Note AN-EVAL-3AR0680VJZ
21
V1.0, 2013-09-23
30W 12V SMPS evaluation board with ICE3AR0680VJZ
AN-PS0079
Waveforms and scope plots
11.5
Load transient response (Dynamic load from 10% to 100%)
BDTIC
Channel 1; C1 : Output ripple voltage (Vo)
Channel 2; C2 : Output current (Io)
Vripple_pk_pk=194mV (Load change from10% to
100%,100Hz,0.4A/μS slew rate)
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Channel 1; C1 : Output ripple voltage (Vo)
Channel 2; C2 : Output current (Io)
Vripple_pk_pk=193mV (Load change from10% to
100%,100Hz,0.4A/μS slew rate)
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Figure 26 – Load transient response @ 85Vac
Figure 27 – Load transient response @ 265Vac
11.6
Output ripple voltage at maximum load
Channel 1; C1 : Output ripple voltage (Vo)
Channel 1; C1 : Output ripple voltage (Vo)
Vripple_pk_pk=25mV
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Vripple_pk_pk = 25mV
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Figure 28 – AC output ripple @ 85Vac and max.
load
Figure 29 – AC output ripple @ 282Vac and max.
load
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Application Note AN-EVAL-3AR0680VJZ
22
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30W 12V SMPS evaluation board with ICE3AR0680VJZ
AN-PS0079
Waveforms and scope plots
11.7
Output ripple voltage during burst mode at 1 W load
BDTIC
Channel 1; C1 : Output ripple voltage (Vo)
Channel 1; C1 : Output ripple voltage (Vo)
Vripple_pk_pk=44mV
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Vripple_pk_pk = 51mV
Probe terminal end with decoupling capacitor of
0.1μF(ceramic) & 1μF(Electrolytic), 20MHz filter
Figure 30 – AC output ripple @ 85Vac and 1W
load
Figure 31 – AC output ripple @ 265Vac and 1W
load
11.8
Entering active burst mode
20ms
20ms
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
Blanking time to enter burst mode : 20ms (load step
down from 2.5A to 0.083A)
Figure 32 – Entering active burst mode @ 85Vac
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
Blanking time to enter burst mode : 20ms (load step
down from 2.5A to 0.083A)
Figure 33 – Entering active burst mode @ 265Vac
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Application Note AN-EVAL-3AR0680VJZ
23
V1.0, 2013-09-23
30W 12V SMPS evaluation board with ICE3AR0680VJZ
AN-PS0079
Waveforms and scope plots
11.9
Vcc over voltage protection (Odd skip auto restart mode)
VCC OVP2
VCC OVP2
VCC OVP1
VCC OVP1
BDTIC
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
VCC OVP2 first & follows VCC OVP1 (Jumper 5
disconnected during system operating at no load)
Figure 34 – Vcc overvoltage protection @ 85Vac
11.10
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
VCC OVP2 first & follows VCC OVP1 (Jumper 5
disconnected during system operating at no load)
Figure 35 – Vcc overvoltage protection @ 265Vac
Over load protection (Odd skip auto restart mode)
built-in 20ms blanking
built-in 20ms blanking
extended blanking
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
Over load protection with (built-in+extended)
blanking time =457ms (output load change from
2.5A to 4A)
Figure 36 – Over load protection with extended
blanking time @ 85Vac)
extended blanking
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Supply voltage (VCC)
Channel 3; C3 : Feedback voltage (VFBB)
Channel 4; C4 : BV voltage (VBV)
Over load protection with (built-in+extended)
blanking time =449ms (output load change from
2.5A to 4A)
Figure 37 – Over load protection with extended
blanking time @ 265Vac)
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Application Note AN-EVAL-3AR0680VJZ
24
V1.0, 2013-09-23
30W 12V SMPS evaluation board with ICE3AR0680VJZ
AN-PS0079
Waveforms and scope plots
11.11
Open loop protection (Odd skip auto restart mode)
BDTIC
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Open loop protection (Jumper 5 disconnected
during system operation at max. load) – VCC OVP2
protection
Open loop protection (Jumper 5 disconnected
during system operation at max. load) – VCC OVP2
protection
Figure 38 – Open loop protection @ 85Vac
Figure 39 – Open loop protection @ 265Vac
11.12
VCC under voltage/Short optocoupler protection (Normal auto restart mode)
Exit autorestart
Exit autorestart
Enter autorestart
Channel
Channel
Channel
Channel
Enter autorestart
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV)
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BV voltage (VBV
VCC under voltage/short optocoupler protection
(short the transistor of optocoupler during system
operating @ full load & release)
VCC under voltage/short optocoupler protection
(short the transistor of optocoupler during system
operating @ full load & release)
Figure 40 – Vcc under voltage/short optocoupler
protection @ 85Vac
Figure 41 – Vcc under voltage/short optocoupler
protection @ 265Vac
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Application Note AN-EVAL-3AR0680VJZ
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V1.0, 2013-09-23
30W 12V SMPS evaluation board with ICE3AR0680VJZ
AN-PS0079
References
11.13
AC Line input OVP mode
402Vdc(284Vac)
Exit input OVP
398.7Vdc(282Vac)
Exit input OVP
421.7Vdc(298Vac)
Enter input OVP
422Vdc(298Vac)
Enter input OVP
BDTIC
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Bulk voltage(Vbulk)
4; C4 : BV voltage (VBV)
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Bulk voltage(Vbulk)
4; C4 : BV voltage (VBV)
Input OVP detect: Vbulk= 421.7Vdc(298Vac)
Input OVP reset: Vbulk= 398.7Vdc(282Vac)
Input OVP detect: Vbulk= 422Vdc(298Vac)
Input OVP reset: Vbulk= 402Vdc(284Vac)
Figure 42 – Input OVP mode at max. load condition
Figure 43 – Input OVP mode at no load condition
12
References
[1]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3AR0680VJZ Off-Line SMPS Current Mode
Controller with integrated 800V CoolMOS™and Startup cell( input OVP & Frequency Jitter) in DIP-7”
[2]
Infineon Technologies, AN-PS0044-CoolSET F3R80 DIP-7 brownout/input OVP & frequency jitter version
design guide-V1.5
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Application Note AN-EVAL-3AR0680VJZ
26
V1.0, 2013-09-23
BDTIC
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Published by Infineon Technologies AG