Ho Nam, Antoni Portero, Alberto Scionti, Roberto Giorgi Abstract

A Novel Architecture and Simulation
for Executing Decoupled Threads in
Future 1‑ kilo-core Chips
Ho Nam, Antoni Portero, Alberto Scionti, Roberto Giorgi
T-Star (T*) is an ISA-extension that supports a promising execution model to exploit Thread Level Parallelism
(TLP) in designing for the next generation chip. This model relies on DataFlow principles. A compiler
partitions the program into non-blocking threads which start consuming their own data frames when all their
inputs become ready. Especially for future systems composed of thousands of cores on a single chip, we
believe that this model is very efficient because it allows less synchronization delays among parallel threads.
In this paper we describe some initial works towards simulating 1 kilo-core DataFlow enable chips.
Basic Paradigm for T* Execution:
.c (sequential)
void main() {
int add, mul, c;
int a = 4;
int b = 4;
add = a + b;
mul = a * b;
c = mul/add;
}
3 threads (add,mul
and div) are created
using 3 TCreate >3
frames are allocated
Proposed Simulation Model:
TERAFLUX Architecture:
The simulation model that we propose relies on COTSon
simulation infrastructure, a full-system simulator potentially
supporting the simulation of system at the kilo-cores scale.
Recently, we experimented not only with the AMD’s SimNow but
also with Qsim/Qemu emulator. One of the reasons we want to
replace SimNow is that we need to model the physical global
address space as described above.
COTSon
Timing Simulation
Core 0
…
…
Conclusions:
This paper presents a novel architecture and a simulation framework targeting
future systems composed of on thousand or more cores (i.e., kilo-core chips).
The proposed architecture comes with an extension of the current x86-64 ISA,
and it represents a general model for designing the next generation chips able to
exploit TLP by efficiently scheduling T* instructions execution. The described
simulation model supports this architecture and possibly scales up to a fullsystem simulation with one thousand cores (and more).
Acknowledgments:
This work was partly funded by the European FP7 projects TERAFLUX id.
249013 http://www.teraflux.eu, ERA (Embedded Reconfigurable Architectures)
id. 249059 (FP7) http://era-project.eu; HiPEAC IST-217068, and IT PRIN 2008
(200855LRP2).
DISK
NIC
DISK
NIC
Core n
Core n
HW platform
(ie. 48-cores
256GB-Ram)
MEMORY
Core 0
CACHE
HIERARC.
CACHE
HIERARC.
Qsim/Qemu
Functional Emulation
MEMORY
Computer Architecture Group - DII
Abstract:
Event
Queues
Nodes
We modify Qemu which emulates
a node with a physical memory
device (i.e., DRAM block) to see
more physical memory devices
from other nodes.
We also integrate T* architectural
support in Qemu to model T*
instructions execution.
References:
1]. Shekhar Borkar, Thousand Core Chips: A Technology Perspective, Proceedings of the 44th annual Design Automation Conference, (DAC’ 07), June 4-8, 2007, San Diego, California, USA.
[2]. R. Giorgi, Z. Popovic, N. Puzovic, DTA-C: A Decoupled multi-threaded Architecture for CMP Systems, Proceedings of IEEE SBAC-PAD, Gramado, Brazil, Oct. 2007, pp. 263-270.
[3]. R. Giorgi, TERAFLUX: exploiting dataflow parallelism in teradevices, Proceedings CF '12 Proceedings of the 9th conference on Computing Frontiers, pp. 303-304.
[4]. http://www.teraflux.eu/
[5]. Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi, Simulating the Future kilo-x86-64 core Processors and
their Infrastructure, 45th Annual Simulation Symp. (ANSS12), Orlando, FL, Mar. 2012.
[6]. http://www.l4ka.org/
[7]. Eduardo Argollo, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega, COTSon: infrastructure for full system simulation, ACM SIGOPS Operating Systems, vol. 43 Issue 1, Jan. 2009, pp. 52-61.
[8]. Roberto Giorgi, Alberto Scionti, Antoni Portero Paolo Faraboschi, Architectural Simulation in the Kilo-core Era, Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), London,
UK, Mar. 2012, pp. 1-3.
Department of Information Engineering, University of Siena
Address: Via Roma, 56 53100 Siena – Italy
Tel:+39 0577 23 4850 (int. 1085)
Fax: +39 0577 233.609
Website: http://www.dii.unisi.it/