slides

Ralph Otten
complexity and diversity
in ic layout design
october 1980
single metal layer chips
• my thesis in 1976 was about
embedding a planarized circuit graph onto a bipolar carrier
– 1. convert the schematic into an annotated potential graph
– 2. use technological tricks to planarize the graph[M. van Lier]
– 3. generate a rectangle dissection with component assignment
– 4. map the plane graph onto the carrier
• features
– an uninterrupted flow
from schematic to layout
– adopt the footprint
and embed from the outside
– to ensure completion
use tearing lines
• observations
– plenty of space -> no tearing
– especially easy when slicing
iteration free synthesis
hierarchy =
set of hierarchies
structural restraint for efficiency
textual layout notations
gradual module stiffening
HIERARCHY
HIERARCHY
SLICING
T-CONSTRAINT
CONSTRAINT CYCLES
SLICING
TEXTUAL FORM
JACOPINI CONTROL FLOW CONSTRUCTS
SCOPE MINIMIZATION
SCOPE MINIMIZATION
SCOPE MINIMIZATION
Ralph Otten
complexity and diversity
in ic layout design
october 1980
GENEALOGIZE
GENEALOGIZE
GENEALOGIZE
GENEALOGIZE
GENEALOGIZE
GENEALOGIZE
PROCREATE
PROCREATE
PROCREATE
SAGA
the genealogical approach
to layout synthesis
SAGA
Giuliano de Medici
(1453-1478)
SAGA
Giuliano de Medici
(1453-1478)
SAGA
Piero
il gottoso
(1418-1469)
Giuliano de Medici
(1453-1478)
SAGA
Cosimo
pater patriae
(1389-1464)
Piero
il gottoso
(1418-1469)
Giuliano de Medici
(1453-1478)
Giovanni di Bicci de Medici
(1360-1429)
SAGA
Cosimo
pater patriae
(1389-1464)
Piero
il gottoso
(1418-1469)
Giuliano de Medici
(1453-1478)
Giovanni di Bicci de Medici
(1360-1429)
SAGA
Cosimo
pater patriae
(1389-1464)
Piero
il gottoso
(1418-1469)
Lorenzo
(1394-1440)
Pierfrancesco
(1431-1477)
Giuliano de Medici Lorenzo
il popolano
(1453-1478)
(1463-1503)
Giovanni
il popolano
(1467-1498)
Giovanni di Bicci de Medici
(1360-1429)
SAGA
Cosimo
pater patriae
(1389-1464)
Piero
il gottoso
(1418-1469)
Lorenzo
il magnifico
(1449-1492)
Lorenzo
(1394-1440)
Pierfrancesco
(1431-1477)
Giuliano de Medici Lorenzo
il popolano
(1453-1478)
(1463-1503)
Pietro
Giovanni
Giuliano
lo sfortunato
(Leo X)
of Nemours
(1471-1503) (1475-1521) (1478-1516)
Giovanni
il popolano
(1467-1498)
Giovanni di Bicci de Medici
(1360-1429)
SAGA
Cosimo
pater patriae
(1389-1464)
Piero
il gottoso
(1418-1469)
Lorenzo
il magnifico
(1449-1492)
Giovanni
(1421-1463)
Lorenzo
(1394-1440)
Pierfrancesco
(1431-1477)
Giuliano de Medici Lorenzo
il popolano
(1453-1478)
(1463-1503)
Giovanni
il popolano
(1467-1498)
Pietro
Giovanni
Giuliano
Pierfrancesco Averardo Vincenzo
lo sfortunato
(Leo X)
of Nemours (1431-1477)
(1471-1503) (1475-1521) (1478-1516)
silicon compilation
floorplan
silicon compilation
floorplan =
a data structure
that captures relative positions
Ralph Otten
complexity and diversity
in ic layout design
october 1980
WIRING
STRUCTURES
WIRING STRUCTURES
WIRING STRUCTURES
WIRING STRUCTURES
WIRING STRUCTURES
wire space inflation
buffers, optical receivers, i.o
Si
polyimide
SiO2 + Al
processor, first level cache
Si
polyimide
SiO2 + Al
second level cache interfaces
Si
polyimide
SiO2 + Al
advanced memory technology
Si
optical clock receivers,
line repeaters,
regular i/o [Otten,1980]
processors
(the main heat source),
first level memory
second level cache
for performance improvement
[M.B. Kleiner, S.A.Kühn, P. Ramm,
W.Weber, 1995]
high density
advanced
memory technology
Ralph Otten
complexity and diversity
in ic layout design
april 2016