IP101A BANDGAP RESISTOR 50MHz CLOCK OUT

5
4
DVDD33
3
U1
MDC
MDIO
TXD0
TXD1
50MHz CLOCK OUT
Generate by IP101A
DVDD33
25
26
6
5
4
3
TX_EN
2
REFCLK_IP101A 7
CRS_DV
22
RXD0
21
RXD1
20
19
18
16
COL/RMII
1
23
RX_ER
24
X1_INPUT
46
X2_OUTPUT
47
P3 REFCLK_IP101A
50MHz_CLKOUT
P3 50MHz_CLKOUT
R3
5.1k
Set IP101A
to RMII Mode
R4
5.1k
AVDD33
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TX_EN
REF_CLK
CRS_DV
RXD0
RXD1
RXD2
RXD3
C50M_O
COL
CRS/LEDMOD
RX_ER
X1
X2
DVDD33
5.1k INT
*
P3 PHYAD0/LED0
P3 PHYAD1/LED1
P3 PHYAD2/LED2
P3 PHYAD3/LED3
P3 PHYAD4/LED4
C
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
use 25M crystal
X2_OUTPUT
14
48
DVDD33
INTR
9
10
12
13
15
PHYAD0/LED0
PHYAD1/LED1
PHYAD2/LED2
PHYAD3/LED3
PHYAD4/LED4
11
17
45
DGND
DGND
DGND
X1_INPUT
AVDD33
REGIN
REGOUT
AVDD33
REGIN
REGOUT
36
8
32
AGND
AGND
29
35
ISET
28
MDI_RP
MDI_RN
31
30
MDI_RP
MDI_RN
MDI_TN
MDI_TP
33
34
MDI_TN
MDI_TP
TEST_ON
27
AN_ENA
DPLX
SPD
RPTR
APS
ISOL
MII/SNIB
37
38
39
40
41
43
44
RESET_N
42
IP101A
DVDD33
R5
1
R1
5.1K
D
2
REGOUT P2
D
BANDGAP
RESISTOR
JP1
R2
6.19K/1%
1
AN_ENA
DPLX
SPD
RPTR
APS
ISOL
MII/SNIB
1
2
3
4
5
6
7
8
9
10
MDI_RP P2
MDI_RN P2
MDI_TN P2
MDI_TP P2
TP1
1
1
1
1
1
1
1
MDIO
MDC
RXD1
RXD0
CRS_DV
RX_ER
TX_EN
TXD0
TXD1
COL/RMII
HEADER 10
TP2
TP3
TP4
TP5
TP6
TP7
TP8
RMII Signals
C
Hardwire Configuration network:
IP101A LQFP48
Y1
R6
33R
Pin48 could be short VDD33 if
interrupt funtion is not
used.
25MHZ
C1
C2
30pF
30pF
JP2
1
2
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, RMII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be connected
to VDD or GND directly.
RESET_N
R7
0
HEADER 2/SM
RESET_N
R9
0
DVDD33
CRYSTAL
as close as to chip
R8
470K
C3
0.1U
B
B
VDD33
L1
MLB-160808-1000A-N2, 1.0ohm, 100mA
AVDD33
VDD33
P2 REGOUT
REGOUT
0R
+
C9
0.1uF
REGIN
0R
+
C5
0.1uF
C4
22uF
C6
0.1uF
C7
0.01uF
**
C10
0.1uF
As close to IP101A
Pin36 as possible
R10
**
L3
MLB-160808-0450B-N3, 0.5ohm, 100mA
L2
C8
10uF
DVDD33
As close to IP101A
Pin32 as possible
As close to IP101A
Pin14 as possible
A
As close to IP101A
Pin8 as possible
** Bead should be placed as close to IP101A
as possible and in the same side as IP101A.
A
IC Plus Semiconductor Corporation
Title
Size
B
Date:
5
4
* : Optional ,but recommended
3
www.BDTIC.com/ICplus
2
IP101A
Chip Circuit Diagram
Document Number
RMII UTP
Wednesday, April 30, 2008
Sheet
1
1
of
3
Rev
5
4
3
2
1
D
D
C11
.1u
C12
1n/2KV/1206
R11
49.9(1%)
R12
49.9(1%)
U2
U3
P1 MDI_RN
C
8
RD-
RX-
9
7
CT
CT
10
RD+
RX+
11
P1 MDI_RP
6
P1 MDI_TN
3
TD-
TX-
14
2
CT
CT
15
TD+
TX+
16
1
P1 MDI_TP
*
TS8121C
R13
R14
49.9(1%) 49.9(1%)
C13
1n/2KV/1206
1
TX+
2
TX-
3
RX+
4
N/C
5
N/C
6
RX-
7
N/C
8
N/C
*
C
GND
9
RJ8-45
R15
75
R16
75
R17
75
R18
75
C14
.1u
C15
R19
0
B
R20
0
*
Only 1 resister is needed
if 2 CT of transformer
have been shorted inside.
REGOUT
*
C16
C17
0.01U
0.1U
*
C18
0.01U
*
B
1n/2KV/1206
REGOUT P1
C19
0.1U
IC Plus Semiconductor Corporation
A
A
Title
5
4
IP101A Chip Circuit Diagram
www.BDTIC.com/ICplus
3
Size
A
Document Number
Date:
Wednesday, April 30, 2008
RMII UTP
2
Sheet
2
of
1
3
Rev
5
4
DC 5V INPUT ONLY
3
2
VDD5V
1
LED and PHY address Configuration
L4
BEAD
CN1
+5V
3
1
2
D
R21
POWERJACK
This schematic sets PHY address to
00001b.
330R
D1
DIODE
DVDD33
Z1
RLED
L5
BEAD
R22
P1 PHYAD0/LED0
R23
5.1K
D2
510 ohm
"Voltage 3.3V"
VDD5V
U4
3
VIN
1
ADJ(GND)
C
+
C20
220uF
D
LT1086CT
VOUT
2
OUT
4
LED
R24
VDD33
P1 PHYAD1/LED1
L6
1U, 50-100OHM@100-1000MHZ
3.3V
D3
5.1K
R25
C
+
C21
220uF
510 ohm
LED
C22
10nF
C23
0.1uF
R26
P1 PHYAD2/LED2
R27
D4
110R/1%
LED
R29
182R/1%
5.1K
R28
510 ohm
R30
P1 PHYAD3/LED3
D5
5.1K
LED
R31
510 ohm
R32
CLOCK generate by IP101A
P1 PHYAD4/LED4
B
B
D6
5.1K
R33
UZ1
P1 50MHz_CLKOUT
DVDD33
A
2
4
6
8
1A0
1A1
1A2
1A3
1Y0
1Y1
1Y2
1Y3
18
16
14
12
17
15
13
2A0
2A1
2A2
2Y0
2Y1
2Y2
3
5
7
1
19
1OE
2OE
20
VCC
GND
RZ1
0
RZ2
0
REFCLK_OUT
510 ohm
JP3
LED0
Link
1
2
LED1
Dupx
LED2
10Act
LED3
100Act
LED4
COL
HEADER 2/SM
REFCLK_OUT
There could be more than 2
output REFCLK(50MHz) when
using buffer 74LV244.
10
74LV244
5
LED
REFCLK_IP101A P1
4
IC Plus Semiconductor Corporation
Title
IP101A Chip Circuit Diagram
www.BDTIC.com/ICplus
3
A
Size
A
Document Number
Date:
Wednesday, April 30, 2008
RMII UTP
2
Sheet
3
of
1
3
Rev