FDC6321C Dual N & P Channel , Digital FET

April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
Features
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
N-Ch 25 V, 0.68 A, RDS(ON) = 0.45 Ω @ VGS= 4.5 V
P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 Ω @ VGS= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. VGS(th) < 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOIC-16
SOT-223
Mark:.321
D2
S1
D1
G2
4
3
5
2
6
1
S2
SuperSOT TM -6
G1
Absolute Maximum Ratings
TA = 25oC unless other wise noted
Symbol
Parameter
N-Channel
P-Channel
Units
VDSS, VCC
Drain-Source Voltage, Power Supply Voltage
25
-25
V
VGSS, VIN
Gate-Source Voltage,
8
-8
V
ID, IO
Drain/Output Current
0.68
-0.46
A
2
-1.5
- Continuous
- Pulsed
PD
Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Tempature Ranger
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
0.9
W
0.7
-55 to 150
°C
6
kV
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
140
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
60
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC6321C.RevB
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Type
Min
VGS = 0 V, ID = 250 µA
N-Ch
25
VGS = 0 V, ID = -250 µA
P-Ch
-25
ID= 250 µA, Referenced to 25 oC
N-Ch
26
ID = -250 µA, Referenced to 25 oC
P-Ch
-22
N-Ch
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
IDSS
Zero Gate Voltage Drain Current
VDS= 20 V, VGS= 0 V,
IDSS
Zero Gate Voltage Drain Current
VDS =-20 V, VGS = 0 V,
IGSS
Gate - Body Leakage Current
V
mV /oC
1
TJ = 55°C
µA
10
P-Ch
-1
VGS = 8 V, VDS= 0 V
N-Ch
100
nA
VGS = -8 V, VDS= 0 V
P-Ch
-100
nA
ID = 250 µA, Referenced to 25 o C
N-Ch
TJ = 55°C
µA
-10
ON CHARACTERISTICS (Note 2)
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp. Coefficient
VGS(th)
Gate Threshold Voltage
RDS(ON)
Static Drain-Source On-Resistance
ID= -250 µA, Referenced to 25 o C
P-Ch
VDS = VGS, ID = 250 µA
N-Ch
0.65
0.8
VDS = VGS, ID= -250 µA
P-Ch
-0.65
-0.86
-1.5
VGS = 4.5 V, ID = 0.5 A
N-Ch
0.33
0.45
0.51
0.72
2.1
TJ =125°C
VGS = 2.7 V, ID = 0.25A
VGS = -4.5 V, ID = -0.5 A
P-Ch
TJ =125°C
VGS = -2.7 V, ID = -0.25 A
ID(ON)
On-State Drain Current
gFS
Forward Transconductance
mV / oC
-2.6
VGS = 4.5 V, VDS = 5 V
1.5
0.44
0.6
0.87
1.1
1.21
1.8
1.22
1.5
N-Ch
1
VGS = -4.5 V, VDS = -5 V
P-Ch
-1
VDS = 5 V, ID= 0.5 A
N-Ch
1.45
VDS = -5 V, ID= -0.5 A
P-Ch
0.8
N-Channel
N-Ch
50
VDS= 10 V, VGS= 0 V,
P-Ch
63
f = 1.0 MHz
N-Ch
28
P-Channel
P-Ch
34
VDS= -10 V, VGS = 0V,
N-Ch
9
f = 1.0 MHz
P-Ch
10
V
Ω
A
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
pF
pF
pF
FDC6321C.RevB
Electrical Characteristics (TA = 25 OC unless otherwise noted )
SWITCHING CHARACTERISTICS (Note 2)
Symbol
Parameter
Conditions
Type
tD(on)
Turn - On Delay Time
N-Channel
N-Ch
VDD = 6 V, ID = 0.5 A,
P-Ch
VGs = 4.5 V, RGEN = 50 Ω
tr
tD(off)
tf
Qg
Qgs
Qgd
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Min
Typ
Max
Units
3
6
nS
7
20
N-Ch
8
16
P-Ch
9
18
P-Channel
N-Ch
17
30
VDD = -6 V, ID = -0.5 A,
P-Ch
55
110
VGen = -4.5 V, RGEN = 50 Ω
N-Ch
13
25
P-Ch
35
70
N-Channel
N-Ch
1.64
2.3
VDS= 5 V, ID = 0.5 A,
P-Ch
1.1
1.5
VGS = 4.5 V
N-Ch
0.38
P- Channel
P-Ch
0.32
VDS = -5 V,
N-Ch
0.45
ID = -0.25 A, VGS = -4.5 V
P-Ch
0.25
nS
nS
nS
nC
nC
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
VSD
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.5 A
(Note)
VGS = 0 V, IS = -0.5 A
(Note)
N-Ch
0.3
P-Ch
-0.5
N-Ch
0.83
1.2
0.69
0.85
P-Ch
-0.89
-1.2
-0.75
-0.85
TJ =125°C
TJ =125°C
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where thecase thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
FDC6321C.RevB
Typical Electrical Characteristics: N-Channel
2
VGS = 4.5V
2.5
3.5
3.0
2.7
1.2
R DS(on) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
I D , DRAIN-SOURCE CURRENT (A)
1.5
2.0
0.9
0.6
1.5
0.3
VGS = 2.0V
1.5
2.5
2.7
3.5
4.5
1
0.5
0
0
0.5
1
1.5
0
2
0.2
0.4
VDS , DRAIN-SOURCE VOLTAGE (V)
0.8
1
2
ID= 0.5A
I D =0.5 A
VGS = 4.5 V
R DS(on) , ON-RESISTANCE (OHM)
1.4
1.2
1
0.8
0.6
-50
1.2
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
R DS(ON) , NORMALIZED
0.6
I D , DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
DRAIN-SOURCE ON-RESISTANCE
3.0
-25
0
25
50
75
100
125
150
1.6
1.2
0.8
125°C
25°C
0.4
0
1
1.5
2
2.5
3
3.5
4
4.5
5
VGS , GATE TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (°C)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On Resistance Variation with
Gate-To-Source Voltage.
1
TJ = -55°C
1
25°C
IS , REVERSE DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
V DS = 5.0V
0.8
125°C
0.6
0.4
0.2
0
0
0.5
1
1.5
2
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
2.5
V GS = 0V
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
FDC6321C.RevB
Typical Electrical Characteristics: N-Channel (continued)
VGS , GATE-SOURCE VOLTAGE (V)
5
150
VDS = 5V
I D = 0.5A
100
10V
4
CAPACITANCE (pF)
15V
3
2
Coss
20
f = 1 MHz
V GS = 0V
10
1
C rss
5
0.1
0
0
0.4
0.8
1.2
1.6
2
DS
Figure 7. Gate Charge Characteristics.
0.03
0.01
0.1
2
5
10
25
5
10
1m 0µs
s
10
ms
DC
1s
10
0m
s
V GS = 4.5V
SINGLE PULSE
R θJA = See note 1b
TA = 25°C
0.2
0.5
1
SINGLE PULSE
RθJA =See note 1b
TA = 25°C
4
POWER (W)
IT
IM
)L
ON
(
S
RD
0.3
0.1
1
, DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance Characteristics.
5
1
0.5
V
Q g , GATE CHARGE (nC)
I D , DRAIN CURRENT (A)
Ciss
50
3
2
1
2
5
10
20
VDS , DRAI N-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
40
0
0.01
0.1
1
10
100
300
SINGLE PULSE TIME (SEC)
Figure 10. Single Pulse Maximum Power
Dissipation.
FDC6321C.RevB
Typical Electrical Characteristics: P-Channel
2.4
VGS = -4.5V
-3.5 -3.0
1.25
R DS(ON) , NORMALIZED
-2.7
-2.5
1
0.75
-2.0
0.5
0.25
-1.5
DRAIN-SOURCE ON-RESISTANCE
-ID , DRAIN-SOURCE CURRENT (A)
1.5
2.2
2
1.6
0
1
2
3
4
-2.5
-2.7
1.4
-3.0
-3.5
1.2
-4.0
1
0.8
0
V GS= -2.0 V
1.8
5
0
0.2
0.8
1
Figure 12. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
5
I D = -0.5A
R DS(on) , ON-RESISTANCE (OHM)
RDS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE (OHMS)
Figure 11. On-Region Characteristics.
V GS = -4.5V
1.4
1.2
1
0.8
0.6
-50
ID=-0.5A
25°C
4
125°C
3
2
1
0
-25
0
25
50
75
100
125
-1
150
-1.5
-2
Figure 13. On-Resistance Variation
with Temperature.
0.5
-0.75
-I S , REVERSE DRAIN CURRENT (A)
T = -55°C
J
-3
-3.5
-4
-4.5
-5
Figure 14. On Resistance Variation with
Gate-To- Source Voltage.
-1
V DS = -5 V
-2.5
V GS , GATE TO SOURCE VOLTAGE (V)
T J, JUNCTION TEMPERATURE (°C)
ID , DRAIN CURRENT (A)
0.6
-I D , DRAIN CURRENT (A)
-VDS , DRAIN-SOURCE VOLTAGE (V)
25°C
125°C
-0.5
-0.25
0
-0.5
0.4
-4.5
VGS = 0V
0.1
TJ = 125°C
25°C
0.01
-55°C
0.001
0.0001
-1
-1.5
-2
-2.5
V GS, GATE TO SOURCE VOLTAGE (V)
Figure 15. Transfer Characteristics.
-3
0
0.2
0.4
0.6
0.8
1
1.2
-VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 16. Body Diode Forward Voltage
Variation with Source Current and
Temperature.
FDC6321C.RevB
Typical Electrical Characteristics: P-Channel (continued)
150
VDS = -5V
-10V
-15V
I D = -0.5A
4
100
Ciss
CAPACITANCE (pF)
-V GS , GATE-SOURCE VOLTAGE (V)
5
3
2
50
Coss
20
10
1
5
0.1
0
0
0.3
0.6
0.9
1.2
1.5
1.8
0.3
1
5
10
15
25
Figure 18. Capacitance Characteristics.
Figure 17. Gate Charge Characteristics.
2
5
1m
s
10
m
s
1
S
)L
IM
IT
0.1
0.03
VGS = -4.5V
SINGLE PULSE
RθJA = See Note 1b
A T = 25°C
A
0.01
0.1
0.2
0.5
1
SINGLE PULSE
RθJA =See note 1b
TA = 25°C
4
10
0m
s
1s
POWER (W)
RD
N
(O
DC
3
2
1
2
5
10
20
0
0.01
40
0.1
- VDS , DRAIN-SOURCE VOLTAGE (V)
1
10
100
300
SINGLE PULSE TIME (SEC)
Figure 19. Maximum Safe Operating Area.
Figure 20. Single Pulse Maximum Power
Dissipation.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
-I D , DRAIN CURRENT (A)
0.5
-V DS, DRAIN TO SOURCE VOLTAGE (V)
Q g , GATE CHARGE (nC)
0.3
Crss
f = 1 MHz
V GS = 0 V
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
0.0001
RθJA (t) = r(t) * R θJA
R θJA = See Note 1b
0.1
P(pk)
0.05
t1
0.02
0.01
Single Pulse
0.001
t2
TJ - TA = P * R θJA(t)
Duty Cycle, D = t 1 / t 2
0.01
0.1
1
10
100
300
t 1, TIME (sec)
Figure 21. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
FDC6321C.RevB
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
TinyLogic™
UHC™
VCX™
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.