Virtex-5 FPGA GTX Transceiver OC-48 Protocol Standard

Virtex-5 FPGA
GTX Transceiver
OC-48 Protocol
Standard
Characterization Report
RPT116 (v1.0) February 23, 2010
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Revision History
The following table shows the revision history for this document.
Date
Version
02/23/10
1.0
Revision
Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OC-48 Electrical Characterization Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Near-End Output Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
7
7
8
8
9
10
10
10
11
11
13
14
14
16
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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6
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Virtex-5 FPGA GTX Transceiver
OC-48 Protocol Standard
Introduction
This characterization report compares the electrical performance of the Virtex®-5 FPGA
RocketIO™ GTX transceiver against the GR-253-CORE standard [Ref 1]. Synchronous
Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are a set of
related standards for synchronous data transmission over fiber optic networks. SONET
links are traditionally used in the telecommunication industry. The applicable test
specifications are found in GR-253, International Telecommunication Union
Telecommunication Standardization Sector (ITU-T) G.783 [Ref 2], and ITU-T G.957 [Ref 3].
The specifications are written for optical signals. Thus, a reference optical device is used in
the test setup. The characterization is performed as per specifications at a data rate of
2.488 Gb/s across voltage, temperature, and worst-case transceiver performance corners.
The following tests are included in this report:
•
Transmitter Output Jitter
•
Receiver Jitter Tolerance
Test Conditions
Table 1 and Table 2 show the supply voltage and temperature conditions, respectively.
Table 1:
Supply Voltage Test Conditions
Condition
MGTAVCC
(V)
MGTAVCCPLL
(V)
MGTAVTTRX
(V)
MGTAVTTTX
(V)
VMIN
0.95
0.95
1.14
1.14
VMAX
1.05
1.05
1.26
1.26
Notes:
1. Other FPGA voltages remain at their nominal values.
Table 2:
Temperature Test Conditions
Condition
Temperature
(°C)
T-40
–40
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Transceiver Selection
Table 2:
Temperature Test Conditions (Cont’d)
Condition
Temperature
(°C)
T0
0
T100
100
Transceiver Selection
As part of the transceiver selection process, volume generic transceiver characterization is
first performed across process, voltage, and temperature (PVT). The generic data from this
characterization can be found in Virtex-5 FPGA RocketIO GTX Transceiver Characterization
Report [Ref 4]. Protocol-specific characterization is then performed using representative
transceivers from generic characterization. The chosen transceivers represent a mixture of
worst-case and typical performance transmitters and receivers. Transceivers with the
absolute worst-case transmitter output jitter and receiver jitter tolerance are selected from
the corner silicon used during generic volume characterization. The histograms in this
characterization report are therefore skewed towards worst-case performance and do not
contain a true statistical representation of the entire population.
Summary of Results
Table 3 shows a comparison of the GTX transceiver using two reference clock rates:
311.04 MHz and 155.52 MHz. The data reported in Table 3 represents the worst-case
voltage, temperature, and performance corners tested.
Table 3:
OC-48 Characterization: Summary of Results
Test
Parameter
Specification
(P2P) (1)
Test Results for
311.04 MHz
REFCLK (P2P)
Test Results for
155.52 MHz
REFCLK (P2P)
Units
Compliant
Transmitter
Output Jitter (2)
HP1 + LP
0.1
0.057
0.083
UI
Yes
Receiver Jitter
Tolerance (3)
HP1 + LP
0.3
0.375
0.375
UI
Yes
HP2 + LP
0.1
0.375
0.375
UI
Yes
Notes:
1. P2P is peak to peak.
2. Tests were run for 60 seconds as per the ITU-T Recommendation G.2851.
3. The jitter tolerance tester is limited at 0.375 UI.
Table 3 uses standard SONET terminology for filters: HP, HP1, HP2, and LP. These values
are described in Figure 1 and Table 4.
8
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OC-48 Electrical Characterization Details
X-Ref Target - Figure 1
100.00
Jitter Generate Mask
Jitter Tolerance Mask
10.00
HP1
1.00
UI
HP2
0.10
HP
LP
0.01
1
102
10
103
104
105
106
107
Frequency (Hz)
Figure 1:
Table 4:
108
RPT116_01_013009
OC-48 Jitter Tolerance and Generation Filter Specifications
SONET Filter Description
Parameter
Specification
HP
12 KHz
HP1
6 KHz
HP2
1 MHz
LP
20 MHz
OC-48 Electrical Characterization Details
This section contains the detailed OC-48 test methodology and results of each test
summarized in Table 3. The GTX transceiver is configured using version 1.5 of the
RocketIO GTX Wizard, including attribute settings. GTX transceiver attribute settings that
differ from the GTX Wizard default settings are identified in Table 6, Table 7, page 12, and
Table 9, page 15 for each test.
Table 5 shows the phase-locked loop (PLL) settings for OC-48 characterization for
311.04 MHz and 155.52 MHz REFCLKs.
Table 5:
2.488 Gb/s Line Rate PLL Settings
Data Rate
(Gb/s)
PLL
Frequency
(GHz)
REFCLK
Frequency
(MHz)
PLL_DIVSEL_REF
PLL_DIVSEL_FB and
DIV
PLL_TXDIVSEL_OUT and
PLL_RXDIVSEL_OUT
2.488
2.488
311.04
1
2×4=8
2
2.488
2.488
155.52
1
4 × 4 = 16
2
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OC-48 Electrical Characterization Details
Transmitter Near-End Output Eye
This section details the test methodology and results of the transmitter near-end
output eye.
Test Methodology
The FPGA is configured to transmit a received pattern on the TX data pins, and the
resulting eye is captured using an Agilent DSA91304A infiniium high-performance
oscilloscope for 1,000 samples at nominal voltage and room temperature.
Table 6 details the test setup and conditions.
Table 6:
Transmitter Near-End Output Eye Test Setup and Conditions
Parameter
Value
Load Board
ML523 characterization platform, revision D (FF1136)
Measurement Instrument
Agilent DSA91304A infiniium high-performance
oscilloscope: 13 GHz
Pattern
OTN bulk PRBS23
Temperature
Room temperature
TX Amplitude/Pre-Emphasis
Maximum amplitude, TXDIFFCTRL = 111
TX Coupling
AC coupled using DC blocks
Voltage
Nominal
Test Results
Figure 2 and Figure 3 show the transmitter near-end output eye at 2.488 Gb/s with
311.04 MHz and 155.52 MHz REFCLKs, respectively.
X-Ref Target - Figure 2
RPT116_02_011509
Figure 2:
10
TX Near-End Output Eye (2.488 Gb/s with 311.04 MHz REFCLK)
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OC-48 Electrical Characterization Details
X-Ref Target - Figure 3
RPT116_03_011509
Figure 3:
TX Near-End Output Eye (2.488 Gb/s with 155.52 MHz REFCLK)
Transmitter Output Jitter
This section details the transmitter output jitter test methodology and test results.
Test Methodology
Transmitter output jitter data was collected using the test setup shown in Figure 4. A JDSU
ONT-506 optical network tester was used to collect the output jitter data. To obtain the
appropriate reference clock rate for the GTX transceiver under test, the bit rate clock
supplied by the JDSU optical network tester was divided down by factors of eight
(311.04 MHz REFCLK) and sixteen (155.52 MHz REFCLK) using the Agilent 81134A pulse
pattern generator.
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OC-48 Electrical Characterization Details
X-Ref Target - Figure 4
Agilent E3631A 0–6V, 5A / 0–±25V, 1A
JDSU ONT-506
Electrical
Connection
Display
Adjust
TxClk
Voltage/Current
Function
TxData
On/Off
RxClk
+
6V
-
-
+ 25V
+ -COM -
GPIB Addr = 6
MGTAVTT Power Supply
RxData
Optical
Connection
Agilent E3631A 0–6V, 5A / 0–±25V, 1A
TxData
1550
Display
Adjust
TxData
1310
RxData
Voltage/Current
Function
1550
On/Off
RxData
+
6V
-
-
+ 25V
+ -COM -
GPIB Addr = 5
1310
MGTAVTT Power Supply
81134A 3.35 GHz Pulse/Pattern Generator
GPIB Addr = 13
Start Input
Display
Keyboard and
Miscellaneous
Buttons
Trigger Out
Xilinx
SMA-SFP
RXN RXP TXP TXN
Clock Input
Channel 2
TXP
TXN
RXP
RXN
AVCCPLL
1.0V
Channel 1
Output
Output
MGTAVCC
1.0V
Channel 1
Output
Output
AVTTTX
1.2V
SMA Matched Pair Cables for GT Receiver
SMA Matched Pair Cables for GT Transmitter
SMA Matched Pair Cables for GT Clocks
SC to LC Fibre Cable, Single Mode
Cable for 1.0V Power Supply
Cable for 1.2V Power Supply
Cable for Ground Power Supply
DC Blocks
50Ω Termination
CLKN
Virtex-5
FPGA
AVTTRX
1.2V
CLKP
Channel 1
GND
ML523 Virtex-5 FPGA DUT Board
RPT116_04_010410
Figure 4:
OC-48 Transmitter Output Jitter Test Setup
Table 7 details the test setup and conditions.
Table 7:
OC-48 Transmitter Output Jitter Test Setup and Conditions
Parameter
12
Value
Load Board
ML523 characterization platform, revision D (FF1136)
Measurement Instrument
JDSU ONT-506 optical network tester BN 3061/90.27
Optical to SFP Board
FiberOn FTM-3128C-SL2G
Pattern
OTN bulk PRBS23
REFCLK
311.04 MHz: JDSU bit rate clock divided by 8
155.52 MHz: JDSU bit rate clock divided by 16
Temperature
T-40, T0, T100
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OC-48 Electrical Characterization Details
Table 7:
OC-48 Transmitter Output Jitter Test Setup and Conditions (Cont’d)
Parameter
Value
TX Amplitude/Pre-Emphasis
GTX transceiver attributes:
• TXDIFFCTRL = 000
• TXBUFDIFFCTRL = 101
• TXPREEMPHASIS = 0000
TX Coupling
AC coupled using DC blocks
Voltage
VMIN, VMAX
Test Results
Figure 5 and Figure 6 show the output jitter test results for 311.04 MHz and 155.52 MHz
REFCLKs, respectively, using an OTN bulk PRBS23 pattern. Due to mechanical limitations,
the measurement is taken with 4 to 6.8 inches of FR4 between the TXP/TXN FPGA pins
and the SMA connectors on the ML523 characterization platform. The added FR4 channel
contributes additional ISI (deterministic jitter) when tested with an OTN bulk PRBS23
pattern, artificially increasing the measured output jitter.
X-Ref Target - Figure 5
Number of Datapoints
20
18
16
14
12
10
8
6
4
2
0
0.0300 0.0400 0.0500 0.0600 0.0700 0.0800 0.0900
TJ (UI)
Figure 5:
RPT116_05_012709
OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23)
Using 311.04 MHz REFCLK
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OC-48 Electrical Characterization Details
X-Ref Target - Figure 6
Number of Datapoints
18
16
14
12
10
8
6
4
2
0
0.0300 0.0400 0.0500 0.0600 0.0700 0.0800 0.0900
TJ (UI)
Figure 6:
RPT116_06_012709
OC-48 Transmitter Output Jitter Test Results (OTN Bulk PRBS23)
Using 155.52 MHz REFCLK
Table 8 summarizes the results of the transmitter output jitter characterization.
Table 8:
Summary of OC-48 Transmitter Output Jitter Characterization (1)
Parameter
HP1 + LP
Test Results Test Results for Test Results for Test Results for
Specification
for 311.04 MHz
311.04 MHz
155.52 MHz
155.52 MHz
Units Compliant
(P2P)
REFCLK (P2P) REFCLK (RMS) REFCLK (P2P) REFCLK (RMS)
0.1
0.057
0.0053
0.083
0.0079
UI
Yes
Notes:
1. Tests were run for 60 seconds as per the specification.
Receiver Jitter Tolerance
This section details the receiver jitter tolerance test methodology and test results.
Test Methodology
Receiver jitter tolerance was measured using the test setup shown in Figure 4, page 12. The
JDSU optical network tester generates an SDH frame using a PRBS23 pattern. The GTX
transceiver under test recovers the data and transmits the pattern back to the error detector
input of the optical network tester where bit errors are measured. To obtain the appropriate
reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the
JDSU optical network tester is divided down by factors of eight (311.04 MHz REFCLK) and
sixteen (155.52 MHz REFCLK) using the Agilent 81134A pulse pattern generator. Eye
diagrams are generated using the Agilent DSA91304A oscilloscope.
14
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OC-48 Electrical Characterization Details
Figure 7 shows a screen capture of the jitter injected to the GTX transceiver under test for
OC-48 testing.
X-Ref Target - Figure 7
RPT116_08_011509
Figure 7:
OC-48 Eye Diagram of OTN Bulk PRBS23 Pattern
Table 9 details the test setup and conditions.
Table 9:
OC-48 Receiver Jitter Tolerance Test Setup and Conditions
Parameter
Value
Load Board
ML523 characterization platform, revision D (FF1136)
Measurement Instrument
JDSU ONT-506 optical network tester BN 3061/90.27
Optical Module
FiberOn FTM-3128C-SL2G
Optical to SFP Board
Xilinx® HW-AFX-SMA-SFP, Rev. A
Pattern
OTN Bulk PRBS23
REFCLK
311.04 MHz: JDSU bit rate clock divided by 8
155.52 MHz: JDSU bit rate clock divided by 16
RX Coupling
AC coupled using DC blocks
Temperature
T-40, T0, T100
Voltage
VMIN, VMAX
Table 10 lists filter parameter specifications.
Table 10:
OC-48 Jitter Tolerance Filter Description
Parameter
Specification
HP1
6 KHz
HP2
1 MHz
LP
20 MHz
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References
Test Results
Table 11 and Figure 8 show the results of jitter tolerance for both 311.04 MHz and
155.52 MHz REFCLKs at the worst-case voltage, temperature, and performance corners.
Table 11:
Summary of OC-48 Receiver Jitter Tolerance Characterization
Parameter
Specification
(P2P)
Test Results for 311.04 MHz
REFCLK (P2P)
Test Results for 155.52 MHz
REFCLK (P2P)
Units
Compliant
HP1 + LP
0.3
0.375
0.375
UI
Yes
HP2 + LP
0.1
0.375
0.375
UI
Yes
Notes:
1. The tolerance of the GTX transceiver devices exceeded the 0.375 UI limit of the jitter tolerance tester.
X-Ref Target - Figure 8
1000.00
Jitter Tolerance
Mask
100.00
UI
10.00
1.00
0.10
0.01
1
10
102
103
104
105
106
107
Frequency (Hz)
Figure 8:
108
RPT116_08_013009
JItter Tolerance Results for Both 311.04 MHz and 155.52 MHz REFCLKs
References
This characterization report uses the following references:
16
1.
GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic
Criteria, Telcordia Technologies, Inc., http://telecom-info.telcordia.com/sitecgi/ido/newcust.pl?page=idosearch&docnum=GR-253.
2.
ITU-T G.783, Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional
Blocks, International Telecommunication Union,
http://www.itu.int/rec/T-REC-G.783-200603-I/en.
3.
ITU-T G.957, Optical Interfaces for Equipments and Systems Relating to the Synchronous Digital
Hierarchy, International Telecommunication Union,
http://www.itu.int/rec/T-REC-G.957-200603-I/en.
4.
RPT109, Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report.
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